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ralink: add 3.14 support
[openwrt/openwrt.git] / target / linux / ramips / patches-3.14 / 0030-pinctrl-ralink-add-pinctrl-driver.patch
1 From 675c6ddd9432c39f508f9d6bdda17d9c675788cf Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sun, 27 Jul 2014 09:34:05 +0100
4 Subject: [PATCH 30/57] pinctrl: ralink: add pinctrl driver
5
6 Signed-off-by: John Crispin <blogic@openwrt.org>
7 ---
8 arch/mips/Kconfig | 2 +
9 arch/mips/include/asm/mach-ralink/mt7620.h | 41 ++-
10 arch/mips/include/asm/mach-ralink/pinmux.h | 53 ++++
11 arch/mips/include/asm/mach-ralink/rt305x.h | 35 ++-
12 arch/mips/include/asm/mach-ralink/rt3883.h | 16 +-
13 arch/mips/ralink/common.h | 19 --
14 arch/mips/ralink/mt7620.c | 159 +++-------
15 arch/mips/ralink/rt288x.c | 62 ++--
16 arch/mips/ralink/rt305x.c | 151 ++++-----
17 arch/mips/ralink/rt3883.c | 173 +++--------
18 drivers/pinctrl/Kconfig | 5 +
19 drivers/pinctrl/Makefile | 1 +
20 drivers/pinctrl/pinctrl-rt2880.c | 467 ++++++++++++++++++++++++++++
21 13 files changed, 764 insertions(+), 420 deletions(-)
22 create mode 100644 arch/mips/include/asm/mach-ralink/pinmux.h
23 create mode 100644 drivers/pinctrl/pinctrl-rt2880.c
24
25 diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
26 index 95fa1f1..4ac98ca 100644
27 --- a/arch/mips/Kconfig
28 +++ b/arch/mips/Kconfig
29 @@ -435,6 +435,8 @@ config RALINK
30 select CLKDEV_LOOKUP
31 select ARCH_HAS_RESET_CONTROLLER
32 select RESET_CONTROLLER
33 + select PINCTRL
34 + select PINCTRL_RT2880
35
36 config SGI_IP22
37 bool "SGI IP22 (Indy/Indigo2)"
38 diff --git a/arch/mips/include/asm/mach-ralink/mt7620.h b/arch/mips/include/asm/mach-ralink/mt7620.h
39 index c8590df..1976fb8 100644
40 --- a/arch/mips/include/asm/mach-ralink/mt7620.h
41 +++ b/arch/mips/include/asm/mach-ralink/mt7620.h
42 @@ -90,7 +90,6 @@ enum mt762x_soc_type {
43 #define MT7620_DDR2_SIZE_MIN 32
44 #define MT7620_DDR2_SIZE_MAX 256
45
46 -#define MT7620_GPIO_MODE_I2C BIT(0)
47 #define MT7620_GPIO_MODE_UART0_SHIFT 2
48 #define MT7620_GPIO_MODE_UART0_MASK 0x7
49 #define MT7620_GPIO_MODE_UART0(x) ((x) << MT7620_GPIO_MODE_UART0_SHIFT)
50 @@ -102,16 +101,36 @@ enum mt762x_soc_type {
51 #define MT7620_GPIO_MODE_GPIO_UARTF 0x5
52 #define MT7620_GPIO_MODE_GPIO_I2S 0x6
53 #define MT7620_GPIO_MODE_GPIO 0x7
54 -#define MT7620_GPIO_MODE_UART1 BIT(5)
55 -#define MT7620_GPIO_MODE_MDIO BIT(8)
56 -#define MT7620_GPIO_MODE_RGMII1 BIT(9)
57 -#define MT7620_GPIO_MODE_RGMII2 BIT(10)
58 -#define MT7620_GPIO_MODE_SPI BIT(11)
59 -#define MT7620_GPIO_MODE_SPI_REF_CLK BIT(12)
60 -#define MT7620_GPIO_MODE_WLED BIT(13)
61 -#define MT7620_GPIO_MODE_JTAG BIT(15)
62 -#define MT7620_GPIO_MODE_EPHY BIT(15)
63 -#define MT7620_GPIO_MODE_WDT BIT(22)
64 +
65 +#define MT7620_GPIO_MODE_NAND 0
66 +#define MT7620_GPIO_MODE_SD 1
67 +#define MT7620_GPIO_MODE_ND_SD_GPIO 2
68 +#define MT7620_GPIO_MODE_ND_SD_MASK 0x3
69 +#define MT7620_GPIO_MODE_ND_SD_SHIFT 18
70 +
71 +#define MT7620_GPIO_MODE_PCIE_RST 0
72 +#define MT7620_GPIO_MODE_PCIE_REF 1
73 +#define MT7620_GPIO_MODE_PCIE_GPIO 2
74 +#define MT7620_GPIO_MODE_PCIE_MASK 0x3
75 +#define MT7620_GPIO_MODE_PCIE_SHIFT 16
76 +
77 +#define MT7620_GPIO_MODE_WDT_RST 0
78 +#define MT7620_GPIO_MODE_WDT_REF 1
79 +#define MT7620_GPIO_MODE_WDT_GPIO 2
80 +#define MT7620_GPIO_MODE_WDT_MASK 0x3
81 +#define MT7620_GPIO_MODE_WDT_SHIFT 21
82 +
83 +#define MT7620_GPIO_MODE_I2C 0
84 +#define MT7620_GPIO_MODE_UART1 5
85 +#define MT7620_GPIO_MODE_MDIO 8
86 +#define MT7620_GPIO_MODE_RGMII1 9
87 +#define MT7620_GPIO_MODE_RGMII2 10
88 +#define MT7620_GPIO_MODE_SPI 11
89 +#define MT7620_GPIO_MODE_SPI_REF_CLK 12
90 +#define MT7620_GPIO_MODE_WLED 13
91 +#define MT7620_GPIO_MODE_JTAG 15
92 +#define MT7620_GPIO_MODE_EPHY 15
93 +#define MT7620_GPIO_MODE_PA 20
94
95 static inline int mt7620_get_eco(void)
96 {
97 diff --git a/arch/mips/include/asm/mach-ralink/pinmux.h b/arch/mips/include/asm/mach-ralink/pinmux.h
98 new file mode 100644
99 index 0000000..324fa40
100 --- /dev/null
101 +++ b/arch/mips/include/asm/mach-ralink/pinmux.h
102 @@ -0,0 +1,53 @@
103 +/*
104 + * This program is free software; you can redistribute it and/or modify
105 + * it under the terms of the GNU General Public License version 2 as
106 + * publishhed by the Free Software Foundation.
107 + *
108 + * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
109 + */
110 +
111 +#ifndef _RT288X_PINMUX_H__
112 +#define _RT288X_PINMUX_H__
113 +
114 +#define FUNC(name, value, pin_first, pin_count) { name, value, pin_first, pin_count }
115 +#define GRP(_name, _func, _mask, _shift) \
116 + { .name = _name, .mask = _mask, .shift = _shift, \
117 + .func = _func, .gpio = _mask, \
118 + .func_count = ARRAY_SIZE(_func) }
119 +
120 +#define GRP_G(_name, _func, _mask, _gpio, _shift) \
121 + { .name = _name, .mask = _mask, .shift = _shift, \
122 + .func = _func, .gpio = _gpio, \
123 + .func_count = ARRAY_SIZE(_func) }
124 +
125 +struct rt2880_pmx_group;
126 +
127 +struct rt2880_pmx_func {
128 + const char *name;
129 + const char value;
130 +
131 + int pin_first;
132 + int pin_count;
133 + int *pins;
134 +
135 + int *groups;
136 + int group_count;
137 +
138 + int enabled;
139 +};
140 +
141 +struct rt2880_pmx_group {
142 + const char *name;
143 + int enabled;
144 +
145 + const u32 shift;
146 + const char mask;
147 + const char gpio;
148 +
149 + struct rt2880_pmx_func *func;
150 + int func_count;
151 +};
152 +
153 +extern struct rt2880_pmx_group *rt2880_pinmux_data;
154 +
155 +#endif
156 diff --git a/arch/mips/include/asm/mach-ralink/rt305x.h b/arch/mips/include/asm/mach-ralink/rt305x.h
157 index 069bf37..96f731b 100644
158 --- a/arch/mips/include/asm/mach-ralink/rt305x.h
159 +++ b/arch/mips/include/asm/mach-ralink/rt305x.h
160 @@ -125,24 +125,29 @@ static inline int soc_is_rt5350(void)
161 #define RT305X_GPIO_GE0_TXD0 40
162 #define RT305X_GPIO_GE0_RXCLK 51
163
164 -#define RT305X_GPIO_MODE_I2C BIT(0)
165 -#define RT305X_GPIO_MODE_SPI BIT(1)
166 #define RT305X_GPIO_MODE_UART0_SHIFT 2
167 #define RT305X_GPIO_MODE_UART0_MASK 0x7
168 #define RT305X_GPIO_MODE_UART0(x) ((x) << RT305X_GPIO_MODE_UART0_SHIFT)
169 -#define RT305X_GPIO_MODE_UARTF 0x0
170 -#define RT305X_GPIO_MODE_PCM_UARTF 0x1
171 -#define RT305X_GPIO_MODE_PCM_I2S 0x2
172 -#define RT305X_GPIO_MODE_I2S_UARTF 0x3
173 -#define RT305X_GPIO_MODE_PCM_GPIO 0x4
174 -#define RT305X_GPIO_MODE_GPIO_UARTF 0x5
175 -#define RT305X_GPIO_MODE_GPIO_I2S 0x6
176 -#define RT305X_GPIO_MODE_GPIO 0x7
177 -#define RT305X_GPIO_MODE_UART1 BIT(5)
178 -#define RT305X_GPIO_MODE_JTAG BIT(6)
179 -#define RT305X_GPIO_MODE_MDIO BIT(7)
180 -#define RT305X_GPIO_MODE_SDRAM BIT(8)
181 -#define RT305X_GPIO_MODE_RGMII BIT(9)
182 +#define RT305X_GPIO_MODE_UARTF 0
183 +#define RT305X_GPIO_MODE_PCM_UARTF 1
184 +#define RT305X_GPIO_MODE_PCM_I2S 2
185 +#define RT305X_GPIO_MODE_I2S_UARTF 3
186 +#define RT305X_GPIO_MODE_PCM_GPIO 4
187 +#define RT305X_GPIO_MODE_GPIO_UARTF 5
188 +#define RT305X_GPIO_MODE_GPIO_I2S 6
189 +#define RT305X_GPIO_MODE_GPIO 7
190 +
191 +#define RT305X_GPIO_MODE_I2C 0
192 +#define RT305X_GPIO_MODE_SPI 1
193 +#define RT305X_GPIO_MODE_UART1 5
194 +#define RT305X_GPIO_MODE_JTAG 6
195 +#define RT305X_GPIO_MODE_MDIO 7
196 +#define RT305X_GPIO_MODE_SDRAM 8
197 +#define RT305X_GPIO_MODE_RGMII 9
198 +#define RT5350_GPIO_MODE_PHY_LED 14
199 +#define RT5350_GPIO_MODE_SPI_CS1 21
200 +#define RT3352_GPIO_MODE_LNA 18
201 +#define RT3352_GPIO_MODE_PA 20
202
203 #define RT3352_SYSC_REG_SYSCFG0 0x010
204 #define RT3352_SYSC_REG_SYSCFG1 0x014
205 diff --git a/arch/mips/include/asm/mach-ralink/rt3883.h b/arch/mips/include/asm/mach-ralink/rt3883.h
206 index 058382f..0fbe6f9 100644
207 --- a/arch/mips/include/asm/mach-ralink/rt3883.h
208 +++ b/arch/mips/include/asm/mach-ralink/rt3883.h
209 @@ -112,8 +112,6 @@
210 #define RT3883_CLKCFG1_PCI_CLK_EN BIT(19)
211 #define RT3883_CLKCFG1_UPHY0_CLK_EN BIT(18)
212
213 -#define RT3883_GPIO_MODE_I2C BIT(0)
214 -#define RT3883_GPIO_MODE_SPI BIT(1)
215 #define RT3883_GPIO_MODE_UART0_SHIFT 2
216 #define RT3883_GPIO_MODE_UART0_MASK 0x7
217 #define RT3883_GPIO_MODE_UART0(x) ((x) << RT3883_GPIO_MODE_UART0_SHIFT)
218 @@ -125,11 +123,15 @@
219 #define RT3883_GPIO_MODE_GPIO_UARTF 0x5
220 #define RT3883_GPIO_MODE_GPIO_I2S 0x6
221 #define RT3883_GPIO_MODE_GPIO 0x7
222 -#define RT3883_GPIO_MODE_UART1 BIT(5)
223 -#define RT3883_GPIO_MODE_JTAG BIT(6)
224 -#define RT3883_GPIO_MODE_MDIO BIT(7)
225 -#define RT3883_GPIO_MODE_GE1 BIT(9)
226 -#define RT3883_GPIO_MODE_GE2 BIT(10)
227 +
228 +#define RT3883_GPIO_MODE_I2C 0
229 +#define RT3883_GPIO_MODE_SPI 1
230 +#define RT3883_GPIO_MODE_UART1 5
231 +#define RT3883_GPIO_MODE_JTAG 6
232 +#define RT3883_GPIO_MODE_MDIO 7
233 +#define RT3883_GPIO_MODE_GE1 9
234 +#define RT3883_GPIO_MODE_GE2 10
235 +
236 #define RT3883_GPIO_MODE_PCI_SHIFT 11
237 #define RT3883_GPIO_MODE_PCI_MASK 0x7
238 #define RT3883_GPIO_MODE_PCI (RT3883_GPIO_MODE_PCI_MASK << RT3883_GPIO_MODE_PCI_SHIFT)
239 diff --git a/arch/mips/ralink/common.h b/arch/mips/ralink/common.h
240 index 42dfd61..8e7d8e6 100644
241 --- a/arch/mips/ralink/common.h
242 +++ b/arch/mips/ralink/common.h
243 @@ -11,25 +11,6 @@
244
245 #define RAMIPS_SYS_TYPE_LEN 32
246
247 -struct ralink_pinmux_grp {
248 - const char *name;
249 - u32 mask;
250 - int gpio_first;
251 - int gpio_last;
252 -};
253 -
254 -struct ralink_pinmux {
255 - struct ralink_pinmux_grp *mode;
256 - struct ralink_pinmux_grp *uart;
257 - int uart_shift;
258 - u32 uart_mask;
259 - void (*wdt_reset)(void);
260 - struct ralink_pinmux_grp *pci;
261 - int pci_shift;
262 - u32 pci_mask;
263 -};
264 -extern struct ralink_pinmux rt_gpio_pinmux;
265 -
266 struct ralink_soc_info {
267 unsigned char sys_type[RAMIPS_SYS_TYPE_LEN];
268 unsigned char *compatible;
269 diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c
270 index e590ccf..818a7db 100644
271 --- a/arch/mips/ralink/mt7620.c
272 +++ b/arch/mips/ralink/mt7620.c
273 @@ -17,6 +17,7 @@
274 #include <asm/mipsregs.h>
275 #include <asm/mach-ralink/ralink_regs.h>
276 #include <asm/mach-ralink/mt7620.h>
277 +#include <asm/mach-ralink/pinmux.h>
278
279 #include "common.h"
280
281 @@ -47,118 +48,58 @@ enum mt762x_soc_type mt762x_soc;
282 /* does the board have sdram or ddram */
283 static int dram_type;
284
285 -static struct ralink_pinmux_grp mode_mux[] = {
286 - {
287 - .name = "i2c",
288 - .mask = MT7620_GPIO_MODE_I2C,
289 - .gpio_first = 1,
290 - .gpio_last = 2,
291 - }, {
292 - .name = "spi",
293 - .mask = MT7620_GPIO_MODE_SPI,
294 - .gpio_first = 3,
295 - .gpio_last = 6,
296 - }, {
297 - .name = "uartlite",
298 - .mask = MT7620_GPIO_MODE_UART1,
299 - .gpio_first = 15,
300 - .gpio_last = 16,
301 - }, {
302 - .name = "wdt",
303 - .mask = MT7620_GPIO_MODE_WDT,
304 - .gpio_first = 17,
305 - .gpio_last = 17,
306 - }, {
307 - .name = "mdio",
308 - .mask = MT7620_GPIO_MODE_MDIO,
309 - .gpio_first = 22,
310 - .gpio_last = 23,
311 - }, {
312 - .name = "rgmii1",
313 - .mask = MT7620_GPIO_MODE_RGMII1,
314 - .gpio_first = 24,
315 - .gpio_last = 35,
316 - }, {
317 - .name = "spi refclk",
318 - .mask = MT7620_GPIO_MODE_SPI_REF_CLK,
319 - .gpio_first = 37,
320 - .gpio_last = 39,
321 - }, {
322 - .name = "jtag",
323 - .mask = MT7620_GPIO_MODE_JTAG,
324 - .gpio_first = 40,
325 - .gpio_last = 44,
326 - }, {
327 - /* shared lines with jtag */
328 - .name = "ephy",
329 - .mask = MT7620_GPIO_MODE_EPHY,
330 - .gpio_first = 40,
331 - .gpio_last = 44,
332 - }, {
333 - .name = "nand",
334 - .mask = MT7620_GPIO_MODE_JTAG,
335 - .gpio_first = 45,
336 - .gpio_last = 59,
337 - }, {
338 - .name = "rgmii2",
339 - .mask = MT7620_GPIO_MODE_RGMII2,
340 - .gpio_first = 60,
341 - .gpio_last = 71,
342 - }, {
343 - .name = "wled",
344 - .mask = MT7620_GPIO_MODE_WLED,
345 - .gpio_first = 72,
346 - .gpio_last = 72,
347 - }, {0}
348 +static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 1, 2) };
349 +static struct rt2880_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) };
350 +static struct rt2880_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 15, 2) };
351 +static struct rt2880_pmx_func mdio_grp[] = { FUNC("mdio", 0, 22, 2) };
352 +static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 24, 12) };
353 +static struct rt2880_pmx_func refclk_grp[] = { FUNC("spi refclk", 0, 37, 3) };
354 +static struct rt2880_pmx_func ephy_grp[] = { FUNC("ephy", 0, 40, 5) };
355 +static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 60, 12) };
356 +static struct rt2880_pmx_func wled_grp[] = { FUNC("wled", 0, 72, 1) };
357 +static struct rt2880_pmx_func pa_grp[] = { FUNC("pa", 0, 18, 4) };
358 +static struct rt2880_pmx_func uartf_grp[] = {
359 + FUNC("uartf", MT7620_GPIO_MODE_UARTF, 7, 8),
360 + FUNC("pcm uartf", MT7620_GPIO_MODE_PCM_UARTF, 7, 8),
361 + FUNC("pcm i2s", MT7620_GPIO_MODE_PCM_I2S, 7, 8),
362 + FUNC("i2s uartf", MT7620_GPIO_MODE_I2S_UARTF, 7, 8),
363 + FUNC("pcm gpio", MT7620_GPIO_MODE_PCM_GPIO, 11, 4),
364 + FUNC("gpio uartf", MT7620_GPIO_MODE_GPIO_UARTF, 7, 4),
365 + FUNC("gpio i2s", MT7620_GPIO_MODE_GPIO_I2S, 7, 4),
366 };
367 -
368 -static struct ralink_pinmux_grp uart_mux[] = {
369 - {
370 - .name = "uartf",
371 - .mask = MT7620_GPIO_MODE_UARTF,
372 - .gpio_first = 7,
373 - .gpio_last = 14,
374 - }, {
375 - .name = "pcm uartf",
376 - .mask = MT7620_GPIO_MODE_PCM_UARTF,
377 - .gpio_first = 7,
378 - .gpio_last = 14,
379 - }, {
380 - .name = "pcm i2s",
381 - .mask = MT7620_GPIO_MODE_PCM_I2S,
382 - .gpio_first = 7,
383 - .gpio_last = 14,
384 - }, {
385 - .name = "i2s uartf",
386 - .mask = MT7620_GPIO_MODE_I2S_UARTF,
387 - .gpio_first = 7,
388 - .gpio_last = 14,
389 - }, {
390 - .name = "pcm gpio",
391 - .mask = MT7620_GPIO_MODE_PCM_GPIO,
392 - .gpio_first = 11,
393 - .gpio_last = 14,
394 - }, {
395 - .name = "gpio uartf",
396 - .mask = MT7620_GPIO_MODE_GPIO_UARTF,
397 - .gpio_first = 7,
398 - .gpio_last = 10,
399 - }, {
400 - .name = "gpio i2s",
401 - .mask = MT7620_GPIO_MODE_GPIO_I2S,
402 - .gpio_first = 7,
403 - .gpio_last = 10,
404 - }, {
405 - .name = "gpio",
406 - .mask = MT7620_GPIO_MODE_GPIO,
407 - }, {0}
408 +static struct rt2880_pmx_func wdt_grp[] = {
409 + FUNC("wdt rst", 0, 17, 1),
410 + FUNC("wdt refclk", 0, 17, 1),
411 + };
412 +static struct rt2880_pmx_func pcie_rst_grp[] = {
413 + FUNC("pcie rst", MT7620_GPIO_MODE_PCIE_RST, 36, 1),
414 + FUNC("pcie refclk", MT7620_GPIO_MODE_PCIE_REF, 36, 1)
415 +};
416 +static struct rt2880_pmx_func nd_sd_grp[] = {
417 + FUNC("nand", MT7620_GPIO_MODE_NAND, 45, 15),
418 + FUNC("sd", MT7620_GPIO_MODE_SD, 45, 15)
419 };
420
421 -struct ralink_pinmux rt_gpio_pinmux = {
422 - .mode = mode_mux,
423 - .uart = uart_mux,
424 - .uart_shift = MT7620_GPIO_MODE_UART0_SHIFT,
425 - .uart_mask = MT7620_GPIO_MODE_UART0_MASK,
426 +static struct rt2880_pmx_group mt7620a_pinmux_data[] = {
427 + GRP("i2c", i2c_grp, 1, MT7620_GPIO_MODE_I2C),
428 + GRP("uartf", uartf_grp, MT7620_GPIO_MODE_UART0_MASK,
429 + MT7620_GPIO_MODE_UART0_SHIFT),
430 + GRP("spi", spi_grp, 1, MT7620_GPIO_MODE_SPI),
431 + GRP("uartlite", uartlite_grp, 1, MT7620_GPIO_MODE_UART1),
432 + GRP_G("wdt", wdt_grp, MT7620_GPIO_MODE_WDT_MASK,
433 + MT7620_GPIO_MODE_WDT_GPIO, MT7620_GPIO_MODE_WDT_SHIFT),
434 + GRP("mdio", mdio_grp, 1, MT7620_GPIO_MODE_MDIO),
435 + GRP("rgmii1", rgmii1_grp, 1, MT7620_GPIO_MODE_RGMII1),
436 + GRP("spi refclk", refclk_grp, 1, MT7620_GPIO_MODE_SPI_REF_CLK),
437 + GRP_G("pcie", pcie_rst_grp, MT7620_GPIO_MODE_PCIE_MASK,
438 + MT7620_GPIO_MODE_PCIE_GPIO, MT7620_GPIO_MODE_PCIE_SHIFT),
439 + GRP_G("nd_sd", nd_sd_grp, MT7620_GPIO_MODE_ND_SD_MASK,
440 + MT7620_GPIO_MODE_ND_SD_GPIO, MT7620_GPIO_MODE_ND_SD_SHIFT),
441 + GRP("rgmii2", rgmii2_grp, 1, MT7620_GPIO_MODE_RGMII2),
442 + GRP("wled", wled_grp, 1, MT7620_GPIO_MODE_WLED),
443 + GRP("ephy", ephy_grp, 1, MT7620_GPIO_MODE_EPHY),
444 + GRP("pa", pa_grp, 1, MT7620_GPIO_MODE_PA),
445 + { 0 }
446 };
447
448 static struct rt2880_pmx_func pwm1_grp_mt7628[] = {
449 diff --git a/arch/mips/ralink/rt288x.c b/arch/mips/ralink/rt288x.c
450 index 90e8934..2bfc660 100644
451 --- a/arch/mips/ralink/rt288x.c
452 +++ b/arch/mips/ralink/rt288x.c
453 @@ -17,46 +17,27 @@
454 #include <asm/mipsregs.h>
455 #include <asm/mach-ralink/ralink_regs.h>
456 #include <asm/mach-ralink/rt288x.h>
457 +#include <asm/mach-ralink/pinmux.h>
458
459 #include "common.h"
460
461 -static struct ralink_pinmux_grp mode_mux[] = {
462 - {
463 - .name = "i2c",
464 - .mask = RT2880_GPIO_MODE_I2C,
465 - .gpio_first = 1,
466 - .gpio_last = 2,
467 - }, {
468 - .name = "spi",
469 - .mask = RT2880_GPIO_MODE_SPI,
470 - .gpio_first = 3,
471 - .gpio_last = 6,
472 - }, {
473 - .name = "uartlite",
474 - .mask = RT2880_GPIO_MODE_UART0,
475 - .gpio_first = 7,
476 - .gpio_last = 14,
477 - }, {
478 - .name = "jtag",
479 - .mask = RT2880_GPIO_MODE_JTAG,
480 - .gpio_first = 17,
481 - .gpio_last = 21,
482 - }, {
483 - .name = "mdio",
484 - .mask = RT2880_GPIO_MODE_MDIO,
485 - .gpio_first = 22,
486 - .gpio_last = 23,
487 - }, {
488 - .name = "sdram",
489 - .mask = RT2880_GPIO_MODE_SDRAM,
490 - .gpio_first = 24,
491 - .gpio_last = 39,
492 - }, {
493 - .name = "pci",
494 - .mask = RT2880_GPIO_MODE_PCI,
495 - .gpio_first = 40,
496 - .gpio_last = 71,
497 - }, {0}
498 +static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) };
499 +static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
500 +static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 7, 8) };
501 +static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) };
502 +static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) };
503 +static struct rt2880_pmx_func sdram_func[] = { FUNC("sdram", 0, 24, 16) };
504 +static struct rt2880_pmx_func pci_func[] = { FUNC("pci", 0, 40, 32) };
505 +
506 +static struct rt2880_pmx_group rt2880_pinmux_data_act[] = {
507 + GRP("i2c", i2c_func, 1, RT2880_GPIO_MODE_I2C),
508 + GRP("spi", spi_func, 1, RT2880_GPIO_MODE_SPI),
509 + GRP("uartlite", uartlite_func, 1, RT2880_GPIO_MODE_UART0),
510 + GRP("jtag", jtag_func, 1, RT2880_GPIO_MODE_JTAG),
511 + GRP("mdio", mdio_func, 1, RT2880_GPIO_MODE_MDIO),
512 + GRP("sdram", sdram_func, 1, RT2880_GPIO_MODE_SDRAM),
513 + GRP("pci", pci_func, 1, RT2880_GPIO_MODE_PCI),
514 + { 0 }
515 };
516
517 static void rt288x_wdt_reset(void)
518 @@ -69,11 +50,6 @@ static void rt288x_wdt_reset(void)
519 rt_sysc_w32(t, SYSC_REG_CLKCFG);
520 }
521
522 -struct ralink_pinmux rt_gpio_pinmux = {
523 - .mode = mode_mux,
524 - .wdt_reset = rt288x_wdt_reset,
525 -};
526 -
527 void __init ralink_clk_init(void)
528 {
529 unsigned long cpu_rate, wmac_rate = 40000000;
530 @@ -141,4 +117,6 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
531 soc_info->mem_base = RT2880_SDRAM_BASE;
532 soc_info->mem_size_min = RT2880_MEM_SIZE_MIN;
533 soc_info->mem_size_max = RT2880_MEM_SIZE_MAX;
534 +
535 + rt2880_pinmux_data = rt2880_pinmux_data_act;
536 }
537 diff --git a/arch/mips/ralink/rt305x.c b/arch/mips/ralink/rt305x.c
538 index bb82a82..356d6a0 100644
539 --- a/arch/mips/ralink/rt305x.c
540 +++ b/arch/mips/ralink/rt305x.c
541 @@ -17,90 +17,76 @@
542 #include <asm/mipsregs.h>
543 #include <asm/mach-ralink/ralink_regs.h>
544 #include <asm/mach-ralink/rt305x.h>
545 +#include <asm/mach-ralink/pinmux.h>
546
547 #include "common.h"
548
549 enum rt305x_soc_type rt305x_soc;
550
551 -static struct ralink_pinmux_grp mode_mux[] = {
552 - {
553 - .name = "i2c",
554 - .mask = RT305X_GPIO_MODE_I2C,
555 - .gpio_first = RT305X_GPIO_I2C_SD,
556 - .gpio_last = RT305X_GPIO_I2C_SCLK,
557 - }, {
558 - .name = "spi",
559 - .mask = RT305X_GPIO_MODE_SPI,
560 - .gpio_first = RT305X_GPIO_SPI_EN,
561 - .gpio_last = RT305X_GPIO_SPI_CLK,
562 - }, {
563 - .name = "uartlite",
564 - .mask = RT305X_GPIO_MODE_UART1,
565 - .gpio_first = RT305X_GPIO_UART1_TXD,
566 - .gpio_last = RT305X_GPIO_UART1_RXD,
567 - }, {
568 - .name = "jtag",
569 - .mask = RT305X_GPIO_MODE_JTAG,
570 - .gpio_first = RT305X_GPIO_JTAG_TDO,
571 - .gpio_last = RT305X_GPIO_JTAG_TDI,
572 - }, {
573 - .name = "mdio",
574 - .mask = RT305X_GPIO_MODE_MDIO,
575 - .gpio_first = RT305X_GPIO_MDIO_MDC,
576 - .gpio_last = RT305X_GPIO_MDIO_MDIO,
577 - }, {
578 - .name = "sdram",
579 - .mask = RT305X_GPIO_MODE_SDRAM,
580 - .gpio_first = RT305X_GPIO_SDRAM_MD16,
581 - .gpio_last = RT305X_GPIO_SDRAM_MD31,
582 - }, {
583 - .name = "rgmii",
584 - .mask = RT305X_GPIO_MODE_RGMII,
585 - .gpio_first = RT305X_GPIO_GE0_TXD0,
586 - .gpio_last = RT305X_GPIO_GE0_RXCLK,
587 - }, {0}
588 +static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) };
589 +static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
590 +static struct rt2880_pmx_func uartf_func[] = {
591 + FUNC("uartf", RT305X_GPIO_MODE_UARTF, 7, 8),
592 + FUNC("pcm uartf", RT305X_GPIO_MODE_PCM_UARTF, 7, 8),
593 + FUNC("pcm i2s", RT305X_GPIO_MODE_PCM_I2S, 7, 8),
594 + FUNC("i2s uartf", RT305X_GPIO_MODE_I2S_UARTF, 7, 8),
595 + FUNC("pcm gpio", RT305X_GPIO_MODE_PCM_GPIO, 11, 4),
596 + FUNC("gpio uartf", RT305X_GPIO_MODE_GPIO_UARTF, 7, 4),
597 + FUNC("gpio i2s", RT305X_GPIO_MODE_GPIO_I2S, 7, 4),
598 +};
599 +static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 15, 2) };
600 +static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) };
601 +static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) };
602 +static struct rt2880_pmx_func rt5350_led_func[] = { FUNC("led", 0, 22, 5) };
603 +static struct rt2880_pmx_func rt5350_cs1_func[] = {
604 + FUNC("spi_cs1", 0, 27, 1),
605 + FUNC("wdg_cs1", 1, 27, 1),
606 +};
607 +static struct rt2880_pmx_func sdram_func[] = { FUNC("sdram", 0, 24, 16) };
608 +static struct rt2880_pmx_func rt3352_rgmii_func[] = { FUNC("rgmii", 0, 24, 12) };
609 +static struct rt2880_pmx_func rgmii_func[] = { FUNC("rgmii", 0, 40, 12) };
610 +static struct rt2880_pmx_func rt3352_lna_func[] = { FUNC("lna", 0, 36, 2) };
611 +static struct rt2880_pmx_func rt3352_pa_func[] = { FUNC("pa", 0, 38, 2) };
612 +static struct rt2880_pmx_func rt3352_led_func[] = { FUNC("led", 0, 40, 5) };
613 +
614 +static struct rt2880_pmx_group rt3050_pinmux_data[] = {
615 + GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
616 + GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI),
617 + GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK,
618 + RT305X_GPIO_MODE_UART0_SHIFT),
619 + GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1),
620 + GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG),
621 + GRP("mdio", mdio_func, 1, RT305X_GPIO_MODE_MDIO),
622 + GRP("rgmii", rgmii_func, 1, RT305X_GPIO_MODE_RGMII),
623 + GRP("sdram", sdram_func, 1, RT305X_GPIO_MODE_SDRAM),
624 + { 0 }
625 };
626
627 -static struct ralink_pinmux_grp uart_mux[] = {
628 - {
629 - .name = "uartf",
630 - .mask = RT305X_GPIO_MODE_UARTF,
631 - .gpio_first = RT305X_GPIO_7,
632 - .gpio_last = RT305X_GPIO_14,
633 - }, {
634 - .name = "pcm uartf",
635 - .mask = RT305X_GPIO_MODE_PCM_UARTF,
636 - .gpio_first = RT305X_GPIO_7,
637 - .gpio_last = RT305X_GPIO_14,
638 - }, {
639 - .name = "pcm i2s",
640 - .mask = RT305X_GPIO_MODE_PCM_I2S,
641 - .gpio_first = RT305X_GPIO_7,
642 - .gpio_last = RT305X_GPIO_14,
643 - }, {
644 - .name = "i2s uartf",
645 - .mask = RT305X_GPIO_MODE_I2S_UARTF,
646 - .gpio_first = RT305X_GPIO_7,
647 - .gpio_last = RT305X_GPIO_14,
648 - }, {
649 - .name = "pcm gpio",
650 - .mask = RT305X_GPIO_MODE_PCM_GPIO,
651 - .gpio_first = RT305X_GPIO_10,
652 - .gpio_last = RT305X_GPIO_14,
653 - }, {
654 - .name = "gpio uartf",
655 - .mask = RT305X_GPIO_MODE_GPIO_UARTF,
656 - .gpio_first = RT305X_GPIO_7,
657 - .gpio_last = RT305X_GPIO_10,
658 - }, {
659 - .name = "gpio i2s",
660 - .mask = RT305X_GPIO_MODE_GPIO_I2S,
661 - .gpio_first = RT305X_GPIO_7,
662 - .gpio_last = RT305X_GPIO_10,
663 - }, {
664 - .name = "gpio",
665 - .mask = RT305X_GPIO_MODE_GPIO,
666 - }, {0}
667 +static struct rt2880_pmx_group rt3352_pinmux_data[] = {
668 + GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
669 + GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI),
670 + GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK,
671 + RT305X_GPIO_MODE_UART0_SHIFT),
672 + GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1),
673 + GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG),
674 + GRP("mdio", mdio_func, 1, RT305X_GPIO_MODE_MDIO),
675 + GRP("rgmii", rt3352_rgmii_func, 1, RT305X_GPIO_MODE_RGMII),
676 + GRP("lna", rt3352_lna_func, 1, RT3352_GPIO_MODE_LNA),
677 + GRP("pa", rt3352_pa_func, 1, RT3352_GPIO_MODE_PA),
678 + GRP("led", rt3352_led_func, 1, RT5350_GPIO_MODE_PHY_LED),
679 + { 0 }
680 +};
681 +
682 +static struct rt2880_pmx_group rt5350_pinmux_data[] = {
683 + GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
684 + GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI),
685 + GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK,
686 + RT305X_GPIO_MODE_UART0_SHIFT),
687 + GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1),
688 + GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG),
689 + GRP("led", rt5350_led_func, 1, RT5350_GPIO_MODE_PHY_LED),
690 + GRP("spi_cs1", rt5350_cs1_func, 2, RT5350_GPIO_MODE_SPI_CS1),
691 + { 0 }
692 };
693
694 static void rt305x_wdt_reset(void)
695 @@ -114,14 +100,6 @@ static void rt305x_wdt_reset(void)
696 rt_sysc_w32(t, SYSC_REG_SYSTEM_CONFIG);
697 }
698
699 -struct ralink_pinmux rt_gpio_pinmux = {
700 - .mode = mode_mux,
701 - .uart = uart_mux,
702 - .uart_shift = RT305X_GPIO_MODE_UART0_SHIFT,
703 - .uart_mask = RT305X_GPIO_MODE_UART0_MASK,
704 - .wdt_reset = rt305x_wdt_reset,
705 -};
706 -
707 static unsigned long rt5350_get_mem_size(void)
708 {
709 void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE);
710 @@ -290,11 +268,14 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
711 soc_info->mem_base = RT305X_SDRAM_BASE;
712 if (soc_is_rt5350()) {
713 soc_info->mem_size = rt5350_get_mem_size();
714 + rt2880_pinmux_data = rt5350_pinmux_data;
715 } else if (soc_is_rt305x() || soc_is_rt3350()) {
716 soc_info->mem_size_min = RT305X_MEM_SIZE_MIN;
717 soc_info->mem_size_max = RT305X_MEM_SIZE_MAX;
718 + rt2880_pinmux_data = rt3050_pinmux_data;
719 } else if (soc_is_rt3352()) {
720 soc_info->mem_size_min = RT3352_MEM_SIZE_MIN;
721 soc_info->mem_size_max = RT3352_MEM_SIZE_MAX;
722 + rt2880_pinmux_data = rt3352_pinmux_data;
723 }
724 }
725 diff --git a/arch/mips/ralink/rt3883.c b/arch/mips/ralink/rt3883.c
726 index 58b5b9f..86a535c 100644
727 --- a/arch/mips/ralink/rt3883.c
728 +++ b/arch/mips/ralink/rt3883.c
729 @@ -17,132 +17,50 @@
730 #include <asm/mipsregs.h>
731 #include <asm/mach-ralink/ralink_regs.h>
732 #include <asm/mach-ralink/rt3883.h>
733 +#include <asm/mach-ralink/pinmux.h>
734
735 #include "common.h"
736
737 -static struct ralink_pinmux_grp mode_mux[] = {
738 - {
739 - .name = "i2c",
740 - .mask = RT3883_GPIO_MODE_I2C,
741 - .gpio_first = RT3883_GPIO_I2C_SD,
742 - .gpio_last = RT3883_GPIO_I2C_SCLK,
743 - }, {
744 - .name = "spi",
745 - .mask = RT3883_GPIO_MODE_SPI,
746 - .gpio_first = RT3883_GPIO_SPI_CS0,
747 - .gpio_last = RT3883_GPIO_SPI_MISO,
748 - }, {
749 - .name = "uartlite",
750 - .mask = RT3883_GPIO_MODE_UART1,
751 - .gpio_first = RT3883_GPIO_UART1_TXD,
752 - .gpio_last = RT3883_GPIO_UART1_RXD,
753 - }, {
754 - .name = "jtag",
755 - .mask = RT3883_GPIO_MODE_JTAG,
756 - .gpio_first = RT3883_GPIO_JTAG_TDO,
757 - .gpio_last = RT3883_GPIO_JTAG_TCLK,
758 - }, {
759 - .name = "mdio",
760 - .mask = RT3883_GPIO_MODE_MDIO,
761 - .gpio_first = RT3883_GPIO_MDIO_MDC,
762 - .gpio_last = RT3883_GPIO_MDIO_MDIO,
763 - }, {
764 - .name = "ge1",
765 - .mask = RT3883_GPIO_MODE_GE1,
766 - .gpio_first = RT3883_GPIO_GE1_TXD0,
767 - .gpio_last = RT3883_GPIO_GE1_RXCLK,
768 - }, {
769 - .name = "ge2",
770 - .mask = RT3883_GPIO_MODE_GE2,
771 - .gpio_first = RT3883_GPIO_GE2_TXD0,
772 - .gpio_last = RT3883_GPIO_GE2_RXCLK,
773 - }, {
774 - .name = "pci",
775 - .mask = RT3883_GPIO_MODE_PCI,
776 - .gpio_first = RT3883_GPIO_PCI_AD0,
777 - .gpio_last = RT3883_GPIO_PCI_AD31,
778 - }, {
779 - .name = "lna a",
780 - .mask = RT3883_GPIO_MODE_LNA_A,
781 - .gpio_first = RT3883_GPIO_LNA_PE_A0,
782 - .gpio_last = RT3883_GPIO_LNA_PE_A2,
783 - }, {
784 - .name = "lna g",
785 - .mask = RT3883_GPIO_MODE_LNA_G,
786 - .gpio_first = RT3883_GPIO_LNA_PE_G0,
787 - .gpio_last = RT3883_GPIO_LNA_PE_G2,
788 - }, {0}
789 +static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) };
790 +static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
791 +static struct rt2880_pmx_func uartf_func[] = {
792 + FUNC("uartf", RT3883_GPIO_MODE_UARTF, 7, 8),
793 + FUNC("pcm uartf", RT3883_GPIO_MODE_PCM_UARTF, 7, 8),
794 + FUNC("pcm i2s", RT3883_GPIO_MODE_PCM_I2S, 7, 8),
795 + FUNC("i2s uartf", RT3883_GPIO_MODE_I2S_UARTF, 7, 8),
796 + FUNC("pcm gpio", RT3883_GPIO_MODE_PCM_GPIO, 11, 4),
797 + FUNC("gpio uartf", RT3883_GPIO_MODE_GPIO_UARTF, 7, 4),
798 + FUNC("gpio i2s", RT3883_GPIO_MODE_GPIO_I2S, 7, 4),
799 };
800 -
801 -static struct ralink_pinmux_grp uart_mux[] = {
802 - {
803 - .name = "uartf",
804 - .mask = RT3883_GPIO_MODE_UARTF,
805 - .gpio_first = RT3883_GPIO_7,
806 - .gpio_last = RT3883_GPIO_14,
807 - }, {
808 - .name = "pcm uartf",
809 - .mask = RT3883_GPIO_MODE_PCM_UARTF,
810 - .gpio_first = RT3883_GPIO_7,
811 - .gpio_last = RT3883_GPIO_14,
812 - }, {
813 - .name = "pcm i2s",
814 - .mask = RT3883_GPIO_MODE_PCM_I2S,
815 - .gpio_first = RT3883_GPIO_7,
816 - .gpio_last = RT3883_GPIO_14,
817 - }, {
818 - .name = "i2s uartf",
819 - .mask = RT3883_GPIO_MODE_I2S_UARTF,
820 - .gpio_first = RT3883_GPIO_7,
821 - .gpio_last = RT3883_GPIO_14,
822 - }, {
823 - .name = "pcm gpio",
824 - .mask = RT3883_GPIO_MODE_PCM_GPIO,
825 - .gpio_first = RT3883_GPIO_11,
826 - .gpio_last = RT3883_GPIO_14,
827 - }, {
828 - .name = "gpio uartf",
829 - .mask = RT3883_GPIO_MODE_GPIO_UARTF,
830 - .gpio_first = RT3883_GPIO_7,
831 - .gpio_last = RT3883_GPIO_10,
832 - }, {
833 - .name = "gpio i2s",
834 - .mask = RT3883_GPIO_MODE_GPIO_I2S,
835 - .gpio_first = RT3883_GPIO_7,
836 - .gpio_last = RT3883_GPIO_10,
837 - }, {
838 - .name = "gpio",
839 - .mask = RT3883_GPIO_MODE_GPIO,
840 - }, {0}
841 +static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 15, 2) };
842 +static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) };
843 +static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) };
844 +static struct rt2880_pmx_func lna_a_func[] = { FUNC("lna a", 0, 32, 3) };
845 +static struct rt2880_pmx_func lna_g_func[] = { FUNC("lna a", 0, 35, 3) };
846 +static struct rt2880_pmx_func pci_func[] = {
847 + FUNC("pci-dev", 0, 40, 32),
848 + FUNC("pci-host2", 1, 40, 32),
849 + FUNC("pci-host1", 2, 40, 32),
850 + FUNC("pci-fnc", 3, 40, 32)
851 };
852 -
853 -static struct ralink_pinmux_grp pci_mux[] = {
854 - {
855 - .name = "pci-dev",
856 - .mask = 0,
857 - .gpio_first = RT3883_GPIO_PCI_AD0,
858 - .gpio_last = RT3883_GPIO_PCI_AD31,
859 - }, {
860 - .name = "pci-host2",
861 - .mask = 1,
862 - .gpio_first = RT3883_GPIO_PCI_AD0,
863 - .gpio_last = RT3883_GPIO_PCI_AD31,
864 - }, {
865 - .name = "pci-host1",
866 - .mask = 2,
867 - .gpio_first = RT3883_GPIO_PCI_AD0,
868 - .gpio_last = RT3883_GPIO_PCI_AD31,
869 - }, {
870 - .name = "pci-fnc",
871 - .mask = 3,
872 - .gpio_first = RT3883_GPIO_PCI_AD0,
873 - .gpio_last = RT3883_GPIO_PCI_AD31,
874 - }, {
875 - .name = "pci-gpio",
876 - .mask = 7,
877 - .gpio_first = RT3883_GPIO_PCI_AD0,
878 - .gpio_last = RT3883_GPIO_PCI_AD31,
879 - }, {0}
880 +static struct rt2880_pmx_func ge1_func[] = { FUNC("ge1", 0, 72, 12) };
881 +static struct rt2880_pmx_func ge2_func[] = { FUNC("ge1", 0, 84, 12) };
882 +
883 +static struct rt2880_pmx_group rt3883_pinmux_data[] = {
884 + GRP("i2c", i2c_func, 1, RT3883_GPIO_MODE_I2C),
885 + GRP("spi", spi_func, 1, RT3883_GPIO_MODE_SPI),
886 + GRP("uartf", uartf_func, RT3883_GPIO_MODE_UART0_MASK,
887 + RT3883_GPIO_MODE_UART0_SHIFT),
888 + GRP("uartlite", uartlite_func, 1, RT3883_GPIO_MODE_UART1),
889 + GRP("jtag", jtag_func, 1, RT3883_GPIO_MODE_JTAG),
890 + GRP("mdio", mdio_func, 1, RT3883_GPIO_MODE_MDIO),
891 + GRP("lna a", lna_a_func, 1, RT3883_GPIO_MODE_LNA_A),
892 + GRP("lna g", lna_g_func, 1, RT3883_GPIO_MODE_LNA_G),
893 + GRP("pci", pci_func, RT3883_GPIO_MODE_PCI_MASK,
894 + RT3883_GPIO_MODE_PCI_SHIFT),
895 + GRP("ge1", ge1_func, 1, RT3883_GPIO_MODE_GE1),
896 + GRP("ge2", ge2_func, 1, RT3883_GPIO_MODE_GE2),
897 + { 0 }
898 };
899
900 static void rt3883_wdt_reset(void)
901 @@ -155,17 +73,6 @@ static void rt3883_wdt_reset(void)
902 rt_sysc_w32(t, RT3883_SYSC_REG_SYSCFG1);
903 }
904
905 -struct ralink_pinmux rt_gpio_pinmux = {
906 - .mode = mode_mux,
907 - .uart = uart_mux,
908 - .uart_shift = RT3883_GPIO_MODE_UART0_SHIFT,
909 - .uart_mask = RT3883_GPIO_MODE_UART0_MASK,
910 - .wdt_reset = rt3883_wdt_reset,
911 - .pci = pci_mux,
912 - .pci_shift = RT3883_GPIO_MODE_PCI_SHIFT,
913 - .pci_mask = RT3883_GPIO_MODE_PCI_MASK,
914 -};
915 -
916 void __init ralink_clk_init(void)
917 {
918 unsigned long cpu_rate, sys_rate;
919 @@ -244,4 +151,6 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
920 soc_info->mem_base = RT3883_SDRAM_BASE;
921 soc_info->mem_size_min = RT3883_MEM_SIZE_MIN;
922 soc_info->mem_size_max = RT3883_MEM_SIZE_MAX;
923 +
924 + rt2880_pinmux_data = rt3883_pinmux_data;
925 }
926 diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
927 index 1e4e693..1ff1491 100644
928 --- a/drivers/pinctrl/Kconfig
929 +++ b/drivers/pinctrl/Kconfig
930 @@ -198,6 +198,11 @@ config PINCTRL_LANTIQ
931 select PINMUX
932 select PINCONF
933
934 +config PINCTRL_RT2880
935 + bool
936 + depends on RALINK
937 + select PINMUX
938 +
939 config PINCTRL_FALCON
940 bool
941 depends on SOC_FALCON
942 diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
943 index 4b83588..3160836 100644
944 --- a/drivers/pinctrl/Makefile
945 +++ b/drivers/pinctrl/Makefile
946 @@ -45,6 +45,7 @@ obj-$(CONFIG_PINCTRL_DB8500) += pinctrl-nomadik-db8500.o
947 obj-$(CONFIG_PINCTRL_DB8540) += pinctrl-nomadik-db8540.o
948 obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o
949 obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o
950 +obj-$(CONFIG_PINCTRL_RT2880) += pinctrl-rt2880.o
951 obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
952 obj-$(CONFIG_PINCTRL_SIRF) += sirf/
953 obj-$(CONFIG_PINCTRL_SUNXI) += pinctrl-sunxi.o
954 diff --git a/drivers/pinctrl/pinctrl-rt2880.c b/drivers/pinctrl/pinctrl-rt2880.c
955 new file mode 100644
956 index 0000000..378ed52
957 --- /dev/null
958 +++ b/drivers/pinctrl/pinctrl-rt2880.c
959 @@ -0,0 +1,467 @@
960 +/*
961 + * linux/drivers/pinctrl/pinctrl-rt2880.c
962 + *
963 + * This program is free software; you can redistribute it and/or modify
964 + * it under the terms of the GNU General Public License version 2 as
965 + * publishhed by the Free Software Foundation.
966 + *
967 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
968 + */
969 +
970 +#include <linux/module.h>
971 +#include <linux/device.h>
972 +#include <linux/io.h>
973 +#include <linux/platform_device.h>
974 +#include <linux/slab.h>
975 +#include <linux/of.h>
976 +#include <linux/pinctrl/pinctrl.h>
977 +#include <linux/pinctrl/pinconf.h>
978 +#include <linux/pinctrl/pinmux.h>
979 +#include <linux/pinctrl/consumer.h>
980 +#include <linux/pinctrl/machine.h>
981 +
982 +#include <asm/mach-ralink/ralink_regs.h>
983 +#include <asm/mach-ralink/pinmux.h>
984 +#include <asm/mach-ralink/mt7620.h>
985 +
986 +#include "core.h"
987 +
988 +#define SYSC_REG_GPIO_MODE 0x60
989 +
990 +struct rt2880_priv {
991 + struct device *dev;
992 +
993 + struct pinctrl_pin_desc *pads;
994 + struct pinctrl_desc *desc;
995 +
996 + struct rt2880_pmx_func **func;
997 + int func_count;
998 +
999 + struct rt2880_pmx_group *groups;
1000 + const char **group_names;
1001 + int group_count;
1002 +
1003 + uint8_t *gpio;
1004 + int max_pins;
1005 +};
1006 +
1007 +struct rt2880_pmx_group *rt2880_pinmux_data = NULL;
1008 +
1009 +static int rt2880_get_group_count(struct pinctrl_dev *pctrldev)
1010 +{
1011 + struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
1012 +
1013 + return p->group_count;
1014 +}
1015 +
1016 +static const char *rt2880_get_group_name(struct pinctrl_dev *pctrldev,
1017 + unsigned group)
1018 +{
1019 + struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
1020 +
1021 + if (group >= p->group_count)
1022 + return NULL;
1023 +
1024 + return p->group_names[group];
1025 +}
1026 +
1027 +static int rt2880_get_group_pins(struct pinctrl_dev *pctrldev,
1028 + unsigned group,
1029 + const unsigned **pins,
1030 + unsigned *num_pins)
1031 +{
1032 + struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
1033 +
1034 + if (group >= p->group_count)
1035 + return -EINVAL;
1036 +
1037 + *pins = p->groups[group].func[0].pins;
1038 + *num_pins = p->groups[group].func[0].pin_count;
1039 +
1040 + return 0;
1041 +}
1042 +
1043 +static void rt2880_pinctrl_dt_free_map(struct pinctrl_dev *pctrldev,
1044 + struct pinctrl_map *map, unsigned num_maps)
1045 +{
1046 + int i;
1047 +
1048 + for (i = 0; i < num_maps; i++)
1049 + if (map[i].type == PIN_MAP_TYPE_CONFIGS_PIN ||
1050 + map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
1051 + kfree(map[i].data.configs.configs);
1052 + kfree(map);
1053 +}
1054 +
1055 +static void rt2880_pinctrl_pin_dbg_show(struct pinctrl_dev *pctrldev,
1056 + struct seq_file *s,
1057 + unsigned offset)
1058 +{
1059 + seq_printf(s, "ralink pio");
1060 +}
1061 +
1062 +static void rt2880_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctrldev,
1063 + struct device_node *np,
1064 + struct pinctrl_map **map)
1065 +{
1066 + const char *function;
1067 + int func = of_property_read_string(np, "ralink,function", &function);
1068 + int grps = of_property_count_strings(np, "ralink,group");
1069 + int i;
1070 +
1071 + if (func || !grps)
1072 + return;
1073 +
1074 + for (i = 0; i < grps; i++) {
1075 + const char *group;
1076 +
1077 + of_property_read_string_index(np, "ralink,group", i, &group);
1078 +
1079 + (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
1080 + (*map)->name = function;
1081 + (*map)->data.mux.group = group;
1082 + (*map)->data.mux.function = function;
1083 + (*map)++;
1084 + }
1085 +}
1086 +
1087 +static int rt2880_pinctrl_dt_node_to_map(struct pinctrl_dev *pctrldev,
1088 + struct device_node *np_config,
1089 + struct pinctrl_map **map,
1090 + unsigned *num_maps)
1091 +{
1092 + int max_maps = 0;
1093 + struct pinctrl_map *tmp;
1094 + struct device_node *np;
1095 +
1096 + for_each_child_of_node(np_config, np) {
1097 + int ret = of_property_count_strings(np, "ralink,group");
1098 +
1099 + if (ret >= 0)
1100 + max_maps += ret;
1101 + }
1102 +
1103 + if (!max_maps)
1104 + return max_maps;
1105 +
1106 + *map = kzalloc(max_maps * sizeof(struct pinctrl_map), GFP_KERNEL);
1107 + if (!*map)
1108 + return -ENOMEM;
1109 +
1110 + tmp = *map;
1111 +
1112 + for_each_child_of_node(np_config, np)
1113 + rt2880_pinctrl_dt_subnode_to_map(pctrldev, np, &tmp);
1114 + *num_maps = max_maps;
1115 +
1116 + return 0;
1117 +}
1118 +
1119 +static const struct pinctrl_ops rt2880_pctrl_ops = {
1120 + .get_groups_count = rt2880_get_group_count,
1121 + .get_group_name = rt2880_get_group_name,
1122 + .get_group_pins = rt2880_get_group_pins,
1123 + .pin_dbg_show = rt2880_pinctrl_pin_dbg_show,
1124 + .dt_node_to_map = rt2880_pinctrl_dt_node_to_map,
1125 + .dt_free_map = rt2880_pinctrl_dt_free_map,
1126 +};
1127 +
1128 +static int rt2880_pmx_func_count(struct pinctrl_dev *pctrldev)
1129 +{
1130 + struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
1131 +
1132 + return p->func_count;
1133 +}
1134 +
1135 +static const char *rt2880_pmx_func_name(struct pinctrl_dev *pctrldev,
1136 + unsigned func)
1137 +{
1138 + struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
1139 +
1140 + return p->func[func]->name;
1141 +}
1142 +
1143 +static int rt2880_pmx_group_get_groups(struct pinctrl_dev *pctrldev,
1144 + unsigned func,
1145 + const char * const **groups,
1146 + unsigned * const num_groups)
1147 +{
1148 + struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
1149 +
1150 + if (p->func[func]->group_count == 1)
1151 + *groups = &p->group_names[p->func[func]->groups[0]];
1152 + else
1153 + *groups = p->group_names;
1154 +
1155 + *num_groups = p->func[func]->group_count;
1156 +
1157 + return 0;
1158 +}
1159 +
1160 +static int rt2880_pmx_group_enable(struct pinctrl_dev *pctrldev,
1161 + unsigned func,
1162 + unsigned group)
1163 +{
1164 + struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
1165 + u32 mode = 0;
1166 + int i;
1167 +
1168 + /* dont allow double use */
1169 + if (p->groups[group].enabled) {
1170 + dev_err(p->dev, "%s is already enabled\n", p->groups[group].name);
1171 + return -EBUSY;
1172 + }
1173 +
1174 + p->groups[group].enabled = 1;
1175 + p->func[func]->enabled = 1;
1176 +
1177 + mode = rt_sysc_r32(SYSC_REG_GPIO_MODE);
1178 + mode &= ~(p->groups[group].mask << p->groups[group].shift);
1179 +
1180 + /* mark the pins as gpio */
1181 + for (i = 0; i < p->groups[group].func[0].pin_count; i++)
1182 + p->gpio[p->groups[group].func[0].pins[i]] = 1;
1183 +
1184 + /* function 0 is gpio and needs special handling */
1185 + if (func == 0) {
1186 + mode |= p->groups[group].gpio << p->groups[group].shift;
1187 + } else {
1188 + for (i = 0; i < p->func[func]->pin_count; i++)
1189 + p->gpio[p->func[func]->pins[i]] = 0;
1190 + mode |= p->func[func]->value << p->groups[group].shift;
1191 + }
1192 + rt_sysc_w32(mode, SYSC_REG_GPIO_MODE);
1193 +
1194 +
1195 + return 0;
1196 +}
1197 +
1198 +static int rt2880_pmx_group_gpio_request_enable(struct pinctrl_dev *pctrldev,
1199 + struct pinctrl_gpio_range *range,
1200 + unsigned pin)
1201 +{
1202 + struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
1203 +
1204 + if (!p->gpio[pin]) {
1205 + dev_err(p->dev, "pin %d is not set to gpio mux\n", pin);
1206 + return -EINVAL;
1207 + }
1208 +
1209 + return 0;
1210 +}
1211 +
1212 +static const struct pinmux_ops rt2880_pmx_group_ops = {
1213 + .get_functions_count = rt2880_pmx_func_count,
1214 + .get_function_name = rt2880_pmx_func_name,
1215 + .get_function_groups = rt2880_pmx_group_get_groups,
1216 + .enable = rt2880_pmx_group_enable,
1217 + .gpio_request_enable = rt2880_pmx_group_gpio_request_enable,
1218 +};
1219 +
1220 +static struct pinctrl_desc rt2880_pctrl_desc = {
1221 + .owner = THIS_MODULE,
1222 + .name = "rt2880-pinmux",
1223 + .pctlops = &rt2880_pctrl_ops,
1224 + .pmxops = &rt2880_pmx_group_ops,
1225 +};
1226 +
1227 +static struct rt2880_pmx_func gpio_func = {
1228 + .name = "gpio",
1229 +};
1230 +
1231 +static int rt2880_pinmux_index(struct rt2880_priv *p)
1232 +{
1233 + struct rt2880_pmx_func **f;
1234 + struct rt2880_pmx_group *mux = p->groups;
1235 + int i, j, c = 0;
1236 +
1237 + /* count the mux functions */
1238 + while (mux->name) {
1239 + p->group_count++;
1240 + mux++;
1241 + }
1242 +
1243 + /* allocate the group names array needed by the gpio function */
1244 + p->group_names = devm_kzalloc(p->dev, sizeof(char *) * p->group_count, GFP_KERNEL);
1245 + if (!p->group_names)
1246 + return -1;
1247 +
1248 + for (i = 0; i < p->group_count; i++) {
1249 + p->group_names[i] = p->groups[i].name;
1250 + p->func_count += p->groups[i].func_count;
1251 + }
1252 +
1253 + /* we have a dummy function[0] for gpio */
1254 + p->func_count++;
1255 +
1256 + /* allocate our function and group mapping index buffers */
1257 + f = p->func = devm_kzalloc(p->dev, sizeof(struct rt2880_pmx_func) * p->func_count, GFP_KERNEL);
1258 + gpio_func.groups = devm_kzalloc(p->dev, sizeof(int) * p->group_count, GFP_KERNEL);
1259 + if (!f || !gpio_func.groups)
1260 + return -1;
1261 +
1262 + /* add a backpointer to the function so it knows its group */
1263 + gpio_func.group_count = p->group_count;
1264 + for (i = 0; i < gpio_func.group_count; i++)
1265 + gpio_func.groups[i] = i;
1266 +
1267 + f[c] = &gpio_func;
1268 + c++;
1269 +
1270 + /* add remaining functions */
1271 + for (i = 0; i < p->group_count; i++) {
1272 + for (j = 0; j < p->groups[i].func_count; j++) {
1273 + f[c] = &p->groups[i].func[j];
1274 + f[c]->groups = devm_kzalloc(p->dev, sizeof(int), GFP_KERNEL);
1275 + f[c]->groups[0] = i;
1276 + f[c]->group_count = 1;
1277 + c++;
1278 + }
1279 + }
1280 + return 0;
1281 +}
1282 +
1283 +static int rt2880_pinmux_pins(struct rt2880_priv *p)
1284 +{
1285 + int i, j;
1286 +
1287 + /* loop over the functions and initialize the pins array. also work out the highest pin used */
1288 + for (i = 0; i < p->func_count; i++) {
1289 + int pin;
1290 +
1291 + if (!p->func[i]->pin_count)
1292 + continue;
1293 +
1294 + p->func[i]->pins = devm_kzalloc(p->dev, sizeof(int) * p->func[i]->pin_count, GFP_KERNEL);
1295 + for (j = 0; j < p->func[i]->pin_count; j++)
1296 + p->func[i]->pins[j] = p->func[i]->pin_first + j;
1297 +
1298 + pin = p->func[i]->pin_first + p->func[i]->pin_count;
1299 + if (pin > p->max_pins)
1300 + p->max_pins = pin;
1301 + }
1302 +
1303 + /* the buffer that tells us which pins are gpio */
1304 + p->gpio = devm_kzalloc(p->dev,sizeof(uint8_t) * p->max_pins,
1305 + GFP_KERNEL);
1306 + /* the pads needed to tell pinctrl about our pins */
1307 + p->pads = devm_kzalloc(p->dev,
1308 + sizeof(struct pinctrl_pin_desc) * p->max_pins,
1309 + GFP_KERNEL);
1310 + if (!p->pads || !p->gpio ) {
1311 + dev_err(p->dev, "Failed to allocate gpio data\n");
1312 + return -ENOMEM;
1313 + }
1314 +
1315 + memset(p->gpio, 1, sizeof(uint8_t) * p->max_pins);
1316 + for (i = 0; i < p->func_count; i++) {
1317 + if (!p->func[i]->pin_count)
1318 + continue;
1319 +
1320 + for (j = 0; j < p->func[i]->pin_count; j++)
1321 + p->gpio[p->func[i]->pins[j]] = 0;
1322 + }
1323 +
1324 + /* pin 0 is always a gpio */
1325 + p->gpio[0] = 1;
1326 +
1327 + /* set the pads */
1328 + for (i = 0; i < p->max_pins; i++) {
1329 + /* strlen("ioXY") + 1 = 5 */
1330 + char *name = devm_kzalloc(p->dev, 5, GFP_KERNEL);
1331 +
1332 + if (!name) {
1333 + dev_err(p->dev, "Failed to allocate pad name\n");
1334 + return -ENOMEM;
1335 + }
1336 + snprintf(name, 5, "io%d", i);
1337 + p->pads[i].number = i;
1338 + p->pads[i].name = name;
1339 + }
1340 + p->desc->pins = p->pads;
1341 + p->desc->npins = p->max_pins;
1342 +
1343 + return 0;
1344 +}
1345 +
1346 +static int rt2880_pinmux_probe(struct platform_device *pdev)
1347 +{
1348 + struct rt2880_priv *p;
1349 + struct pinctrl_dev *dev;
1350 + struct device_node *np;
1351 +
1352 + if (!rt2880_pinmux_data)
1353 + return -ENOSYS;
1354 +
1355 + /* setup the private data */
1356 + p = devm_kzalloc(&pdev->dev, sizeof(struct rt2880_priv), GFP_KERNEL);
1357 + if (!p)
1358 + return -ENOMEM;
1359 +
1360 + p->dev = &pdev->dev;
1361 + p->desc = &rt2880_pctrl_desc;
1362 + p->groups = rt2880_pinmux_data;
1363 + platform_set_drvdata(pdev, p);
1364 +
1365 + /* init the device */
1366 + if (rt2880_pinmux_index(p)) {
1367 + dev_err(&pdev->dev, "failed to load index\n");
1368 + return -EINVAL;
1369 + }
1370 + if (rt2880_pinmux_pins(p)) {
1371 + dev_err(&pdev->dev, "failed to load pins\n");
1372 + return -EINVAL;
1373 + }
1374 + dev = pinctrl_register(p->desc, &pdev->dev, p);
1375 + if (IS_ERR(dev))
1376 + return PTR_ERR(dev);
1377 +
1378 + /* finalize by adding gpio ranges for enables gpio controllers */
1379 + for_each_compatible_node(np, NULL, "ralink,rt2880-gpio") {
1380 + const __be32 *ngpio, *gpiobase;
1381 + struct pinctrl_gpio_range *range;
1382 + char *name;
1383 +
1384 + if (!of_device_is_available(np))
1385 + continue;
1386 +
1387 + ngpio = of_get_property(np, "ralink,num-gpios", NULL);
1388 + gpiobase = of_get_property(np, "ralink,gpio-base", NULL);
1389 + if (!ngpio || !gpiobase) {
1390 + dev_err(&pdev->dev, "failed to load chip info\n");
1391 + return -EINVAL;
1392 + }
1393 +
1394 + range = devm_kzalloc(p->dev, sizeof(struct pinctrl_gpio_range) + 4, GFP_KERNEL);
1395 + range->name = name = (char *) &range[1];
1396 + sprintf(name, "pio");
1397 + range->npins = __be32_to_cpu(*ngpio);
1398 + range->base = __be32_to_cpu(*gpiobase);
1399 + range->pin_base = range->base;
1400 + pinctrl_add_gpio_range(dev, range);
1401 + }
1402 +
1403 + return 0;
1404 +}
1405 +
1406 +static const struct of_device_id rt2880_pinmux_match[] = {
1407 + { .compatible = "ralink,rt2880-pinmux" },
1408 + {},
1409 +};
1410 +MODULE_DEVICE_TABLE(of, rt2880_pinmux_match);
1411 +
1412 +static struct platform_driver rt2880_pinmux_driver = {
1413 + .probe = rt2880_pinmux_probe,
1414 + .driver = {
1415 + .name = "rt2880-pinmux",
1416 + .owner = THIS_MODULE,
1417 + .of_match_table = rt2880_pinmux_match,
1418 + },
1419 +};
1420 +
1421 +int __init rt2880_pinmux_init(void)
1422 +{
1423 + return platform_driver_register(&rt2880_pinmux_driver);
1424 +}
1425 +
1426 +core_initcall_sync(rt2880_pinmux_init);
1427 --
1428 1.7.10.4
1429
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