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add patches for v3.8
[openwrt/staging/wigyori.git] / target / linux / ramips / patches-3.8 / 0109-MIPS-ralink-adds-support-for-RT3883-SoC-family.patch
1 From 45a8644332a85e8b099df9d467a719ded741e749 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sun, 27 Jan 2013 09:39:02 +0100
4 Subject: [PATCH 109/121] MIPS: ralink: adds support for RT3883 SoC family
5
6 Add support code for rt3883 SOC.
7
8 The code detects the SoC and registers the clk / pinmux settings.
9
10 Signed-off-by: John Crispin <blogic@openwrt.org>
11 ---
12 arch/mips/include/asm/mach-ralink/rt3883.h | 247 ++++++++++++++++++++++++++++
13 arch/mips/ralink/Kconfig | 5 +
14 arch/mips/ralink/Makefile | 1 +
15 arch/mips/ralink/Platform | 5 +
16 arch/mips/ralink/rt3883.c | 207 +++++++++++++++++++++++
17 5 files changed, 465 insertions(+)
18 create mode 100644 arch/mips/include/asm/mach-ralink/rt3883.h
19 create mode 100644 arch/mips/ralink/rt3883.c
20
21 diff --git a/arch/mips/include/asm/mach-ralink/rt3883.h b/arch/mips/include/asm/mach-ralink/rt3883.h
22 new file mode 100644
23 index 0000000..b91c6c1
24 --- /dev/null
25 +++ b/arch/mips/include/asm/mach-ralink/rt3883.h
26 @@ -0,0 +1,247 @@
27 +/*
28 + * Ralink RT3662/RT3883 SoC register definitions
29 + *
30 + * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
31 + *
32 + * This program is free software; you can redistribute it and/or modify it
33 + * under the terms of the GNU General Public License version 2 as published
34 + * by the Free Software Foundation.
35 + */
36 +
37 +#ifndef _RT3883_REGS_H_
38 +#define _RT3883_REGS_H_
39 +
40 +#include <linux/bitops.h>
41 +
42 +#define RT3883_SDRAM_BASE 0x00000000
43 +#define RT3883_SYSC_BASE 0x10000000
44 +#define RT3883_TIMER_BASE 0x10000100
45 +#define RT3883_INTC_BASE 0x10000200
46 +#define RT3883_MEMC_BASE 0x10000300
47 +#define RT3883_UART0_BASE 0x10000500
48 +#define RT3883_PIO_BASE 0x10000600
49 +#define RT3883_FSCC_BASE 0x10000700
50 +#define RT3883_NANDC_BASE 0x10000810
51 +#define RT3883_I2C_BASE 0x10000900
52 +#define RT3883_I2S_BASE 0x10000a00
53 +#define RT3883_SPI_BASE 0x10000b00
54 +#define RT3883_UART1_BASE 0x10000c00
55 +#define RT3883_PCM_BASE 0x10002000
56 +#define RT3883_GDMA_BASE 0x10002800
57 +#define RT3883_CODEC1_BASE 0x10003000
58 +#define RT3883_CODEC2_BASE 0x10003800
59 +#define RT3883_FE_BASE 0x10100000
60 +#define RT3883_ROM_BASE 0x10118000
61 +#define RT3883_USBDEV_BASE 0x10112000
62 +#define RT3883_PCI_BASE 0x10140000
63 +#define RT3883_WLAN_BASE 0x10180000
64 +#define RT3883_USBHOST_BASE 0x101c0000
65 +#define RT3883_BOOT_BASE 0x1c000000
66 +#define RT3883_SRAM_BASE 0x1e000000
67 +#define RT3883_PCIMEM_BASE 0x20000000
68 +
69 +#define RT3883_EHCI_BASE (RT3883_USBHOST_BASE)
70 +#define RT3883_OHCI_BASE (RT3883_USBHOST_BASE + 0x1000)
71 +
72 +#define RT3883_SYSC_SIZE 0x100
73 +#define RT3883_TIMER_SIZE 0x100
74 +#define RT3883_INTC_SIZE 0x100
75 +#define RT3883_MEMC_SIZE 0x100
76 +#define RT3883_UART0_SIZE 0x100
77 +#define RT3883_UART1_SIZE 0x100
78 +#define RT3883_PIO_SIZE 0x100
79 +#define RT3883_FSCC_SIZE 0x100
80 +#define RT3883_NANDC_SIZE 0x0f0
81 +#define RT3883_I2C_SIZE 0x100
82 +#define RT3883_I2S_SIZE 0x100
83 +#define RT3883_SPI_SIZE 0x100
84 +#define RT3883_PCM_SIZE 0x800
85 +#define RT3883_GDMA_SIZE 0x800
86 +#define RT3883_CODEC1_SIZE 0x800
87 +#define RT3883_CODEC2_SIZE 0x800
88 +#define RT3883_FE_SIZE 0x10000
89 +#define RT3883_ROM_SIZE 0x4000
90 +#define RT3883_USBDEV_SIZE 0x4000
91 +#define RT3883_PCI_SIZE 0x40000
92 +#define RT3883_WLAN_SIZE 0x40000
93 +#define RT3883_USBHOST_SIZE 0x40000
94 +#define RT3883_BOOT_SIZE (32 * 1024 * 1024)
95 +#define RT3883_SRAM_SIZE (32 * 1024 * 1024)
96 +
97 +/* SYSC registers */
98 +#define RT3883_SYSC_REG_CHIPID0_3 0x00 /* Chip ID 0 */
99 +#define RT3883_SYSC_REG_CHIPID4_7 0x04 /* Chip ID 1 */
100 +#define RT3883_SYSC_REG_REVID 0x0c /* Chip Revision Identification */
101 +#define RT3883_SYSC_REG_SYSCFG0 0x10 /* System Configuration 0 */
102 +#define RT3883_SYSC_REG_SYSCFG1 0x14 /* System Configuration 1 */
103 +#define RT3883_SYSC_REG_CLKCFG0 0x2c /* Clock Configuration 0 */
104 +#define RT3883_SYSC_REG_CLKCFG1 0x30 /* Clock Configuration 1 */
105 +#define RT3883_SYSC_REG_RSTCTRL 0x34 /* Reset Control*/
106 +#define RT3883_SYSC_REG_RSTSTAT 0x38 /* Reset Status*/
107 +#define RT3883_SYSC_REG_USB_PS 0x5c /* USB Power saving control */
108 +#define RT3883_SYSC_REG_GPIO_MODE 0x60 /* GPIO Purpose Select */
109 +#define RT3883_SYSC_REG_PCIE_CLK_GEN0 0x7c
110 +#define RT3883_SYSC_REG_PCIE_CLK_GEN1 0x80
111 +#define RT3883_SYSC_REG_PCIE_CLK_GEN2 0x84
112 +#define RT3883_SYSC_REG_PMU 0x88
113 +#define RT3883_SYSC_REG_PMU1 0x8c
114 +
115 +#define RT3883_CHIP_NAME0 0x38335452
116 +#define RT3883_CHIP_NAME1 0x20203338
117 +
118 +#define RT3883_REVID_VER_ID_MASK 0x0f
119 +#define RT3883_REVID_VER_ID_SHIFT 8
120 +#define RT3883_REVID_ECO_ID_MASK 0x0f
121 +
122 +#define RT3883_SYSCFG0_DRAM_TYPE_DDR2 BIT(17)
123 +#define RT3883_SYSCFG0_CPUCLK_SHIFT 8
124 +#define RT3883_SYSCFG0_CPUCLK_MASK 0x3
125 +#define RT3883_SYSCFG0_CPUCLK_250 0x0
126 +#define RT3883_SYSCFG0_CPUCLK_384 0x1
127 +#define RT3883_SYSCFG0_CPUCLK_480 0x2
128 +#define RT3883_SYSCFG0_CPUCLK_500 0x3
129 +
130 +#define RT3883_SYSCFG1_USB0_HOST_MODE BIT(10)
131 +#define RT3883_SYSCFG1_PCIE_RC_MODE BIT(8)
132 +#define RT3883_SYSCFG1_PCI_HOST_MODE BIT(7)
133 +#define RT3883_SYSCFG1_PCI_66M_MODE BIT(6)
134 +#define RT3883_SYSCFG1_GPIO2_AS_WDT_OUT BIT(2)
135 +
136 +#define RT3883_CLKCFG1_PCIE_CLK_EN BIT(21)
137 +#define RT3883_CLKCFG1_UPHY1_CLK_EN BIT(20)
138 +#define RT3883_CLKCFG1_PCI_CLK_EN BIT(19)
139 +#define RT3883_CLKCFG1_UPHY0_CLK_EN BIT(18)
140 +
141 +#define RT3883_GPIO_MODE_I2C BIT(0)
142 +#define RT3883_GPIO_MODE_SPI BIT(1)
143 +#define RT3883_GPIO_MODE_UART0_SHIFT 2
144 +#define RT3883_GPIO_MODE_UART0_MASK 0x7
145 +#define RT3883_GPIO_MODE_UART0(x) ((x) << RT3883_GPIO_MODE_UART0_SHIFT)
146 +#define RT3883_GPIO_MODE_UARTF 0x0
147 +#define RT3883_GPIO_MODE_PCM_UARTF 0x1
148 +#define RT3883_GPIO_MODE_PCM_I2S 0x2
149 +#define RT3883_GPIO_MODE_I2S_UARTF 0x3
150 +#define RT3883_GPIO_MODE_PCM_GPIO 0x4
151 +#define RT3883_GPIO_MODE_GPIO_UARTF 0x5
152 +#define RT3883_GPIO_MODE_GPIO_I2S 0x6
153 +#define RT3883_GPIO_MODE_GPIO 0x7
154 +#define RT3883_GPIO_MODE_UART1 BIT(5)
155 +#define RT3883_GPIO_MODE_JTAG BIT(6)
156 +#define RT3883_GPIO_MODE_MDIO BIT(7)
157 +#define RT3883_GPIO_MODE_GE1 BIT(9)
158 +#define RT3883_GPIO_MODE_GE2 BIT(10)
159 +#define RT3883_GPIO_MODE_PCI_SHIFT 11
160 +#define RT3883_GPIO_MODE_PCI_MASK 0x7
161 +#define RT3883_GPIO_MODE_PCI (RT3883_GPIO_MODE_PCI_MASK << RT3883_GPIO_MODE_PCI_SHIFT)
162 +#define RT3883_GPIO_MODE_LNA_A_SHIFT 16
163 +#define RT3883_GPIO_MODE_LNA_A_MASK 0x3
164 +#define _RT3883_GPIO_MODE_LNA_A(_x) ((_x) << RT3883_GPIO_MODE_LNA_A_SHIFT)
165 +#define RT3883_GPIO_MODE_LNA_A_GPIO 0x3
166 +#define RT3883_GPIO_MODE_LNA_A _RT3883_GPIO_MODE_LNA_A(RT3883_GPIO_MODE_LNA_A_MASK)
167 +#define RT3883_GPIO_MODE_LNA_G_SHIFT 18
168 +#define RT3883_GPIO_MODE_LNA_G_MASK 0x3
169 +#define _RT3883_GPIO_MODE_LNA_G(_x) ((_x) << RT3883_GPIO_MODE_LNA_G_SHIFT)
170 +#define RT3883_GPIO_MODE_LNA_G_GPIO 0x3
171 +#define RT3883_GPIO_MODE_LNA_G _RT3883_GPIO_MODE_LNA_G(RT3883_GPIO_MODE_LNA_G_MASK)
172 +
173 +#define RT3883_GPIO_I2C_SD 1
174 +#define RT3883_GPIO_I2C_SCLK 2
175 +#define RT3883_GPIO_SPI_CS0 3
176 +#define RT3883_GPIO_SPI_CLK 4
177 +#define RT3883_GPIO_SPI_MOSI 5
178 +#define RT3883_GPIO_SPI_MISO 6
179 +#define RT3883_GPIO_7 7
180 +#define RT3883_GPIO_10 10
181 +#define RT3883_GPIO_14 14
182 +#define RT3883_GPIO_UART1_TXD 15
183 +#define RT3883_GPIO_UART1_RXD 16
184 +#define RT3883_GPIO_JTAG_TDO 17
185 +#define RT3883_GPIO_JTAG_TDI 18
186 +#define RT3883_GPIO_JTAG_TMS 19
187 +#define RT3883_GPIO_JTAG_TCLK 20
188 +#define RT3883_GPIO_JTAG_TRST_N 21
189 +#define RT3883_GPIO_MDIO_MDC 22
190 +#define RT3883_GPIO_MDIO_MDIO 23
191 +#define RT3883_GPIO_LNA_PE_A0 32
192 +#define RT3883_GPIO_LNA_PE_A1 33
193 +#define RT3883_GPIO_LNA_PE_A2 34
194 +#define RT3883_GPIO_LNA_PE_G0 35
195 +#define RT3883_GPIO_LNA_PE_G1 36
196 +#define RT3883_GPIO_LNA_PE_G2 37
197 +#define RT3883_GPIO_PCI_AD0 40
198 +#define RT3883_GPIO_PCI_AD31 71
199 +#define RT3883_GPIO_GE2_TXD0 72
200 +#define RT3883_GPIO_GE2_TXD1 73
201 +#define RT3883_GPIO_GE2_TXD2 74
202 +#define RT3883_GPIO_GE2_TXD3 75
203 +#define RT3883_GPIO_GE2_TXEN 76
204 +#define RT3883_GPIO_GE2_TXCLK 77
205 +#define RT3883_GPIO_GE2_RXD0 78
206 +#define RT3883_GPIO_GE2_RXD1 79
207 +#define RT3883_GPIO_GE2_RXD2 80
208 +#define RT3883_GPIO_GE2_RXD3 81
209 +#define RT3883_GPIO_GE2_RXDV 82
210 +#define RT3883_GPIO_GE2_RXCLK 83
211 +#define RT3883_GPIO_GE1_TXD0 84
212 +#define RT3883_GPIO_GE1_TXD1 85
213 +#define RT3883_GPIO_GE1_TXD2 86
214 +#define RT3883_GPIO_GE1_TXD3 87
215 +#define RT3883_GPIO_GE1_TXEN 88
216 +#define RT3883_GPIO_GE1_TXCLK 89
217 +#define RT3883_GPIO_GE1_RXD0 90
218 +#define RT3883_GPIO_GE1_RXD1 91
219 +#define RT3883_GPIO_GE1_RXD2 92
220 +#define RT3883_GPIO_GE1_RXD3 93
221 +#define RT3883_GPIO_GE1_RXDV 94
222 +#define RT3883_GPIO_GE1_RXCLK 95
223 +
224 +#define RT3883_RSTCTRL_PCIE_PCI_PDM BIT(27)
225 +#define RT3883_RSTCTRL_FLASH BIT(26)
226 +#define RT3883_RSTCTRL_UDEV BIT(25)
227 +#define RT3883_RSTCTRL_PCI BIT(24)
228 +#define RT3883_RSTCTRL_PCIE BIT(23)
229 +#define RT3883_RSTCTRL_UHST BIT(22)
230 +#define RT3883_RSTCTRL_FE BIT(21)
231 +#define RT3883_RSTCTRL_WLAN BIT(20)
232 +#define RT3883_RSTCTRL_UART1 BIT(29)
233 +#define RT3883_RSTCTRL_SPI BIT(18)
234 +#define RT3883_RSTCTRL_I2S BIT(17)
235 +#define RT3883_RSTCTRL_I2C BIT(16)
236 +#define RT3883_RSTCTRL_NAND BIT(15)
237 +#define RT3883_RSTCTRL_DMA BIT(14)
238 +#define RT3883_RSTCTRL_PIO BIT(13)
239 +#define RT3883_RSTCTRL_UART BIT(12)
240 +#define RT3883_RSTCTRL_PCM BIT(11)
241 +#define RT3883_RSTCTRL_MC BIT(10)
242 +#define RT3883_RSTCTRL_INTC BIT(9)
243 +#define RT3883_RSTCTRL_TIMER BIT(8)
244 +#define RT3883_RSTCTRL_SYS BIT(0)
245 +
246 +#define RT3883_INTC_INT_SYSCTL BIT(0)
247 +#define RT3883_INTC_INT_TIMER0 BIT(1)
248 +#define RT3883_INTC_INT_TIMER1 BIT(2)
249 +#define RT3883_INTC_INT_IA BIT(3)
250 +#define RT3883_INTC_INT_PCM BIT(4)
251 +#define RT3883_INTC_INT_UART0 BIT(5)
252 +#define RT3883_INTC_INT_PIO BIT(6)
253 +#define RT3883_INTC_INT_DMA BIT(7)
254 +#define RT3883_INTC_INT_NAND BIT(8)
255 +#define RT3883_INTC_INT_PERFC BIT(9)
256 +#define RT3883_INTC_INT_I2S BIT(10)
257 +#define RT3883_INTC_INT_UART1 BIT(12)
258 +#define RT3883_INTC_INT_UHST BIT(18)
259 +#define RT3883_INTC_INT_UDEV BIT(19)
260 +
261 +/* FLASH/SRAM/Codec Controller registers */
262 +#define RT3883_FSCC_REG_FLASH_CFG0 0x00
263 +#define RT3883_FSCC_REG_FLASH_CFG1 0x04
264 +#define RT3883_FSCC_REG_CODEC_CFG0 0x40
265 +#define RT3883_FSCC_REG_CODEC_CFG1 0x44
266 +
267 +#define RT3883_FLASH_CFG_WIDTH_SHIFT 26
268 +#define RT3883_FLASH_CFG_WIDTH_MASK 0x3
269 +#define RT3883_FLASH_CFG_WIDTH_8BIT 0x0
270 +#define RT3883_FLASH_CFG_WIDTH_16BIT 0x1
271 +#define RT3883_FLASH_CFG_WIDTH_32BIT 0x2
272 +
273 +#endif /* _RT3883_REGS_H_ */
274 diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig
275 index 0d312fc..f21cbaa 100644
276 --- a/arch/mips/ralink/Kconfig
277 +++ b/arch/mips/ralink/Kconfig
278 @@ -15,6 +15,11 @@ choice
279 select USB_ARCH_HAS_OHCI
280 select USB_ARCH_HAS_EHCI
281
282 + config SOC_RT3883
283 + bool "RT3883"
284 + select USB_ARCH_HAS_OHCI
285 + select USB_ARCH_HAS_EHCI
286 +
287 endchoice
288
289 choice
290 diff --git a/arch/mips/ralink/Makefile b/arch/mips/ralink/Makefile
291 index ce83bfc..87f6ca9 100644
292 --- a/arch/mips/ralink/Makefile
293 +++ b/arch/mips/ralink/Makefile
294 @@ -10,6 +10,7 @@ obj-y := prom.o of.o reset.o clk.o irq.o pinmux.o
295
296 obj-$(CONFIG_SOC_RT288X) += rt288x.o
297 obj-$(CONFIG_SOC_RT305X) += rt305x.o
298 +obj-$(CONFIG_SOC_RT3883) += rt3883.o
299
300 obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
301
302 diff --git a/arch/mips/ralink/Platform b/arch/mips/ralink/Platform
303 index 3f49e51..f67c08d 100644
304 --- a/arch/mips/ralink/Platform
305 +++ b/arch/mips/ralink/Platform
306 @@ -13,3 +13,8 @@ load-$(CONFIG_SOC_RT288X) += 0xffffffff88000000
307 # Ralink RT305x
308 #
309 load-$(CONFIG_SOC_RT305X) += 0xffffffff80000000
310 +
311 +#
312 +# Ralink RT3883
313 +#
314 +load-$(CONFIG_SOC_RT3883) += 0xffffffff80000000
315 diff --git a/arch/mips/ralink/rt3883.c b/arch/mips/ralink/rt3883.c
316 new file mode 100644
317 index 0000000..10a8150
318 --- /dev/null
319 +++ b/arch/mips/ralink/rt3883.c
320 @@ -0,0 +1,207 @@
321 +/*
322 + * This program is free software; you can redistribute it and/or modify it
323 + * under the terms of the GNU General Public License version 2 as published
324 + * by the Free Software Foundation.
325 + *
326 + * Parts of this file are based on Ralink's 2.6.21 BSP
327 + *
328 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
329 + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
330 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
331 + */
332 +
333 +#include <linux/kernel.h>
334 +#include <linux/init.h>
335 +#include <linux/module.h>
336 +
337 +#include <asm/mipsregs.h>
338 +#include <asm/mach-ralink/ralink_regs.h>
339 +#include <asm/mach-ralink/rt3883.h>
340 +
341 +#include "common.h"
342 +
343 +struct ralink_pinmux_grp mode_mux[] = {
344 + {
345 + .name = "i2c",
346 + .mask = RT3883_GPIO_MODE_I2C,
347 + .gpio_first = RT3883_GPIO_I2C_SD,
348 + .gpio_last = RT3883_GPIO_I2C_SCLK,
349 + }, {
350 + .name = "spi",
351 + .mask = RT3883_GPIO_MODE_SPI,
352 + .gpio_first = RT3883_GPIO_SPI_CS0,
353 + .gpio_last = RT3883_GPIO_SPI_MISO,
354 + }, {
355 + .name = "uartlite",
356 + .mask = RT3883_GPIO_MODE_UART1,
357 + .gpio_first = RT3883_GPIO_UART1_TXD,
358 + .gpio_last = RT3883_GPIO_UART1_RXD,
359 + }, {
360 + .name = "jtag",
361 + .mask = RT3883_GPIO_MODE_JTAG,
362 + .gpio_first = RT3883_GPIO_JTAG_TDO,
363 + .gpio_last = RT3883_GPIO_JTAG_TCLK,
364 + }, {
365 + .name = "mdio",
366 + .mask = RT3883_GPIO_MODE_MDIO,
367 + .gpio_first = RT3883_GPIO_MDIO_MDC,
368 + .gpio_last = RT3883_GPIO_MDIO_MDIO,
369 + }, {
370 + .name = "ge1",
371 + .mask = RT3883_GPIO_MODE_GE1,
372 + .gpio_first = RT3883_GPIO_GE1_TXD0,
373 + .gpio_last = RT3883_GPIO_GE1_RXCLK,
374 + }, {
375 + .name = "ge2",
376 + .mask = RT3883_GPIO_MODE_GE2,
377 + .gpio_first = RT3883_GPIO_GE2_TXD0,
378 + .gpio_last = RT3883_GPIO_GE2_RXCLK,
379 + }, {
380 + .name = "pci",
381 + .mask = RT3883_GPIO_MODE_PCI,
382 + .gpio_first = RT3883_GPIO_PCI_AD0,
383 + .gpio_last = RT3883_GPIO_PCI_AD31,
384 + }, {
385 + .name = "lna a",
386 + .mask = RT3883_GPIO_MODE_LNA_A,
387 + .gpio_first = RT3883_GPIO_LNA_PE_A0,
388 + .gpio_last = RT3883_GPIO_LNA_PE_A2,
389 + }, {
390 + .name = "lna g",
391 + .mask = RT3883_GPIO_MODE_LNA_G,
392 + .gpio_first = RT3883_GPIO_LNA_PE_G0,
393 + .gpio_last = RT3883_GPIO_LNA_PE_G2,
394 + }, {0}
395 +};
396 +
397 +struct ralink_pinmux_grp uart_mux[] = {
398 + {
399 + .name = "uartf",
400 + .mask = RT3883_GPIO_MODE_UARTF,
401 + .gpio_first = RT3883_GPIO_7,
402 + .gpio_last = RT3883_GPIO_14,
403 + }, {
404 + .name = "pcm uartf",
405 + .mask = RT3883_GPIO_MODE_PCM_UARTF,
406 + .gpio_first = RT3883_GPIO_7,
407 + .gpio_last = RT3883_GPIO_14,
408 + }, {
409 + .name = "pcm i2s",
410 + .mask = RT3883_GPIO_MODE_PCM_I2S,
411 + .gpio_first = RT3883_GPIO_7,
412 + .gpio_last = RT3883_GPIO_14,
413 + }, {
414 + .name = "i2s uartf",
415 + .mask = RT3883_GPIO_MODE_I2S_UARTF,
416 + .gpio_first = RT3883_GPIO_7,
417 + .gpio_last = RT3883_GPIO_14,
418 + }, {
419 + .name = "pcm gpio",
420 + .mask = RT3883_GPIO_MODE_PCM_GPIO,
421 + .gpio_first = RT3883_GPIO_10,
422 + .gpio_last = RT3883_GPIO_14,
423 + }, {
424 + .name = "gpio uartf",
425 + .mask = RT3883_GPIO_MODE_GPIO_UARTF,
426 + .gpio_first = RT3883_GPIO_7,
427 + .gpio_last = RT3883_GPIO_14,
428 + }, {
429 + .name = "gpio i2s",
430 + .mask = RT3883_GPIO_MODE_GPIO_I2S,
431 + .gpio_first = RT3883_GPIO_7,
432 + .gpio_last = RT3883_GPIO_14,
433 + }, {0}
434 +};
435 +
436 +static void rt3883_wdt_reset(void)
437 +{
438 + u32 t;
439 +
440 + /* enable WDT reset output on GPIO 2 */
441 + t = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG1);
442 + t |= RT3883_SYSCFG1_GPIO2_AS_WDT_OUT;
443 + rt_sysc_w32(t, RT3883_SYSC_REG_SYSCFG1);
444 +}
445 +
446 +struct ralink_pinmux rt_pinmux = {
447 + .mode = mode_mux,
448 + .uart = uart_mux,
449 + .uart_shift = RT3883_GPIO_MODE_UART0_SHIFT,
450 + .uart_mask = RT3883_GPIO_MODE_GPIO,
451 + .wdt_reset = rt3883_wdt_reset,
452 +};
453 +
454 +void __init ralink_clk_init(void)
455 +{
456 + unsigned long cpu_rate, sys_rate;
457 + u32 syscfg0;
458 + u32 clksel;
459 + u32 ddr2;
460 +
461 + syscfg0 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG0);
462 + clksel = ((syscfg0 >> RT3883_SYSCFG0_CPUCLK_SHIFT) &
463 + RT3883_SYSCFG0_CPUCLK_MASK);
464 + ddr2 = syscfg0 & RT3883_SYSCFG0_DRAM_TYPE_DDR2;
465 +
466 + switch (clksel) {
467 + case RT3883_SYSCFG0_CPUCLK_250:
468 + cpu_rate = 250000000;
469 + sys_rate = (ddr2) ? 125000000 : 83000000;
470 + break;
471 + case RT3883_SYSCFG0_CPUCLK_384:
472 + cpu_rate = 384000000;
473 + sys_rate = (ddr2) ? 128000000 : 96000000;
474 + break;
475 + case RT3883_SYSCFG0_CPUCLK_480:
476 + cpu_rate = 480000000;
477 + sys_rate = (ddr2) ? 160000000 : 120000000;
478 + break;
479 + case RT3883_SYSCFG0_CPUCLK_500:
480 + cpu_rate = 500000000;
481 + sys_rate = (ddr2) ? 166000000 : 125000000;
482 + break;
483 + }
484 +
485 + ralink_clk_add("cpu", cpu_rate);
486 + ralink_clk_add("10000100.timer", sys_rate);
487 + ralink_clk_add("10000120.watchdog", sys_rate);
488 + ralink_clk_add("10000500.uart", 40000000);
489 + ralink_clk_add("10000b00.spi", sys_rate);
490 + ralink_clk_add("10000c00.uartlite", 40000000);
491 + ralink_clk_add("10100000.ethernet", sys_rate);
492 +}
493 +
494 +void __init ralink_of_remap(void)
495 +{
496 + rt_sysc_membase = plat_of_remap_node("ralink,rt3883-sysc");
497 + rt_memc_membase = plat_of_remap_node("ralink,rt3883-memc");
498 +
499 + if (!rt_sysc_membase || !rt_memc_membase)
500 + panic("Failed to remap core resources");
501 +}
502 +
503 +void prom_soc_init(struct ralink_soc_info *soc_info)
504 +{
505 + void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT3883_SYSC_BASE);
506 + const char *name;
507 + u32 n0;
508 + u32 n1;
509 + u32 id;
510 +
511 + n0 = __raw_readl(sysc + RT3883_SYSC_REG_CHIPID0_3);
512 + n1 = __raw_readl(sysc + RT3883_SYSC_REG_CHIPID4_7);
513 + id = __raw_readl(sysc + RT3883_SYSC_REG_REVID);
514 +
515 + if (n0 == RT3883_CHIP_NAME0 && n1 == RT3883_CHIP_NAME1) {
516 + soc_info->compatible = "ralink,rt3883-soc";
517 + name = "RT3883";
518 + } else {
519 + panic("rt3883: unknown SoC, n0:%08x n1:%08x", n0, n1);
520 + }
521 +
522 + snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
523 + "Ralink %s ver:%u eco:%u",
524 + name,
525 + (id >> RT3883_REVID_VER_ID_SHIFT) & RT3883_REVID_VER_ID_MASK,
526 + (id & RT3883_REVID_ECO_ID_MASK));
527 +}
528 --
529 1.7.10.4
530
Staging tree of Zoltan Herpai