target/linux/ramips/patches-3.8/0114-GPIO-MIPS-ralink-adds-ralink-gpio-support.patch

   1 From f22c157f44c93d61058d2e2aa5626ee2899fde5a Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Tue, 22 Jan 2013 18:24:34 +0100
   4 Subject: [PATCH 114/121] GPIO: MIPS: ralink: adds ralink gpio support
   5
   6 Add gpio driver for Ralink SoC. This driver makes the gpio core on
   7 RT2880, RT305x, rt3352, rt3662, rt3883, rt5350 and mt7620 work.
   8
   9 Signed-off-by: John Crispin <blogic@openwrt.org>
  10 ---
  11  arch/mips/Kconfig                        |    1 +
  12  arch/mips/include/asm/mach-ralink/gpio.h |   24 ++++
  13  drivers/gpio/Kconfig                     |    6 +
  14  drivers/gpio/Makefile                    |    1 +
  15  drivers/gpio/gpio-ralink.c               |  176 ++++++++++++++++++++++++++++++
  16  5 files changed, 208 insertions(+)
  17  create mode 100644 arch/mips/include/asm/mach-ralink/gpio.h
  18  create mode 100644 drivers/gpio/gpio-ralink.c
  19
  20 diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
  21 index 490d769..1db6ce9 100644
  22 --- a/arch/mips/Kconfig
  23 +++ b/arch/mips/Kconfig
  24 @@ -443,6 +443,7 @@ config RALINK
  25         select SYS_HAS_EARLY_PRINTK
  26         select HAVE_MACH_CLKDEV
  27         select CLKDEV_LOOKUP
  28 +       select ARCH_REQUIRE_GPIOLIB
  29
  30  config SGI_IP22
  31         bool "SGI IP22 (Indy/Indigo2)"
  32 diff --git a/arch/mips/include/asm/mach-ralink/gpio.h b/arch/mips/include/asm/mach-ralink/gpio.h
  33 new file mode 100644
  34 index 0000000..f68ee16
  35 --- /dev/null
  36 +++ b/arch/mips/include/asm/mach-ralink/gpio.h
  37 @@ -0,0 +1,24 @@
  38 +/*
  39 + *  Ralink SoC GPIO API support
  40 + *
  41 + *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
  42 + *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  43 + *
  44 + *  This program is free software; you can redistribute it and/or modify it
  45 + *  under the terms of the GNU General Public License version 2 as published
  46 + *  by the Free Software Foundation.
  47 + *
  48 + */
  49 +
  50 +#ifndef __ASM_MACH_RALINK_GPIO_H
  51 +#define __ASM_MACH_RALINK_GPIO_H
  52 +
  53 +#define ARCH_NR_GPIOS  128
  54 +#include <asm-generic/gpio.h>
  55 +
  56 +#define gpio_get_value __gpio_get_value
  57 +#define gpio_set_value __gpio_set_value
  58 +#define gpio_cansleep  __gpio_cansleep
  59 +#define gpio_to_irq    __gpio_to_irq
  60 +
  61 +#endif /* __ASM_MACH_RALINK_GPIO_H */
  62 diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
  63 index 93aaadf..29add97 100644
  64 --- a/drivers/gpio/Kconfig
  65 +++ b/drivers/gpio/Kconfig
  66 @@ -204,6 +204,12 @@ config GPIO_PXA
  67         help
  68           Say yes here to support the PXA GPIO device
  69
  70 +config GPIO_RALINK
  71 +       bool "Ralink GPIO Support"
  72 +       depends on RALINK
  73 +       help
  74 +         Say yes here to support the Ralink SoC GPIO device
  75 +
  76  config GPIO_SPEAR_SPICS
  77         bool "ST SPEAr13xx SPI Chip Select as GPIO support"
  78         depends on PLAT_SPEAR
  79 diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
  80 index 22e07bc..f7b6603 100644
  81 --- a/drivers/gpio/Makefile
  82 +++ b/drivers/gpio/Makefile
  83 @@ -55,6 +55,7 @@ obj-$(CONFIG_GPIO_PCF857X)    += gpio-pcf857x.o
  84  obj-$(CONFIG_GPIO_PCH)         += gpio-pch.o
  85  obj-$(CONFIG_GPIO_PL061)       += gpio-pl061.o
  86  obj-$(CONFIG_GPIO_PXA)         += gpio-pxa.o
  87 +obj-$(CONFIG_GPIO_RALINK)      += gpio-ralink.o
  88  obj-$(CONFIG_GPIO_RC5T583)     += gpio-rc5t583.o
  89  obj-$(CONFIG_GPIO_RDC321X)     += gpio-rdc321x.o
  90  obj-$(CONFIG_PLAT_SAMSUNG)     += gpio-samsung.o
  91 diff --git a/drivers/gpio/gpio-ralink.c b/drivers/gpio/gpio-ralink.c
  92 new file mode 100644
  93 index 0000000..26e8441
  94 --- /dev/null
  95 +++ b/drivers/gpio/gpio-ralink.c
  96 @@ -0,0 +1,176 @@
  97 +/*
  98 + * This program is free software; you can redistribute it and/or modify it
  99 + * under the terms of the GNU General Public License version 2 as published
 100 + * by the Free Software Foundation.
 101 + *
 102 + * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
 103 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
 104 + */
 105 +
 106 +#include <linux/module.h>
 107 +#include <linux/io.h>
 108 +#include <linux/gpio.h>
 109 +#include <linux/spinlock.h>
 110 +#include <linux/platform_device.h>
 111 +
 112 +enum ralink_gpio_reg {
 113 +       GPIO_REG_INT = 0,
 114 +       GPIO_REG_EDGE,
 115 +       GPIO_REG_RENA,
 116 +       GPIO_REG_FENA,
 117 +       GPIO_REG_DATA,
 118 +       GPIO_REG_DIR,
 119 +       GPIO_REG_POL,
 120 +       GPIO_REG_SET,
 121 +       GPIO_REG_RESET,
 122 +       GPIO_REG_TOGGLE,
 123 +       GPIO_REG_MAX
 124 +};
 125 +
 126 +struct ralink_gpio_chip {
 127 +       struct gpio_chip chip;
 128 +       u8 regs[GPIO_REG_MAX];
 129 +
 130 +       spinlock_t lock;
 131 +       void __iomem *membase;
 132 +};
 133 +
 134 +static inline struct ralink_gpio_chip *to_ralink_gpio(struct gpio_chip *chip)
 135 +{
 136 +       struct ralink_gpio_chip *rg;
 137 +
 138 +       rg = container_of(chip, struct ralink_gpio_chip, chip);
 139 +       return rg;
 140 +}
 141 +
 142 +static inline void rt_gpio_w32(struct ralink_gpio_chip *rg, u8 reg, u32 val)
 143 +{
 144 +       iowrite32(val, rg->membase + rg->regs[reg]);
 145 +}
 146 +
 147 +static inline u32 rt_gpio_r32(struct ralink_gpio_chip *rg, u8 reg)
 148 +{
 149 +       return ioread32(rg->membase + rg->regs[reg]);
 150 +}
 151 +
 152 +static void ralink_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 153 +{
 154 +       struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
 155 +
 156 +       rt_gpio_w32(rg, (value) ? GPIO_REG_SET : GPIO_REG_RESET, BIT(offset));
 157 +}
 158 +
 159 +static int ralink_gpio_get(struct gpio_chip *chip, unsigned offset)
 160 +{
 161 +       struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
 162 +
 163 +       return !!(rt_gpio_r32(rg, GPIO_REG_DATA) & BIT(offset));
 164 +}
 165 +
 166 +static int ralink_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 167 +{
 168 +       struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
 169 +       unsigned long flags;
 170 +       u32 t;
 171 +
 172 +       spin_lock_irqsave(&rg->lock, flags);
 173 +       t = rt_gpio_r32(rg, GPIO_REG_DIR);
 174 +       t &= ~BIT(offset);
 175 +       rt_gpio_w32(rg, GPIO_REG_DIR, t);
 176 +       spin_unlock_irqrestore(&rg->lock, flags);
 177 +
 178 +       return 0;
 179 +}
 180 +
 181 +static int ralink_gpio_direction_output(struct gpio_chip *chip,
 182 +                                       unsigned offset, int value)
 183 +{
 184 +       struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
 185 +       unsigned long flags;
 186 +       u32 t;
 187 +
 188 +       spin_lock_irqsave(&rg->lock, flags);
 189 +       ralink_gpio_set(chip, offset, value);
 190 +       t = rt_gpio_r32(rg, GPIO_REG_DIR);
 191 +       t |= BIT(offset);
 192 +       rt_gpio_w32(rg, GPIO_REG_DIR, t);
 193 +       spin_unlock_irqrestore(&rg->lock, flags);
 194 +
 195 +       return 0;
 196 +}
 197 +
 198 +static int ralink_gpio_probe(struct platform_device *pdev)
 199 +{
 200 +       struct device_node *np = pdev->dev.of_node;
 201 +       struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 202 +       struct ralink_gpio_chip *gc;
 203 +       const __be32 *ngpio;
 204 +
 205 +       if (!res) {
 206 +               dev_err(&pdev->dev, "failed to find resource\n");
 207 +               return -ENOMEM;
 208 +       }
 209 +
 210 +       gc = devm_kzalloc(&pdev->dev,
 211 +                               sizeof(struct ralink_gpio_chip), GFP_KERNEL);
 212 +       if (!gc)
 213 +               return -ENOMEM;
 214 +
 215 +       gc->membase = devm_request_and_ioremap(&pdev->dev, res);
 216 +       if (!gc->membase) {
 217 +               dev_err(&pdev->dev, "cannot remap I/O memory region\n");
 218 +               return -ENOMEM;
 219 +       }
 220 +
 221 +       if (of_property_read_u8_array(np, "ralink,register-map",
 222 +                       gc->regs, GPIO_REG_MAX)) {
 223 +               dev_err(&pdev->dev, "failed to read register definition\n");
 224 +               return -EINVAL;
 225 +       }
 226 +
 227 +       ngpio = of_get_property(np, "ralink,num-gpios", NULL);
 228 +       if (!ngpio) {
 229 +               dev_err(&pdev->dev, "failed to read number of pins\n");
 230 +               return -EINVAL;
 231 +       }
 232 +
 233 +       spin_lock_init(&gc->lock);
 234 +
 235 +       gc->chip.label = dev_name(&pdev->dev);
 236 +       gc->chip.of_node = np;
 237 +       gc->chip.base = -1;
 238 +       gc->chip.ngpio = be32_to_cpu(*ngpio);
 239 +       gc->chip.direction_input = ralink_gpio_direction_input;
 240 +       gc->chip.direction_output = ralink_gpio_direction_output;
 241 +       gc->chip.get = ralink_gpio_get;
 242 +       gc->chip.set = ralink_gpio_set;
 243 +
 244 +       /* set polarity to low for all lines */
 245 +       rt_gpio_w32(gc, GPIO_REG_POL, 0);
 246 +
 247 +       dev_info(&pdev->dev, "registering %d gpios\n", gc->chip.ngpio);
 248 +
 249 +       return gpiochip_add(&gc->chip);
 250 +}
 251 +
 252 +static const struct of_device_id ralink_gpio_match[] = {
 253 +       { .compatible = "ralink,rt2880-gpio" },
 254 +       {},
 255 +};
 256 +MODULE_DEVICE_TABLE(of, ralink_gpio_match);
 257 +
 258 +static struct platform_driver ralink_gpio_driver = {
 259 +       .probe = ralink_gpio_probe,
 260 +       .driver = {
 261 +               .name = "rt2880_gpio",
 262 +               .owner = THIS_MODULE,
 263 +               .of_match_table = ralink_gpio_match,
 264 +       },
 265 +};
 266 +
 267 +static int __init ralink_gpio_init(void)
 268 +{
 269 +       return platform_driver_register(&ralink_gpio_driver);
 270 +}
 271 +
 272 +subsys_initcall(ralink_gpio_init);
 273 --
 274 1.7.10.4
 275