target/linux/ramips/patches-3.9/0148-DMA-MIPS-ralink-add-dmaengine-driver.patch

   1 From 27eef043b05fb8d9d3178fd3352c530f71901dd4 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Thu, 23 May 2013 18:45:29 +0200
   4 Subject: [PATCH 148/164] DMA: MIPS: ralink: add dmaengine driver
   5
   6 Signed-off-by: John Crispin <blogic@openwrt.org>
   7 ---
   8  drivers/dma/Kconfig       |    7 ++
   9  drivers/dma/Makefile      |    1 +
  10  drivers/dma/ralink_gdma.c |  229 +++++++++++++++++++++++++++++++++++++++++++++
  11  drivers/dma/ralink_gdma.h |   55 +++++++++++
  12  4 files changed, 292 insertions(+)
  13  create mode 100644 drivers/dma/ralink_gdma.c
  14  create mode 100644 drivers/dma/ralink_gdma.h
  15
  16 --- a/drivers/dma/Kconfig
  17 +++ b/drivers/dma/Kconfig
  18 @@ -322,6 +322,13 @@ config MMP_PDMA
  19         help
  20           Support the MMP PDMA engine for PXA and MMP platfrom.
  21
  22 +config RALINK_GDMA
  23 +       bool "Ralink Generic DMA support"
  24 +       depends on RALINK
  25 +       select DMA_ENGINE
  26 +       help
  27 +         Support the GDMA engine for MIPS based Ralink SoC.
  28 +
  29  config DMA_ENGINE
  30         bool
  31
  32 --- a/drivers/dma/Makefile
  33 +++ b/drivers/dma/Makefile
  34 @@ -37,3 +37,4 @@ obj-$(CONFIG_DMA_SA11X0) += sa11x0-dma.o
  35  obj-$(CONFIG_MMP_TDMA) += mmp_tdma.o
  36  obj-$(CONFIG_DMA_OMAP) += omap-dma.o
  37  obj-$(CONFIG_MMP_PDMA) += mmp_pdma.o
  38 +obj-$(CONFIG_RALINK_GDMA) += ralink_gdma.o
  39 --- /dev/null
  40 +++ b/drivers/dma/ralink_gdma.c
  41 @@ -0,0 +1,229 @@
  42 +#include <linux/init.h>
  43 +#include <linux/module.h>
  44 +#include <linux/slab.h>
  45 +#include <linux/delay.h>
  46 +#include <linux/dma-mapping.h>
  47 +#include <linux/spinlock.h>
  48 +#include <linux/interrupt.h>
  49 +#include <linux/platform_device.h>
  50 +#include <linux/of_platform.h>
  51 +#include <linux/memory.h>
  52 +
  53 +#include "ralink_gdma.h"
  54 +
  55 +#define SURFBOARDINT_DMA       10
  56 +#define MEMCPY_DMA_CH  8
  57 +#define to_rt2880_dma_chan(chan)            \
  58 +       container_of(chan, struct rt2880_dma_chan, common)
  59 +
  60 +static dma_cookie_t rt2880_dma_tx_submit(struct dma_async_tx_descriptor *tx)
  61 +{
  62 +       dma_cookie_t cookie;
  63 +
  64 +       cookie = tx->chan->cookie;
  65 +
  66 +       return cookie;
  67 +}
  68 +
  69 +#define MIN_RTDMA_PKT_LEN      128
  70 +static struct dma_async_tx_descriptor *
  71 +rt2880_dma_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
  72 +               size_t len, unsigned long flags)
  73 +{
  74 +       struct rt2880_dma_chan *rt_chan = to_rt2880_dma_chan(chan);
  75 +       unsigned long mid_offset;
  76 +
  77 +       spin_lock_bh(&rt_chan->lock);
  78 +
  79 +       if(len < MIN_RTDMA_PKT_LEN) {
  80 +               memcpy(phys_to_virt(dest), phys_to_virt(src), len);
  81 +       } else {
  82 +               mid_offset = len/2;
  83 +
  84 +               /* Lower parts are transferred  by GDMA.
  85 +                * Upper parts are transferred by CPU.
  86 +                */
  87 +               RT_DMA_WRITE_REG(RT_DMA_SRC_REG(MEMCPY_DMA_CH), src);
  88 +               RT_DMA_WRITE_REG(RT_DMA_DST_REG(MEMCPY_DMA_CH), dest);
  89 +               RT_DMA_WRITE_REG(RT_DMA_CTRL_REG(MEMCPY_DMA_CH), (mid_offset << 16) | (3 << 3) | (3 << 0));
  90 +
  91 +               memcpy(phys_to_virt(dest)+mid_offset, phys_to_virt(src)+mid_offset, len-mid_offset);
  92 +
  93 +               dma_async_tx_descriptor_init(&rt_chan->txd, chan);
  94 +
  95 +               while((RT_DMA_READ_REG(RT_DMA_DONEINT) & (0x1<<MEMCPY_DMA_CH))==0);
  96 +               RT_DMA_WRITE_REG(RT_DMA_DONEINT, (1<<MEMCPY_DMA_CH));
  97 +       }
  98 +
  99 +       spin_unlock_bh(&rt_chan->lock);
 100 +
 101 +       return &rt_chan->txd;
 102 +}
 103 +
 104 +/**
 105 + * rt2880_dma_status - poll the status of an XOR transaction
 106 + * @chan: XOR channel handle
 107 + * @cookie: XOR transaction identifier
 108 + * @txstate: XOR transactions state holder (or NULL)
 109 + */
 110 +static enum dma_status rt2880_dma_status(struct dma_chan *chan,
 111 +                                         dma_cookie_t cookie,
 112 +                                         struct dma_tx_state *txstate)
 113 +{
 114 +       return 0;
 115 +}
 116 +
 117 +static irqreturn_t rt2880_dma_interrupt_handler(int irq, void *data)
 118 +{
 119 +
 120 +       printk("%s\n",__FUNCTION__);
 121 +
 122 +       return IRQ_HANDLED;
 123 +}
 124 +
 125 +static void rt2880_dma_issue_pending(struct dma_chan *chan)
 126 +{
 127 +}
 128 +
 129 +static int rt2880_dma_alloc_chan_resources(struct dma_chan *chan)
 130 +{
 131 +//     printk("%s\n",__FUNCTION__);
 132 +
 133 +       return 0;
 134 +}
 135 +
 136 +static void rt2880_dma_free_chan_resources(struct dma_chan *chan)
 137 +{
 138 +//     printk("%s\n",__FUNCTION__);
 139 +
 140 +}
 141 +
 142 +static int rt2880_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, unsigned long arg)
 143 +{
 144 +       switch (cmd) {
 145 +       case DMA_TERMINATE_ALL:
 146 +               printk("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
 147 +               break;
 148 +       case DMA_SLAVE_CONFIG:
 149 +               printk("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
 150 +               break;
 151 +       default:
 152 +               return -ENXIO;
 153 +       }
 154 +
 155 +       return 0;
 156 +}
 157 +
 158 +static int rt2880_dma_probe(struct platform_device *pdev)
 159 +{
 160 +       struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 161 +       __iomem void *membase;
 162 +       struct dma_device *dma_dev;
 163 +       struct rt2880_dma_chan *rt_chan;
 164 +       int err;
 165 +       int ret;
 166 +       int reg;
 167 +       int irq;
 168 +
 169 +       membase = devm_request_and_ioremap(&pdev->dev, res);
 170 +       if (IS_ERR(membase))
 171 +               return PTR_ERR(membase);
 172 +
 173 +       dma_dev = devm_kzalloc(&pdev->dev, sizeof(*dma_dev), GFP_KERNEL);
 174 +       if (!dma_dev)
 175 +               return -ENOMEM;
 176 +
 177 +       irq = platform_get_irq(pdev, 0);
 178 +       if (!irq) {
 179 +               dev_err(&pdev->dev, "failed to load irq\n");
 180 +               return -ENOENT;
 181 +       }
 182 +
 183 +
 184 +       INIT_LIST_HEAD(&dma_dev->channels);
 185 +       dma_cap_zero(dma_dev->cap_mask);
 186 +       dma_cap_set(DMA_MEMCPY, dma_dev->cap_mask);
 187 +       dma_cap_set(DMA_SLAVE, dma_dev->cap_mask);
 188 +       dma_dev->device_alloc_chan_resources = rt2880_dma_alloc_chan_resources;
 189 +       dma_dev->device_free_chan_resources = rt2880_dma_free_chan_resources;
 190 +       dma_dev->device_tx_status = rt2880_dma_status;
 191 +       dma_dev->device_issue_pending = rt2880_dma_issue_pending;
 192 +       dma_dev->device_prep_dma_memcpy = rt2880_dma_prep_dma_memcpy;
 193 +       dma_dev->device_control = rt2880_dma_control;
 194 +       dma_dev->dev = &pdev->dev;
 195 +
 196 +       rt_chan = devm_kzalloc(&pdev->dev, sizeof(*rt_chan), GFP_KERNEL);
 197 +        if (!rt_chan) {
 198 +               return -ENOMEM;
 199 +       }
 200 +
 201 +       spin_lock_init(&rt_chan->lock);
 202 +        INIT_LIST_HEAD(&rt_chan->chain);
 203 +       INIT_LIST_HEAD(&rt_chan->completed_slots);
 204 +       INIT_LIST_HEAD(&rt_chan->all_slots);
 205 +       rt_chan->common.device = dma_dev;
 206 +       rt_chan->txd.tx_submit = rt2880_dma_tx_submit;
 207 +
 208 +       list_add_tail(&rt_chan->common.device_node, &dma_dev->channels);
 209 +
 210 +       err = dma_async_device_register(dma_dev);
 211 +       if (0 != err) {
 212 +               pr_err("ERR_MDMA:device_register failed: %d\n", err);
 213 +               return 1;
 214 +       }
 215 +
 216 +       ret = request_irq(irq, rt2880_dma_interrupt_handler, 0, dev_name(&pdev->dev), NULL);
 217 +       if(ret){
 218 +               pr_err("IRQ %d is not free.\n", SURFBOARDINT_DMA);
 219 +               return 1;
 220 +       }
 221 +
 222 +       //set GDMA register in advance.
 223 +       reg = (32 << 16) | (32 << 8) | (MEMCPY_DMA_CH << 3);
 224 +       RT_DMA_WRITE_REG(RT_DMA_CTRL_REG1(MEMCPY_DMA_CH), reg);
 225 +
 226 +       dev_info(&pdev->dev, "running\n");
 227 +
 228 +       return 0;
 229 +}
 230 +
 231 +static int rt2880_dma_remove(struct platform_device *dev)
 232 +{
 233 +       struct dma_device *dma_dev = platform_get_drvdata(dev);
 234 +
 235 +       printk("%s\n",__FUNCTION__);
 236 +
 237 +       dma_async_device_unregister(dma_dev);
 238 +
 239 +       return 0;
 240 +}
 241 +
 242 +static const struct of_device_id rt2880_dma_match[] = {
 243 +       { .compatible = "ralink,rt2880-gdma" },
 244 +       {},
 245 +};
 246 +MODULE_DEVICE_TABLE(of, rt2880_wdt_match);
 247 +
 248 +static struct platform_driver rt2880_dma_driver = {
 249 +       .probe          = rt2880_dma_probe,
 250 +       .remove         = rt2880_dma_remove,
 251 +       .driver         = {
 252 +               .owner  = THIS_MODULE,
 253 +               .name   = RT_DMA_NAME,
 254 +               .of_match_table = rt2880_dma_match,
 255 +       },
 256 +};
 257 +
 258 +static int __init rt2880_dma_init(void)
 259 +{
 260 +       int rc;
 261 +
 262 +       rc = platform_driver_register(&rt2880_dma_driver);
 263 +       return rc;
 264 +}
 265 +module_init(rt2880_dma_init);
 266 +
 267 +MODULE_AUTHOR("Steven Liu <steven_liu@mediatek.com>");
 268 +MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
 269 +MODULE_DESCRIPTION("DMA engine driver for Ralink DMA engine");
 270 +MODULE_LICENSE("GPL");
 271 --- /dev/null
 272 +++ b/drivers/dma/ralink_gdma.h
 273 @@ -0,0 +1,55 @@
 274 +/*
 275 + * Copyright (C) 2007, 2008, Marvell International Ltd.
 276 + *
 277 + * This program is free software; you can redistribute it and/or modify
 278 + * it under the terms and conditions of the GNU General Public License,
 279 + * version 2, as published by the Free Software Foundation.
 280 + *
 281 + * This program is distributed in the hope it will be useful, but WITHOUT
 282 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 283 + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 284 + * for more details.
 285 + *
 286 + * You should have received a copy of the GNU General Public License
 287 + * along with this program; if not, write to the Free Software Foundation,
 288 + * Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
 289 + */
 290 +
 291 +#ifndef RT_DMA_H
 292 +#define RT_DMA_H
 293 +
 294 +#include <linux/types.h>
 295 +#include <linux/io.h>
 296 +#include <linux/dmaengine.h>
 297 +#include <linux/interrupt.h>
 298 +
 299 +#define RT_DMA_NAME            "rt2880_dma"
 300 +
 301 +#define RALINK_GDMA_BASE       0xB0002800
 302 +
 303 +struct rt2880_dma_chan {
 304 +        int                     pending;
 305 +        dma_cookie_t            completed_cookie;
 306 +        spinlock_t              lock; /* protects the descriptor slot pool */
 307 +        void __iomem            *mmr_base;
 308 +        unsigned int            idx;
 309 +        enum dma_transaction_type       current_type;
 310 +       struct dma_async_tx_descriptor txd;
 311 +        struct list_head        chain;
 312 +        struct list_head        completed_slots;
 313 +        struct dma_chan         common;
 314 +        struct list_head        all_slots;
 315 +        int                     slots_allocated;
 316 +        struct tasklet_struct   irq_tasklet;
 317 +};
 318 +
 319 +#define RT_DMA_READ_REG(addr)             le32_to_cpu(*(volatile u32 *)(addr))
 320 +#define RT_DMA_WRITE_REG(addr, val)       *((volatile uint32_t *)(addr)) = cpu_to_le32(val)
 321 +
 322 +#define RT_DMA_SRC_REG(ch)                (RALINK_GDMA_BASE + ch*16)
 323 +#define RT_DMA_DST_REG(ch)                (RT_DMA_SRC_REG(ch) + 4)
 324 +#define RT_DMA_CTRL_REG(ch)               (RT_DMA_DST_REG(ch) + 4)
 325 +#define RT_DMA_CTRL_REG1(ch)              (RT_DMA_CTRL_REG(ch) + 4)
 326 +#define RT_DMA_DONEINT                   (RALINK_GDMA_BASE + 0x204)
 327 +
 328 +#endif