target/linux/ramips/patches-4.3/0021-arch-mips-ralink-add-mt7688-detection.patch

   1 From 14ef339843c24bf449d0f6d8bc176368c331c2c8 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Mon, 7 Dec 2015 17:29:00 +0100
   4 Subject: [PATCH 21/53] arch: mips: ralink: add mt7688 detection
   5
   6 Signed-off-by: John Crispin <blogic@openwrt.org>
   7 ---
   8  arch/mips/include/asm/mach-ralink/mt7620.h      |    1 +
   9  arch/mips/include/asm/mach-ralink/ralink_regs.h |    1 +
  10  arch/mips/ralink/mt7620.c                       |   21 ++++++++++++++++-----
  11  3 files changed, 18 insertions(+), 5 deletions(-)
  12
  13 --- a/arch/mips/include/asm/mach-ralink/mt7620.h
  14 +++ b/arch/mips/include/asm/mach-ralink/mt7620.h
  15 @@ -17,6 +17,7 @@
  16
  17  #define SYSC_REG_CHIP_NAME0            0x00
  18  #define SYSC_REG_CHIP_NAME1            0x04
  19 +#define SYSC_REG_EFUSE_CFG             0x08
  20  #define SYSC_REG_CHIP_REV              0x0c
  21  #define SYSC_REG_SYSTEM_CONFIG0                0x10
  22  #define SYSC_REG_SYSTEM_CONFIG1                0x14
  23 --- a/arch/mips/include/asm/mach-ralink/ralink_regs.h
  24 +++ b/arch/mips/include/asm/mach-ralink/ralink_regs.h
  25 @@ -24,6 +24,7 @@ enum ralink_soc_type {
  26         MT762X_SOC_MT7620N,
  27         MT762X_SOC_MT7621AT,
  28         MT762X_SOC_MT7628AN,
  29 +       MT762X_SOC_MT7688,
  30  };
  31  extern enum ralink_soc_type ralink_soc;
  32
  33 --- a/arch/mips/ralink/mt7620.c
  34 +++ b/arch/mips/ralink/mt7620.c
  35 @@ -46,6 +46,9 @@ enum mt762x_soc_type mt762x_soc;
  36  #define CLKCFG_FFRAC_MASK      0x001f
  37  #define CLKCFG_FFRAC_USB_VAL   0x0003
  38
  39 +/* EFUSE bits */
  40 +#define EFUSE_MT7688           0x100000
  41 +
  42  /* does the board have sdram or ddram */
  43  static int dram_type;
  44
  45 @@ -407,7 +410,7 @@ void __init ralink_clk_init(void)
  46  #define RINT(x)                ((x) / 1000000)
  47  #define RFRAC(x)       (((x) / 1000) % 1000)
  48
  49 -       if (mt762x_soc == MT762X_SOC_MT7628AN) {
  50 +       if (mt762x_soc == MT762X_SOC_MT7628AN || mt762x_soc == MT762X_SOC_MT7688) {
  51                 if (xtal_rate == MHZ(40))
  52                         cpu_rate = MHZ(580);
  53                 else
  54 @@ -451,7 +454,8 @@ void __init ralink_clk_init(void)
  55         ralink_clk_add("10000c00.uartlite", periph_rate);
  56         ralink_clk_add("10180000.wmac", xtal_rate);
  57
  58 -       if (IS_ENABLED(CONFIG_USB)) {
  59 +       if (IS_ENABLED(CONFIG_USB) &&
  60 +               (mt762x_soc == MT762X_SOC_MT7620A || mt762x_soc == MT762X_SOC_MT7620N)) {
  61                 /*
  62                  * When the CPU goes into sleep mode, the BUS clock will be too low for
  63                  * USB to function properly
  64 @@ -548,8 +552,15 @@ void prom_soc_init(struct ralink_soc_inf
  65                         soc_info->compatible = "ralink,mt7620n-soc";
  66                 }
  67         } else if (n0 == MT7620_CHIP_NAME0 && n1 == MT7628_CHIP_NAME1) {
  68 -               mt762x_soc = MT762X_SOC_MT7628AN;
  69 -               name = "MT7628AN";
  70 +               u32 efuse = __raw_readl(sysc + SYSC_REG_EFUSE_CFG);
  71 +
  72 +               if (efuse & EFUSE_MT7688) {
  73 +                       mt762x_soc = MT762X_SOC_MT7688;
  74 +                       name = "MT7688";
  75 +               } else {
  76 +                       mt762x_soc = MT762X_SOC_MT7628AN;
  77 +                       name = "MT7628AN";
  78 +               }
  79                 soc_info->compatible = "ralink,mt7628an-soc";
  80         } else {
  81                 panic("mt762x: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
  82 @@ -582,7 +593,7 @@ void prom_soc_init(struct ralink_soc_inf
  83         pr_info("Digital PMU set to %s control\n",
  84                 (pmu1 & DIG_SW_SEL) ? ("sw") : ("hw"));
  85
  86 -       if (mt762x_soc == MT762X_SOC_MT7628AN)
  87 +       if (mt762x_soc == MT762X_SOC_MT7628AN || mt762x_soc == MT762X_SOC_MT7688)
  88                 rt2880_pinmux_data = mt7628an_pinmux_data;
  89         else
  90                 rt2880_pinmux_data = mt7620a_pinmux_data;