target/linux/realtek/dts-5.10/rtl838x.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2
   3 #include <dt-bindings/clock/rtl83xx-clk.h>
   4
   5 /dts-v1/;
   6
   7 #define STRINGIZE(s) #s
   8 #define LAN_LABEL(p, s) STRINGIZE(p ## s)
   9 #define SWITCH_PORT_LABEL(n) LAN_LABEL(lan, n)
  10
  11 #define INTERNAL_PHY(n) \
  12         phy##n: ethernet-phy@##n { \
  13                 reg = <##n>; \
  14                 compatible = "ethernet-phy-ieee802.3-c22"; \
  15                 phy-is-integrated; \
  16         };
  17
  18 #define EXTERNAL_PHY(n) \
  19         phy##n: ethernet-phy@##n { \
  20                 reg = <##n>; \
  21                 compatible = "ethernet-phy-ieee802.3-c22"; \
  22         };
  23
  24 #define EXTERNAL_SFP_PHY(n) \
  25         phy##n: ethernet-phy@##n { \
  26                 compatible = "ethernet-phy-ieee802.3-c22"; \
  27                 sfp; \
  28                 media = "fibre"; \
  29                 reg = <##n>; \
  30         };
  31
  32 #define EXTERNAL_SFP_PHY_FULL(n, s) \
  33         phy##n: ethernet-phy@##n { \
  34                 compatible = "ethernet-phy-ieee802.3-c22"; \
  35                 sfp = <&sfp##s>; \
  36                 reg = <##n>; \
  37         };
  38
  39 #define SWITCH_PORT(n, s, m) \
  40         port##n: port@##n { \
  41                 reg = <##n>; \
  42                 label = SWITCH_PORT_LABEL(s) ; \
  43                 phy-handle = <&phy##n>; \
  44                 phy-mode = #m ; \
  45         };
  46
  47 #define SWITCH_SFP_PORT(n, s, m) \
  48         port##n: port@##n { \
  49                 reg = <##n>; \
  50                 label = SWITCH_PORT_LABEL(s) ; \
  51                 phy-handle = <&phy##n>; \
  52                 phy-mode = #m ; \
  53                 fixed-link { \
  54                         speed = <1000>; \
  55                         full-duplex; \
  56                 }; \
  57         };
  58
  59 / {
  60         #address-cells = <1>;
  61         #size-cells = <1>;
  62
  63         compatible = "realtek,rtl838x-soc";
  64
  65         osc: oscillator {
  66                 compatible = "fixed-clock";
  67                 #clock-cells = <0>;
  68                 clock-frequency = <25000000>;
  69         };
  70
  71         ccu: clock-controller {
  72                 compatible = "realtek,rtl8380-clock";
  73                 #clock-cells = <1>;
  74                 clocks = <&osc>;
  75                 clock-names = "ref_clk";
  76         };
  77
  78         cpus {
  79                 #address-cells = <1>;
  80                 #size-cells = <0>;
  81
  82                 cpu@0 {
  83                         compatible = "mips,mips4KEc";
  84                         reg = <0>;
  85                         clocks = <&ccu CLK_CPU>;
  86                         operating-points-v2 = <&cpu_opp_table>;
  87                 };
  88         };
  89
  90         cpu_opp_table: opp-table-0 {
  91                 compatible = "operating-points-v2";
  92                 opp-shared;
  93
  94                 opp00 {
  95                         opp-hz = /bits/ 64 <325000000>;
  96                 };
  97                 opp01 {
  98                         opp-hz = /bits/ 64 <350000000>;
  99                 };
 100                 opp02 {
 101                         opp-hz = /bits/ 64 <375000000>;
 102                 };
 103                 opp03 {
 104                         opp-hz = /bits/ 64 <400000000>;
 105                 };
 106                 opp04 {
 107                         opp-hz = /bits/ 64 <425000000>;
 108                 };
 109                 opp05 {
 110                         opp-hz = /bits/ 64 <450000000>;
 111                 };
 112                 opp06 {
 113                         opp-hz = /bits/ 64 <475000000>;
 114                 };
 115                 opp07 {
 116                         opp-hz = /bits/ 64 <500000000>;
 117                 };
 118         };
 119
 120         chosen {
 121                 bootargs = "console=ttyS0,115200";
 122         };
 123
 124         cpuintc: cpuintc {
 125                 compatible = "mti,cpu-interrupt-controller";
 126                 #address-cells = <0>;
 127                 #interrupt-cells = <1>;
 128                 interrupt-controller;
 129         };
 130
 131         soc: soc {
 132                 compatible = "simple-bus";
 133                 #address-cells = <1>;
 134                 #size-cells = <1>;
 135                 ranges = <0x0 0x18000000 0x10000>;
 136
 137                 intc: interrupt-controller@3000 {
 138                         compatible = "realtek,rtl8380-intc", "realtek,rtl-intc";
 139                         reg = <0x3000 0x18>;
 140                         interrupt-controller;
 141                         #interrupt-cells = <2>;
 142
 143                         interrupt-parent = <&cpuintc>;
 144                         interrupts = <2>, <3>, <4>, <5>, <6>;
 145                 };
 146
 147                 spi0: spi@1200 {
 148                         compatible = "realtek,rtl8380-spi";
 149                         reg = <0x1200 0x100>;
 150
 151                         #address-cells = <1>;
 152                         #size-cells = <0>;
 153                 };
 154
 155                 uart0: uart@2000 {
 156                         compatible = "ns16550a";
 157                         reg = <0x2000 0x100>;
 158
 159                         clocks = <&ccu CLK_LXB>;
 160
 161                         interrupt-parent = <&intc>;
 162                         interrupts = <31 1>;
 163
 164                         reg-io-width = <1>;
 165                         reg-shift = <2>;
 166                         fifo-size = <1>;
 167                         no-loopback-test;
 168                 };
 169
 170                 uart1: uart@2100 {
 171                         pinctrl-names = "default";
 172                         pinctrl-0 = <&enable_uart1>;
 173
 174                         compatible = "ns16550a";
 175                         reg = <0x2100 0x100>;
 176
 177                         clocks = <&ccu CLK_LXB>;
 178
 179                         interrupt-parent = <&intc>;
 180                         interrupts = <30 0>;
 181
 182                         reg-io-width = <1>;
 183                         reg-shift = <2>;
 184                         fifo-size = <1>;
 185                         no-loopback-test;
 186
 187                         status = "disabled";
 188                 };
 189
 190                 watchdog0: watchdog@3150 {
 191                         compatible = "realtek,rtl8380-wdt";
 192                         reg = <0x3150 0xc>;
 193
 194                         realtek,reset-mode = "soc";
 195
 196                         clocks = <&ccu CLK_LXB>;
 197                         timeout-sec = <30>;
 198
 199                         interrupt-parent = <&intc>;
 200                         interrupt-names = "phase1", "phase2";
 201                         interrupts = <19 3>, <18 4>;
 202                 };
 203
 204                 gpio0: gpio-controller@3500 {
 205                         compatible = "realtek,rtl8380-gpio", "realtek,otto-gpio";
 206                         reg = <0x3500 0x20>;
 207
 208                         gpio-controller;
 209                         #gpio-cells = <2>;
 210                         ngpios = <24>;
 211
 212                         interrupt-controller;
 213                         #interrupt-cells = <2>;
 214                         interrupt-parent = <&intc>;
 215                         interrupts = <23 3>;
 216                 };
 217         };
 218
 219         pinmux: pinmux@1b001000 {
 220                 compatible = "pinctrl-single";
 221                 reg = <0x1b001000 0x4>;
 222
 223                 pinctrl-single,bit-per-mux;
 224                 pinctrl-single,register-width = <32>;
 225                 pinctrl-single,function-mask = <0x1>;
 226                 #pinctrl-cells = <2>;
 227
 228                 enable_uart1: pinmux_enable_uart1 {
 229                         pinctrl-single,bits = <0x0 0x10 0x10>;
 230                 };
 231         };
 232
 233         /* LED_GLB_CTRL */
 234         pinmux_led: pinmux@1b00a000 {
 235                 compatible = "pinctrl-single";
 236                 reg = <0x1b00a000 0x4>;
 237
 238                 pinctrl-single,bit-per-mux;
 239                 pinctrl-single,register-width = <32>;
 240                 pinctrl-single,function-mask = <0x1>;
 241                 #pinctrl-cells = <2>;
 242
 243                 /* enable GPIO 0 */
 244                 pinmux_disable_sys_led: disable_sys_led {
 245                         pinctrl-single,bits = <0x0 0x0 0x8000>;
 246                 };
 247         };
 248
 249         ethernet0: ethernet@1b00a300 {
 250                 compatible = "realtek,rtl838x-eth";
 251                 reg = <0x1b00a300 0x100>;
 252                 interrupt-parent = <&intc>;
 253                 interrupts = <24 3>;
 254                 #interrupt-cells = <1>;
 255                 phy-mode = "internal";
 256
 257                 fixed-link {
 258                         speed = <1000>;
 259                         full-duplex;
 260                 };
 261         };
 262
 263         sram0: sram@9f000000 {
 264                 compatible = "mmio-sram";
 265                 reg = <0x9f000000 0x10000>;
 266                 #address-cells = <1>;
 267                 #size-cells = <1>;
 268                 ranges = <0 0x9f000000 0x10000>;
 269         };
 270
 271         switch0: switch@1b000000 {
 272                 compatible = "realtek,rtl83xx-switch";
 273
 274                 interrupt-parent = <&intc>;
 275                 interrupts = <20 2>;
 276         };
 277 };