target/linux/realtek/files-5.10/arch/mips/rtl838x/setup.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Setup for the Realtek RTL838X SoC:
   4  *      Memory, Timer and Serial
   5  *
   6  * Copyright (C) 2020 B. Koblitz
   7  * based on the original BSP by
   8  * Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com)
   9  *
  10  */
  11
  12 #include <linux/console.h>
  13 #include <linux/init.h>
  14 #include <linux/clkdev.h>
  15 #include <linux/clk-provider.h>
  16 #include <linux/delay.h>
  17 #include <linux/of_fdt.h>
  18 #include <linux/irqchip.h>
  19
  20 #include <asm/addrspace.h>
  21 #include <asm/io.h>
  22 #include <asm/bootinfo.h>
  23 #include <asm/time.h>
  24 #include <asm/prom.h>
  25 #include <asm/smp-ops.h>
  26
  27 #include "mach-rtl83xx.h"
  28
  29 extern struct rtl83xx_soc_info soc_info;
  30
  31 static void __init rtl838x_setup(void)
  32 {
  33         /* Setup System LED. Bit 15 then allows to toggle it */
  34         sw_w32_mask(0, 3 << 16, RTL838X_LED_GLB_CTRL);
  35 }
  36
  37 static void __init rtl839x_setup(void)
  38 {
  39         /* Setup System LED. Bit 14 of RTL839X_LED_GLB_CTRL then allows to toggle it */
  40         sw_w32_mask(0, 3 << 15, RTL839X_LED_GLB_CTRL);
  41 }
  42
  43 static void __init rtl930x_setup(void)
  44 {
  45         if (soc_info.id == 0x9302)
  46                 sw_w32_mask(0, 3 << 13, RTL9302_LED_GLB_CTRL);
  47         else
  48                 sw_w32_mask(0, 3 << 13, RTL930X_LED_GLB_CTRL);
  49 }
  50
  51 static void __init rtl931x_setup(void)
  52 {
  53         sw_w32_mask(0, 3 << 12, RTL931X_LED_GLB_CTRL);
  54 }
  55
  56 void __init plat_mem_setup(void)
  57 {
  58         void *dtb;
  59
  60         set_io_port_base(KSEG1);
  61
  62         if (fw_passed_dtb) /* UHI interface */
  63                 dtb = (void *)fw_passed_dtb;
  64         else if (__dtb_start != __dtb_end)
  65                 dtb = (void *)__dtb_start;
  66         else
  67                 panic("no dtb found");
  68
  69         /*
  70          * Load the devicetree. This causes the chosen node to be
  71          * parsed resulting in our memory appearing
  72          */
  73         __dt_setup_arch(dtb);
  74
  75         switch (soc_info.family) {
  76         case RTL8380_FAMILY_ID:
  77                 rtl838x_setup();
  78                 break;
  79         case RTL8390_FAMILY_ID:
  80                 rtl839x_setup();
  81                 break;
  82         case RTL9300_FAMILY_ID:
  83                 rtl930x_setup();
  84                 break;
  85         case RTL9310_FAMILY_ID:
  86                 rtl931x_setup();
  87                 break;
  88         }
  89 }
  90
  91 void __init plat_time_init(void)
  92 {
  93         struct device_node *np;
  94         u32 freq = 500000000;
  95
  96         of_clk_init(NULL);
  97         timer_probe();
  98
  99         np = of_find_node_by_name(NULL, "cpus");
 100         if (!np) {
 101                 pr_err("Missing 'cpus' DT node, using default frequency.");
 102         } else {
 103                 if (of_property_read_u32(np, "frequency", &freq) < 0)
 104                         pr_err("No 'frequency' property in DT, using default.");
 105                 else
 106                         pr_info("CPU frequency from device tree: %dMHz", freq / 1000000);
 107                 of_node_put(np);
 108         }
 109
 110         mips_hpt_frequency = freq / 2;
 111 }
 112
 113 void __init arch_init_irq(void)
 114 {
 115         irqchip_init();
 116 }