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realtek: Cleanup setting inner/outer PVID and Ingress/Egres VLAN filtering
[openwrt/staging/ldir.git] / target / linux / realtek / files-5.10 / drivers / net / dsa / rtl83xx / dsa.c
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <net/dsa.h>
4 #include <linux/if_bridge.h>
5
6 #include <asm/mach-rtl838x/mach-rtl83xx.h>
7 #include "rtl83xx.h"
8
9
10 extern struct rtl83xx_soc_info soc_info;
11
12
13 static void rtl83xx_init_stats(struct rtl838x_switch_priv *priv)
14 {
15 mutex_lock(&priv->reg_mutex);
16
17 /* Enable statistics module: all counters plus debug.
18 * On RTL839x all counters are enabled by default
19 */
20 if (priv->family_id == RTL8380_FAMILY_ID)
21 sw_w32_mask(0, 3, RTL838X_STAT_CTRL);
22
23 /* Reset statistics counters */
24 sw_w32_mask(0, 1, priv->r->stat_rst);
25
26 mutex_unlock(&priv->reg_mutex);
27 }
28
29 static void rtl83xx_enable_phy_polling(struct rtl838x_switch_priv *priv)
30 {
31 int i;
32 u64 v = 0;
33
34 msleep(1000);
35 /* Enable all ports with a PHY, including the SFP-ports */
36 for (i = 0; i < priv->cpu_port; i++) {
37 if (priv->ports[i].phy)
38 v |= BIT_ULL(i);
39 }
40
41 pr_info("%s: %16llx\n", __func__, v);
42 priv->r->set_port_reg_le(v, priv->r->smi_poll_ctrl);
43
44 /* PHY update complete, there is no global PHY polling enable bit on the 9300 */
45 if (priv->family_id == RTL8390_FAMILY_ID)
46 sw_w32_mask(0, BIT(7), RTL839X_SMI_GLB_CTRL);
47 else if(priv->family_id == RTL9300_FAMILY_ID)
48 sw_w32_mask(0, 0x8000, RTL838X_SMI_GLB_CTRL);
49 }
50
51 const struct rtl83xx_mib_desc rtl83xx_mib[] = {
52 MIB_DESC(2, 0xf8, "ifInOctets"),
53 MIB_DESC(2, 0xf0, "ifOutOctets"),
54 MIB_DESC(1, 0xec, "dot1dTpPortInDiscards"),
55 MIB_DESC(1, 0xe8, "ifInUcastPkts"),
56 MIB_DESC(1, 0xe4, "ifInMulticastPkts"),
57 MIB_DESC(1, 0xe0, "ifInBroadcastPkts"),
58 MIB_DESC(1, 0xdc, "ifOutUcastPkts"),
59 MIB_DESC(1, 0xd8, "ifOutMulticastPkts"),
60 MIB_DESC(1, 0xd4, "ifOutBroadcastPkts"),
61 MIB_DESC(1, 0xd0, "ifOutDiscards"),
62 MIB_DESC(1, 0xcc, ".3SingleCollisionFrames"),
63 MIB_DESC(1, 0xc8, ".3MultipleCollisionFrames"),
64 MIB_DESC(1, 0xc4, ".3DeferredTransmissions"),
65 MIB_DESC(1, 0xc0, ".3LateCollisions"),
66 MIB_DESC(1, 0xbc, ".3ExcessiveCollisions"),
67 MIB_DESC(1, 0xb8, ".3SymbolErrors"),
68 MIB_DESC(1, 0xb4, ".3ControlInUnknownOpcodes"),
69 MIB_DESC(1, 0xb0, ".3InPauseFrames"),
70 MIB_DESC(1, 0xac, ".3OutPauseFrames"),
71 MIB_DESC(1, 0xa8, "DropEvents"),
72 MIB_DESC(1, 0xa4, "tx_BroadcastPkts"),
73 MIB_DESC(1, 0xa0, "tx_MulticastPkts"),
74 MIB_DESC(1, 0x9c, "CRCAlignErrors"),
75 MIB_DESC(1, 0x98, "tx_UndersizePkts"),
76 MIB_DESC(1, 0x94, "rx_UndersizePkts"),
77 MIB_DESC(1, 0x90, "rx_UndersizedropPkts"),
78 MIB_DESC(1, 0x8c, "tx_OversizePkts"),
79 MIB_DESC(1, 0x88, "rx_OversizePkts"),
80 MIB_DESC(1, 0x84, "Fragments"),
81 MIB_DESC(1, 0x80, "Jabbers"),
82 MIB_DESC(1, 0x7c, "Collisions"),
83 MIB_DESC(1, 0x78, "tx_Pkts64Octets"),
84 MIB_DESC(1, 0x74, "rx_Pkts64Octets"),
85 MIB_DESC(1, 0x70, "tx_Pkts65to127Octets"),
86 MIB_DESC(1, 0x6c, "rx_Pkts65to127Octets"),
87 MIB_DESC(1, 0x68, "tx_Pkts128to255Octets"),
88 MIB_DESC(1, 0x64, "rx_Pkts128to255Octets"),
89 MIB_DESC(1, 0x60, "tx_Pkts256to511Octets"),
90 MIB_DESC(1, 0x5c, "rx_Pkts256to511Octets"),
91 MIB_DESC(1, 0x58, "tx_Pkts512to1023Octets"),
92 MIB_DESC(1, 0x54, "rx_Pkts512to1023Octets"),
93 MIB_DESC(1, 0x50, "tx_Pkts1024to1518Octets"),
94 MIB_DESC(1, 0x4c, "rx_StatsPkts1024to1518Octets"),
95 MIB_DESC(1, 0x48, "tx_Pkts1519toMaxOctets"),
96 MIB_DESC(1, 0x44, "rx_Pkts1519toMaxOctets"),
97 MIB_DESC(1, 0x40, "rxMacDiscards")
98 };
99
100
101 /* DSA callbacks */
102
103
104 static enum dsa_tag_protocol rtl83xx_get_tag_protocol(struct dsa_switch *ds,
105 int port,
106 enum dsa_tag_protocol mprot)
107 {
108 /* The switch does not tag the frames, instead internally the header
109 * structure for each packet is tagged accordingly.
110 */
111 return DSA_TAG_PROTO_TRAILER;
112 }
113
114 /*
115 * Initialize all VLANS
116 */
117 static void rtl83xx_vlan_setup(struct rtl838x_switch_priv *priv)
118 {
119 struct rtl838x_vlan_info info;
120 int i;
121
122 pr_info("In %s\n", __func__);
123
124 priv->r->vlan_profile_setup(0);
125 priv->r->vlan_profile_setup(1);
126 pr_info("UNKNOWN_MC_PMASK: %016llx\n", priv->r->read_mcast_pmask(UNKNOWN_MC_PMASK));
127 priv->r->vlan_profile_dump(0);
128
129 info.fid = 0; // Default Forwarding ID / MSTI
130 info.hash_uc_fid = false; // Do not build the L2 lookup hash with FID, but VID
131 info.hash_mc_fid = false; // Do the same for Multicast packets
132 info.profile_id = 0; // Use default Vlan Profile 0
133 info.tagged_ports = 0; // Initially no port members
134 if (priv->family_id == RTL9310_FAMILY_ID) {
135 info.if_id = 0;
136 info.multicast_grp_mask = 0;
137 info.l2_tunnel_list_id = -1;
138 }
139
140 // Initialize all vlans 0-4095
141 for (i = 0; i < MAX_VLANS; i ++)
142 priv->r->vlan_set_tagged(i, &info);
143
144 // reset PVIDs; defaults to 1 on reset
145 for (i = 0; i <= priv->ds->num_ports; i++) {
146 priv->r->vlan_port_pvid_set(i, PBVLAN_TYPE_INNER, 0);
147 priv->r->vlan_port_pvid_set(i, PBVLAN_TYPE_OUTER, 0);
148 priv->r->vlan_port_pvidmode_set(i, PBVLAN_TYPE_INNER, PBVLAN_MODE_UNTAG_AND_PRITAG);
149 priv->r->vlan_port_pvidmode_set(i, PBVLAN_TYPE_OUTER, PBVLAN_MODE_UNTAG_AND_PRITAG);
150 }
151
152 // Set forwarding action based on inner VLAN tag
153 for (i = 0; i < priv->cpu_port; i++)
154 priv->r->vlan_fwd_on_inner(i, true);
155 }
156
157 static int rtl83xx_setup(struct dsa_switch *ds)
158 {
159 int i;
160 struct rtl838x_switch_priv *priv = ds->priv;
161 u64 port_bitmap = BIT_ULL(priv->cpu_port);
162
163 pr_debug("%s called\n", __func__);
164
165 /* Disable MAC polling the PHY so that we can start configuration */
166 priv->r->set_port_reg_le(0ULL, priv->r->smi_poll_ctrl);
167
168 for (i = 0; i < ds->num_ports; i++)
169 priv->ports[i].enable = false;
170 priv->ports[priv->cpu_port].enable = true;
171
172 /* Isolate ports from each other: traffic only CPU <-> port */
173 /* Setting bit j in register RTL838X_PORT_ISO_CTRL(i) allows
174 * traffic from source port i to destination port j
175 */
176 for (i = 0; i < priv->cpu_port; i++) {
177 if (priv->ports[i].phy) {
178 priv->r->set_port_reg_be(BIT_ULL(priv->cpu_port) | BIT_ULL(i),
179 priv->r->port_iso_ctrl(i));
180 port_bitmap |= BIT_ULL(i);
181 }
182 }
183 priv->r->set_port_reg_be(port_bitmap, priv->r->port_iso_ctrl(priv->cpu_port));
184
185 if (priv->family_id == RTL8380_FAMILY_ID)
186 rtl838x_print_matrix();
187 else
188 rtl839x_print_matrix();
189
190 rtl83xx_init_stats(priv);
191
192 rtl83xx_vlan_setup(priv);
193
194 ds->configure_vlan_while_not_filtering = true;
195
196 priv->r->l2_learning_setup();
197
198 /* Enable MAC Polling PHY again */
199 rtl83xx_enable_phy_polling(priv);
200 pr_debug("Please wait until PHY is settled\n");
201 msleep(1000);
202 priv->r->pie_init(priv);
203
204 return 0;
205 }
206
207 static int rtl93xx_setup(struct dsa_switch *ds)
208 {
209 int i;
210 struct rtl838x_switch_priv *priv = ds->priv;
211 u32 port_bitmap = BIT(priv->cpu_port);
212
213 pr_info("%s called\n", __func__);
214
215 /* Disable MAC polling the PHY so that we can start configuration */
216 if (priv->family_id == RTL9300_FAMILY_ID)
217 sw_w32(0, RTL930X_SMI_POLL_CTRL);
218
219 if (priv->family_id == RTL9310_FAMILY_ID) {
220 sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL);
221 sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL + 4);
222 }
223
224 // Disable all ports except CPU port
225 for (i = 0; i < ds->num_ports; i++)
226 priv->ports[i].enable = false;
227 priv->ports[priv->cpu_port].enable = true;
228
229 for (i = 0; i < priv->cpu_port; i++) {
230 if (priv->ports[i].phy) {
231 priv->r->traffic_set(i, BIT_ULL(priv->cpu_port) | BIT_ULL(i));
232 port_bitmap |= BIT_ULL(i);
233 }
234 }
235 priv->r->traffic_set(priv->cpu_port, port_bitmap);
236
237 rtl930x_print_matrix();
238
239 // TODO: Initialize statistics
240
241 rtl83xx_vlan_setup(priv);
242
243 ds->configure_vlan_while_not_filtering = true;
244
245 priv->r->l2_learning_setup();
246
247 rtl83xx_enable_phy_polling(priv);
248
249 priv->r->pie_init(priv);
250
251 return 0;
252 }
253
254 static int rtl93xx_get_sds(struct phy_device *phydev)
255 {
256 struct device *dev = &phydev->mdio.dev;
257 struct device_node *dn;
258 u32 sds_num;
259
260 if (!dev)
261 return -1;
262 if (dev->of_node) {
263 dn = dev->of_node;
264 if (of_property_read_u32(dn, "sds", &sds_num))
265 sds_num = -1;
266 } else {
267 dev_err(dev, "No DT node.\n");
268 return -1;
269 }
270
271 return sds_num;
272 }
273
274 static void rtl83xx_phylink_validate(struct dsa_switch *ds, int port,
275 unsigned long *supported,
276 struct phylink_link_state *state)
277 {
278 struct rtl838x_switch_priv *priv = ds->priv;
279 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
280
281 pr_debug("In %s port %d, state is %d", __func__, port, state->interface);
282
283 if (!phy_interface_mode_is_rgmii(state->interface) &&
284 state->interface != PHY_INTERFACE_MODE_NA &&
285 state->interface != PHY_INTERFACE_MODE_1000BASEX &&
286 state->interface != PHY_INTERFACE_MODE_MII &&
287 state->interface != PHY_INTERFACE_MODE_REVMII &&
288 state->interface != PHY_INTERFACE_MODE_GMII &&
289 state->interface != PHY_INTERFACE_MODE_QSGMII &&
290 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
291 state->interface != PHY_INTERFACE_MODE_SGMII) {
292 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
293 dev_err(ds->dev,
294 "Unsupported interface: %d for port %d\n",
295 state->interface, port);
296 return;
297 }
298
299 /* Allow all the expected bits */
300 phylink_set(mask, Autoneg);
301 phylink_set_port_modes(mask);
302 phylink_set(mask, Pause);
303 phylink_set(mask, Asym_Pause);
304
305 /* With the exclusion of MII and Reverse MII, we support Gigabit,
306 * including Half duplex
307 */
308 if (state->interface != PHY_INTERFACE_MODE_MII &&
309 state->interface != PHY_INTERFACE_MODE_REVMII) {
310 phylink_set(mask, 1000baseT_Full);
311 phylink_set(mask, 1000baseT_Half);
312 }
313
314 /* On both the 8380 and 8382, ports 24-27 are SFP ports */
315 if (port >= 24 && port <= 27 && priv->family_id == RTL8380_FAMILY_ID)
316 phylink_set(mask, 1000baseX_Full);
317
318 /* On the RTL839x family of SoCs, ports 48 to 51 are SFP ports */
319 if (port >= 48 && port <= 51 && priv->family_id == RTL8390_FAMILY_ID)
320 phylink_set(mask, 1000baseX_Full);
321
322 phylink_set(mask, 10baseT_Half);
323 phylink_set(mask, 10baseT_Full);
324 phylink_set(mask, 100baseT_Half);
325 phylink_set(mask, 100baseT_Full);
326
327 bitmap_and(supported, supported, mask,
328 __ETHTOOL_LINK_MODE_MASK_NBITS);
329 bitmap_and(state->advertising, state->advertising, mask,
330 __ETHTOOL_LINK_MODE_MASK_NBITS);
331 }
332
333 static void rtl93xx_phylink_validate(struct dsa_switch *ds, int port,
334 unsigned long *supported,
335 struct phylink_link_state *state)
336 {
337 struct rtl838x_switch_priv *priv = ds->priv;
338 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
339
340 pr_debug("In %s port %d, state is %d (%s)", __func__, port, state->interface,
341 phy_modes(state->interface));
342
343 if (!phy_interface_mode_is_rgmii(state->interface) &&
344 state->interface != PHY_INTERFACE_MODE_NA &&
345 state->interface != PHY_INTERFACE_MODE_1000BASEX &&
346 state->interface != PHY_INTERFACE_MODE_MII &&
347 state->interface != PHY_INTERFACE_MODE_REVMII &&
348 state->interface != PHY_INTERFACE_MODE_GMII &&
349 state->interface != PHY_INTERFACE_MODE_QSGMII &&
350 state->interface != PHY_INTERFACE_MODE_XGMII &&
351 state->interface != PHY_INTERFACE_MODE_HSGMII &&
352 state->interface != PHY_INTERFACE_MODE_10GBASER &&
353 state->interface != PHY_INTERFACE_MODE_10GKR &&
354 state->interface != PHY_INTERFACE_MODE_USXGMII &&
355 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
356 state->interface != PHY_INTERFACE_MODE_SGMII) {
357 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
358 dev_err(ds->dev,
359 "Unsupported interface: %d for port %d\n",
360 state->interface, port);
361 return;
362 }
363
364 /* Allow all the expected bits */
365 phylink_set(mask, Autoneg);
366 phylink_set_port_modes(mask);
367 phylink_set(mask, Pause);
368 phylink_set(mask, Asym_Pause);
369
370 /* With the exclusion of MII and Reverse MII, we support Gigabit,
371 * including Half duplex
372 */
373 if (state->interface != PHY_INTERFACE_MODE_MII &&
374 state->interface != PHY_INTERFACE_MODE_REVMII) {
375 phylink_set(mask, 1000baseT_Full);
376 phylink_set(mask, 1000baseT_Half);
377 }
378
379 // Internal phys of the RTL93xx family provide 10G
380 if (priv->ports[port].phy_is_integrated
381 && state->interface == PHY_INTERFACE_MODE_1000BASEX) {
382 phylink_set(mask, 1000baseX_Full);
383 } else if (priv->ports[port].phy_is_integrated) {
384 phylink_set(mask, 1000baseX_Full);
385 phylink_set(mask, 10000baseKR_Full);
386 phylink_set(mask, 10000baseSR_Full);
387 phylink_set(mask, 10000baseCR_Full);
388 }
389 if (state->interface == PHY_INTERFACE_MODE_INTERNAL) {
390 phylink_set(mask, 1000baseX_Full);
391 phylink_set(mask, 1000baseT_Full);
392 phylink_set(mask, 10000baseKR_Full);
393 phylink_set(mask, 10000baseT_Full);
394 phylink_set(mask, 10000baseSR_Full);
395 phylink_set(mask, 10000baseCR_Full);
396 }
397
398 if (state->interface == PHY_INTERFACE_MODE_USXGMII)
399 phylink_set(mask, 10000baseT_Full);
400
401 phylink_set(mask, 10baseT_Half);
402 phylink_set(mask, 10baseT_Full);
403 phylink_set(mask, 100baseT_Half);
404 phylink_set(mask, 100baseT_Full);
405
406 bitmap_and(supported, supported, mask,
407 __ETHTOOL_LINK_MODE_MASK_NBITS);
408 bitmap_and(state->advertising, state->advertising, mask,
409 __ETHTOOL_LINK_MODE_MASK_NBITS);
410 pr_debug("%s leaving supported: %*pb", __func__, __ETHTOOL_LINK_MODE_MASK_NBITS, supported);
411 }
412
413 static int rtl83xx_phylink_mac_link_state(struct dsa_switch *ds, int port,
414 struct phylink_link_state *state)
415 {
416 struct rtl838x_switch_priv *priv = ds->priv;
417 u64 speed;
418 u64 link;
419
420 if (port < 0 || port > priv->cpu_port)
421 return -EINVAL;
422
423 state->link = 0;
424 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
425 if (link & BIT_ULL(port))
426 state->link = 1;
427 pr_debug("%s: link state port %d: %llx\n", __func__, port, link & BIT_ULL(port));
428
429 state->duplex = 0;
430 if (priv->r->get_port_reg_le(priv->r->mac_link_dup_sts) & BIT_ULL(port))
431 state->duplex = 1;
432
433 speed = priv->r->get_port_reg_le(priv->r->mac_link_spd_sts(port));
434 speed >>= (port % 16) << 1;
435 switch (speed & 0x3) {
436 case 0:
437 state->speed = SPEED_10;
438 break;
439 case 1:
440 state->speed = SPEED_100;
441 break;
442 case 2:
443 state->speed = SPEED_1000;
444 break;
445 case 3:
446 if (priv->family_id == RTL9300_FAMILY_ID
447 && (port == 24 || port == 26)) /* Internal serdes */
448 state->speed = SPEED_2500;
449 else
450 state->speed = SPEED_100; /* Is in fact 500Mbit */
451 }
452
453 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
454 if (priv->r->get_port_reg_le(priv->r->mac_rx_pause_sts) & BIT_ULL(port))
455 state->pause |= MLO_PAUSE_RX;
456 if (priv->r->get_port_reg_le(priv->r->mac_tx_pause_sts) & BIT_ULL(port))
457 state->pause |= MLO_PAUSE_TX;
458 return 1;
459 }
460
461 static int rtl93xx_phylink_mac_link_state(struct dsa_switch *ds, int port,
462 struct phylink_link_state *state)
463 {
464 struct rtl838x_switch_priv *priv = ds->priv;
465 u64 speed;
466 u64 link;
467
468 if (port < 0 || port > priv->cpu_port)
469 return -EINVAL;
470
471 /*
472 * On the RTL9300 for at least the RTL8226B PHY, the MAC-side link
473 * state needs to be read twice in order to read a correct result.
474 * This would not be necessary for ports connected e.g. to RTL8218D
475 * PHYs.
476 */
477 state->link = 0;
478 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
479 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
480 if (link & BIT_ULL(port))
481 state->link = 1;
482 pr_debug("%s: link state port %d: %llx, media %08x\n", __func__, port,
483 link & BIT_ULL(port), sw_r32(RTL930X_MAC_LINK_MEDIA_STS));
484
485 state->duplex = 0;
486 if (priv->r->get_port_reg_le(priv->r->mac_link_dup_sts) & BIT_ULL(port))
487 state->duplex = 1;
488
489 speed = priv->r->get_port_reg_le(priv->r->mac_link_spd_sts(port));
490 speed >>= (port % 8) << 2;
491 switch (speed & 0xf) {
492 case 0:
493 state->speed = SPEED_10;
494 break;
495 case 1:
496 state->speed = SPEED_100;
497 break;
498 case 2:
499 case 7:
500 state->speed = SPEED_1000;
501 break;
502 case 4:
503 state->speed = SPEED_10000;
504 break;
505 case 5:
506 case 8:
507 state->speed = SPEED_2500;
508 break;
509 case 6:
510 state->speed = SPEED_5000;
511 break;
512 default:
513 pr_err("%s: unknown speed: %d\n", __func__, (u32)speed & 0xf);
514 }
515
516 if (priv->family_id == RTL9310_FAMILY_ID
517 && (port >= 52 || port <= 55)) { /* Internal serdes */
518 state->speed = SPEED_10000;
519 state->link = 1;
520 state->duplex = 1;
521 }
522
523 pr_debug("%s: speed is: %d %d\n", __func__, (u32)speed & 0xf, state->speed);
524 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
525 if (priv->r->get_port_reg_le(priv->r->mac_rx_pause_sts) & BIT_ULL(port))
526 state->pause |= MLO_PAUSE_RX;
527 if (priv->r->get_port_reg_le(priv->r->mac_tx_pause_sts) & BIT_ULL(port))
528 state->pause |= MLO_PAUSE_TX;
529 return 1;
530 }
531
532 static void rtl83xx_config_interface(int port, phy_interface_t interface)
533 {
534 u32 old, int_shift, sds_shift;
535
536 switch (port) {
537 case 24:
538 int_shift = 0;
539 sds_shift = 5;
540 break;
541 case 26:
542 int_shift = 3;
543 sds_shift = 0;
544 break;
545 default:
546 return;
547 }
548
549 old = sw_r32(RTL838X_SDS_MODE_SEL);
550 switch (interface) {
551 case PHY_INTERFACE_MODE_1000BASEX:
552 if ((old >> sds_shift & 0x1f) == 4)
553 return;
554 sw_w32_mask(0x7 << int_shift, 1 << int_shift, RTL838X_INT_MODE_CTRL);
555 sw_w32_mask(0x1f << sds_shift, 4 << sds_shift, RTL838X_SDS_MODE_SEL);
556 break;
557 case PHY_INTERFACE_MODE_SGMII:
558 if ((old >> sds_shift & 0x1f) == 2)
559 return;
560 sw_w32_mask(0x7 << int_shift, 2 << int_shift, RTL838X_INT_MODE_CTRL);
561 sw_w32_mask(0x1f << sds_shift, 2 << sds_shift, RTL838X_SDS_MODE_SEL);
562 break;
563 default:
564 return;
565 }
566 pr_debug("configured port %d for interface %s\n", port, phy_modes(interface));
567 }
568
569 static void rtl83xx_phylink_mac_config(struct dsa_switch *ds, int port,
570 unsigned int mode,
571 const struct phylink_link_state *state)
572 {
573 struct rtl838x_switch_priv *priv = ds->priv;
574 u32 reg;
575 int speed_bit = priv->family_id == RTL8380_FAMILY_ID ? 4 : 3;
576
577 pr_debug("%s port %d, mode %x\n", __func__, port, mode);
578
579 if (port == priv->cpu_port) {
580 /* Set Speed, duplex, flow control
581 * FORCE_EN | LINK_EN | NWAY_EN | DUP_SEL
582 * | SPD_SEL = 0b10 | FORCE_FC_EN | PHY_MASTER_SLV_MANUAL_EN
583 * | MEDIA_SEL
584 */
585 if (priv->family_id == RTL8380_FAMILY_ID) {
586 sw_w32(0x6192F, priv->r->mac_force_mode_ctrl(priv->cpu_port));
587 /* allow CRC errors on CPU-port */
588 sw_w32_mask(0, 0x8, RTL838X_MAC_PORT_CTRL(priv->cpu_port));
589 } else {
590 sw_w32_mask(0, 3, priv->r->mac_force_mode_ctrl(priv->cpu_port));
591 }
592 return;
593 }
594
595 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
596 /* Auto-Negotiation does not work for MAC in RTL8390 */
597 if (priv->family_id == RTL8380_FAMILY_ID) {
598 if (mode == MLO_AN_PHY || phylink_autoneg_inband(mode)) {
599 pr_debug("PHY autonegotiates\n");
600 reg |= RTL838X_NWAY_EN;
601 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
602 rtl83xx_config_interface(port, state->interface);
603 return;
604 }
605 }
606
607 if (mode != MLO_AN_FIXED)
608 pr_debug("Fixed state.\n");
609
610 /* Clear id_mode_dis bit, and the existing port mode, let
611 * RGMII_MODE_EN bet set by mac_link_{up,down} */
612 if (priv->family_id == RTL8380_FAMILY_ID) {
613 reg &= ~(RTL838X_RX_PAUSE_EN | RTL838X_TX_PAUSE_EN);
614 if (state->pause & MLO_PAUSE_TXRX_MASK) {
615 if (state->pause & MLO_PAUSE_TX)
616 reg |= RTL838X_TX_PAUSE_EN;
617 reg |= RTL838X_RX_PAUSE_EN;
618 }
619 } else if (priv->family_id == RTL8390_FAMILY_ID) {
620 reg &= ~(RTL839X_RX_PAUSE_EN | RTL839X_TX_PAUSE_EN);
621 if (state->pause & MLO_PAUSE_TXRX_MASK) {
622 if (state->pause & MLO_PAUSE_TX)
623 reg |= RTL839X_TX_PAUSE_EN;
624 reg |= RTL839X_RX_PAUSE_EN;
625 }
626 }
627
628
629 reg &= ~(3 << speed_bit);
630 switch (state->speed) {
631 case SPEED_1000:
632 reg |= 2 << speed_bit;
633 break;
634 case SPEED_100:
635 reg |= 1 << speed_bit;
636 break;
637 default:
638 break; // Ignore, including 10MBit which has a speed value of 0
639 }
640
641 if (priv->family_id == RTL8380_FAMILY_ID) {
642 reg &= ~(RTL838X_DUPLEX_MODE | RTL838X_FORCE_LINK_EN);
643 if (state->link)
644 reg |= RTL838X_FORCE_LINK_EN;
645 if (state->duplex == RTL838X_DUPLEX_MODE)
646 reg |= RTL838X_DUPLEX_MODE;
647 } else if (priv->family_id == RTL8390_FAMILY_ID) {
648 reg &= ~(RTL839X_DUPLEX_MODE | RTL839X_FORCE_LINK_EN);
649 if (state->link)
650 reg |= RTL839X_FORCE_LINK_EN;
651 if (state->duplex == RTL839X_DUPLEX_MODE)
652 reg |= RTL839X_DUPLEX_MODE;
653 }
654 // Disable AN
655 if (priv->family_id == RTL8380_FAMILY_ID)
656 reg &= ~RTL838X_NWAY_EN;
657 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
658 }
659
660 static void rtl931x_phylink_mac_config(struct dsa_switch *ds, int port,
661 unsigned int mode,
662 const struct phylink_link_state *state)
663 {
664 struct rtl838x_switch_priv *priv = ds->priv;
665 int sds_num;
666 u32 reg, band;
667
668 sds_num = priv->ports[port].sds_num;
669 pr_info("%s: speed %d sds_num %d\n", __func__, state->speed, sds_num);
670
671 switch (state->interface) {
672 case PHY_INTERFACE_MODE_HSGMII:
673 pr_info("%s setting mode PHY_INTERFACE_MODE_HSGMII\n", __func__);
674 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_HSGMII);
675 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_HSGMII);
676 band = rtl931x_sds_cmu_band_set(sds_num, true, 62, PHY_INTERFACE_MODE_HSGMII);
677 break;
678 case PHY_INTERFACE_MODE_1000BASEX:
679 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_1000BASEX);
680 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_1000BASEX);
681 break;
682 case PHY_INTERFACE_MODE_XGMII:
683 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_XGMII);
684 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_XGMII);
685 break;
686 case PHY_INTERFACE_MODE_10GBASER:
687 case PHY_INTERFACE_MODE_10GKR:
688 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_10GBASER);
689 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_10GBASER);
690 break;
691 case PHY_INTERFACE_MODE_USXGMII:
692 // Translates to MII_USXGMII_10GSXGMII
693 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_USXGMII);
694 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_USXGMII);
695 break;
696 case PHY_INTERFACE_MODE_SGMII:
697 pr_info("%s setting mode PHY_INTERFACE_MODE_SGMII\n", __func__);
698 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_SGMII);
699 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_SGMII);
700 band = rtl931x_sds_cmu_band_set(sds_num, true, 62, PHY_INTERFACE_MODE_SGMII);
701 break;
702 case PHY_INTERFACE_MODE_QSGMII:
703 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_QSGMII);
704 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_QSGMII);
705 break;
706 default:
707 pr_err("%s: unknown serdes mode: %s\n",
708 __func__, phy_modes(state->interface));
709 return;
710 }
711
712 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
713 pr_info("%s reading FORCE_MODE_CTRL: %08x\n", __func__, reg);
714
715 reg &= ~(RTL931X_DUPLEX_MODE | RTL931X_FORCE_EN | RTL931X_FORCE_LINK_EN);
716
717 reg &= ~(0xf << 12);
718 reg |= 0x2 << 12; // Set SMI speed to 0x2
719
720 reg |= BIT(17) | BIT(16); // Enable RX pause and TX pause
721
722 if (state->duplex == DUPLEX_FULL)
723 reg |= RTL931X_DUPLEX_MODE;
724
725 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
726
727 }
728
729 static void rtl93xx_phylink_mac_config(struct dsa_switch *ds, int port,
730 unsigned int mode,
731 const struct phylink_link_state *state)
732 {
733 struct rtl838x_switch_priv *priv = ds->priv;
734 int sds_num, sds_mode;
735 u32 reg;
736
737 pr_info("%s port %d, mode %x, phy-mode: %s, speed %d, link %d\n", __func__,
738 port, mode, phy_modes(state->interface), state->speed, state->link);
739
740 // Nothing to be done for the CPU-port
741 if (port == priv->cpu_port)
742 return;
743
744 if (priv->family_id == RTL9310_FAMILY_ID)
745 return rtl931x_phylink_mac_config(ds, port, mode, state);
746
747 sds_num = priv->ports[port].sds_num;
748 pr_info("%s SDS is %d\n", __func__, sds_num);
749 if (sds_num >= 0) {
750 switch (state->interface) {
751 case PHY_INTERFACE_MODE_HSGMII:
752 sds_mode = 0x12;
753 break;
754 case PHY_INTERFACE_MODE_1000BASEX:
755 sds_mode = 0x04;
756 break;
757 case PHY_INTERFACE_MODE_XGMII:
758 sds_mode = 0x10;
759 break;
760 case PHY_INTERFACE_MODE_10GBASER:
761 case PHY_INTERFACE_MODE_10GKR:
762 sds_mode = 0x1b; // 10G 1000X Auto
763 break;
764 case PHY_INTERFACE_MODE_USXGMII:
765 sds_mode = 0x0d;
766 break;
767 default:
768 pr_err("%s: unknown serdes mode: %s\n",
769 __func__, phy_modes(state->interface));
770 return;
771 }
772 rtl9300_sds_rst(sds_num, sds_mode);
773 }
774
775 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
776 reg &= ~(0xf << 3);
777
778 switch (state->speed) {
779 case SPEED_10000:
780 reg |= 4 << 3;
781 break;
782 case SPEED_5000:
783 reg |= 6 << 3;
784 break;
785 case SPEED_2500:
786 reg |= 5 << 3;
787 break;
788 case SPEED_1000:
789 reg |= 2 << 3;
790 break;
791 default:
792 reg |= 2 << 3;
793 break;
794 }
795
796 if (state->link)
797 reg |= RTL930X_FORCE_LINK_EN;
798
799 if (state->duplex == DUPLEX_FULL)
800 reg |= RTL930X_DUPLEX_MODE;
801
802 if (priv->ports[port].phy_is_integrated)
803 reg &= ~RTL930X_FORCE_EN; // Clear MAC_FORCE_EN to allow SDS-MAC link
804 else
805 reg |= RTL930X_FORCE_EN;
806
807 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
808 }
809
810 static void rtl83xx_phylink_mac_link_down(struct dsa_switch *ds, int port,
811 unsigned int mode,
812 phy_interface_t interface)
813 {
814 struct rtl838x_switch_priv *priv = ds->priv;
815 u32 v;
816
817 /* Stop TX/RX to port */
818 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(port));
819
820 // No longer force link
821 if (priv->family_id == RTL9300_FAMILY_ID)
822 v = RTL930X_FORCE_EN | RTL930X_FORCE_LINK_EN;
823 else if (priv->family_id == RTL9310_FAMILY_ID)
824 v = RTL931X_FORCE_EN | RTL931X_FORCE_LINK_EN;
825 sw_w32_mask(v, 0, priv->r->mac_port_ctrl(port));
826 }
827
828 static void rtl93xx_phylink_mac_link_down(struct dsa_switch *ds, int port,
829 unsigned int mode,
830 phy_interface_t interface)
831 {
832 struct rtl838x_switch_priv *priv = ds->priv;
833 /* Stop TX/RX to port */
834 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(port));
835
836 // No longer force link
837 sw_w32_mask(3, 0, priv->r->mac_force_mode_ctrl(port));
838 }
839
840 static void rtl83xx_phylink_mac_link_up(struct dsa_switch *ds, int port,
841 unsigned int mode,
842 phy_interface_t interface,
843 struct phy_device *phydev,
844 int speed, int duplex,
845 bool tx_pause, bool rx_pause)
846 {
847 struct rtl838x_switch_priv *priv = ds->priv;
848 /* Restart TX/RX to port */
849 sw_w32_mask(0, 0x3, priv->r->mac_port_ctrl(port));
850 // TODO: Set speed/duplex/pauses
851 }
852
853 static void rtl93xx_phylink_mac_link_up(struct dsa_switch *ds, int port,
854 unsigned int mode,
855 phy_interface_t interface,
856 struct phy_device *phydev,
857 int speed, int duplex,
858 bool tx_pause, bool rx_pause)
859 {
860 struct rtl838x_switch_priv *priv = ds->priv;
861
862 /* Restart TX/RX to port */
863 sw_w32_mask(0, 0x3, priv->r->mac_port_ctrl(port));
864 // TODO: Set speed/duplex/pauses
865 }
866
867 static void rtl83xx_get_strings(struct dsa_switch *ds,
868 int port, u32 stringset, u8 *data)
869 {
870 int i;
871
872 if (stringset != ETH_SS_STATS)
873 return;
874
875 for (i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++)
876 strncpy(data + i * ETH_GSTRING_LEN, rtl83xx_mib[i].name,
877 ETH_GSTRING_LEN);
878 }
879
880 static void rtl83xx_get_ethtool_stats(struct dsa_switch *ds, int port,
881 uint64_t *data)
882 {
883 struct rtl838x_switch_priv *priv = ds->priv;
884 const struct rtl83xx_mib_desc *mib;
885 int i;
886 u64 h;
887
888 for (i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++) {
889 mib = &rtl83xx_mib[i];
890
891 data[i] = sw_r32(priv->r->stat_port_std_mib + (port << 8) + 252 - mib->offset);
892 if (mib->size == 2) {
893 h = sw_r32(priv->r->stat_port_std_mib + (port << 8) + 248 - mib->offset);
894 data[i] |= h << 32;
895 }
896 }
897 }
898
899 static int rtl83xx_get_sset_count(struct dsa_switch *ds, int port, int sset)
900 {
901 if (sset != ETH_SS_STATS)
902 return 0;
903
904 return ARRAY_SIZE(rtl83xx_mib);
905 }
906
907 static int rtl83xx_port_enable(struct dsa_switch *ds, int port,
908 struct phy_device *phydev)
909 {
910 struct rtl838x_switch_priv *priv = ds->priv;
911 u64 v;
912
913 pr_debug("%s: %x %d", __func__, (u32) priv, port);
914 priv->ports[port].enable = true;
915
916 /* enable inner tagging on egress, do not keep any tags */
917 if (priv->family_id == RTL9310_FAMILY_ID)
918 sw_w32(BIT(4), priv->r->vlan_port_tag_sts_ctrl + (port << 2));
919 else
920 sw_w32(1, priv->r->vlan_port_tag_sts_ctrl + (port << 2));
921
922 if (dsa_is_cpu_port(ds, port))
923 return 0;
924
925 /* add port to switch mask of CPU_PORT */
926 priv->r->traffic_enable(priv->cpu_port, port);
927
928 /* add all other ports in the same bridge to switch mask of port */
929 v = priv->r->traffic_get(port);
930 v |= priv->ports[port].pm;
931 priv->r->traffic_set(port, v);
932
933 // TODO: Figure out if this is necessary
934 if (priv->family_id == RTL9300_FAMILY_ID) {
935 sw_w32_mask(0, BIT(port), RTL930X_L2_PORT_SABLK_CTRL);
936 sw_w32_mask(0, BIT(port), RTL930X_L2_PORT_DABLK_CTRL);
937 }
938
939 priv->ports[port].sds_num = rtl93xx_get_sds(phydev);
940
941 return 0;
942 }
943
944 static void rtl83xx_port_disable(struct dsa_switch *ds, int port)
945 {
946 struct rtl838x_switch_priv *priv = ds->priv;
947 u64 v;
948
949 pr_debug("%s %x: %d", __func__, (u32)priv, port);
950 /* you can only disable user ports */
951 if (!dsa_is_user_port(ds, port))
952 return;
953
954 // BUG: This does not work on RTL931X
955 /* remove port from switch mask of CPU_PORT */
956 priv->r->traffic_disable(priv->cpu_port, port);
957
958 /* remove all other ports in the same bridge from switch mask of port */
959 v = priv->r->traffic_get(port);
960 v &= ~priv->ports[port].pm;
961 priv->r->traffic_set(port, v);
962
963 priv->ports[port].enable = false;
964 }
965
966 static int rtl83xx_set_mac_eee(struct dsa_switch *ds, int port,
967 struct ethtool_eee *e)
968 {
969 struct rtl838x_switch_priv *priv = ds->priv;
970
971 if (e->eee_enabled && !priv->eee_enabled) {
972 pr_info("Globally enabling EEE\n");
973 priv->r->init_eee(priv, true);
974 }
975
976 priv->r->port_eee_set(priv, port, e->eee_enabled);
977
978 if (e->eee_enabled)
979 pr_info("Enabled EEE for port %d\n", port);
980 else
981 pr_info("Disabled EEE for port %d\n", port);
982 return 0;
983 }
984
985 static int rtl83xx_get_mac_eee(struct dsa_switch *ds, int port,
986 struct ethtool_eee *e)
987 {
988 struct rtl838x_switch_priv *priv = ds->priv;
989
990 e->supported = SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full;
991
992 priv->r->eee_port_ability(priv, e, port);
993
994 e->eee_enabled = priv->ports[port].eee_enabled;
995
996 e->eee_active = !!(e->advertised & e->lp_advertised);
997
998 return 0;
999 }
1000
1001 static int rtl93xx_get_mac_eee(struct dsa_switch *ds, int port,
1002 struct ethtool_eee *e)
1003 {
1004 struct rtl838x_switch_priv *priv = ds->priv;
1005
1006 e->supported = SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full
1007 | SUPPORTED_2500baseX_Full;
1008
1009 priv->r->eee_port_ability(priv, e, port);
1010
1011 e->eee_enabled = priv->ports[port].eee_enabled;
1012
1013 e->eee_active = !!(e->advertised & e->lp_advertised);
1014
1015 return 0;
1016 }
1017
1018 /*
1019 * Set Switch L2 Aging time, t is time in milliseconds
1020 * t = 0: aging is disabled
1021 */
1022 static int rtl83xx_set_l2aging(struct dsa_switch *ds, u32 t)
1023 {
1024 struct rtl838x_switch_priv *priv = ds->priv;
1025 int t_max = priv->family_id == RTL8380_FAMILY_ID ? 0x7fffff : 0x1FFFFF;
1026
1027 /* Convert time in mseconds to internal value */
1028 if (t > 0x10000000) { /* Set to maximum */
1029 t = t_max;
1030 } else {
1031 if (priv->family_id == RTL8380_FAMILY_ID)
1032 t = ((t * 625) / 1000 + 127) / 128;
1033 else
1034 t = (t * 5 + 2) / 3;
1035 }
1036 sw_w32(t, priv->r->l2_ctrl_1);
1037 return 0;
1038 }
1039
1040 static int rtl83xx_port_bridge_join(struct dsa_switch *ds, int port,
1041 struct net_device *bridge)
1042 {
1043 struct rtl838x_switch_priv *priv = ds->priv;
1044 u64 port_bitmap = BIT_ULL(priv->cpu_port), v;
1045 int i;
1046
1047 pr_debug("%s %x: %d %llx", __func__, (u32)priv, port, port_bitmap);
1048 mutex_lock(&priv->reg_mutex);
1049 for (i = 0; i < ds->num_ports; i++) {
1050 /* Add this port to the port matrix of the other ports in the
1051 * same bridge. If the port is disabled, port matrix is kept
1052 * and not being setup until the port becomes enabled.
1053 */
1054 if (dsa_is_user_port(ds, i) && i != port) {
1055 if (dsa_to_port(ds, i)->bridge_dev != bridge)
1056 continue;
1057 if (priv->ports[i].enable)
1058 priv->r->traffic_enable(i, port);
1059
1060 priv->ports[i].pm |= BIT_ULL(port);
1061 port_bitmap |= BIT_ULL(i);
1062 }
1063 }
1064
1065 /* Add all other ports to this port matrix. */
1066 if (priv->ports[port].enable) {
1067 priv->r->traffic_enable(priv->cpu_port, port);
1068 v = priv->r->traffic_get(port);
1069 v |= port_bitmap;
1070 priv->r->traffic_set(port, v);
1071 }
1072 priv->ports[port].pm |= port_bitmap;
1073 mutex_unlock(&priv->reg_mutex);
1074
1075 return 0;
1076 }
1077
1078 static void rtl83xx_port_bridge_leave(struct dsa_switch *ds, int port,
1079 struct net_device *bridge)
1080 {
1081 struct rtl838x_switch_priv *priv = ds->priv;
1082 u64 port_bitmap = BIT_ULL(priv->cpu_port), v;
1083 int i;
1084
1085 pr_debug("%s %x: %d", __func__, (u32)priv, port);
1086 mutex_lock(&priv->reg_mutex);
1087 for (i = 0; i < ds->num_ports; i++) {
1088 /* Remove this port from the port matrix of the other ports
1089 * in the same bridge. If the port is disabled, port matrix
1090 * is kept and not being setup until the port becomes enabled.
1091 * And the other port's port matrix cannot be broken when the
1092 * other port is still a VLAN-aware port.
1093 */
1094 if (dsa_is_user_port(ds, i) && i != port) {
1095 if (dsa_to_port(ds, i)->bridge_dev != bridge)
1096 continue;
1097 if (priv->ports[i].enable)
1098 priv->r->traffic_disable(i, port);
1099
1100 priv->ports[i].pm |= BIT_ULL(port);
1101 port_bitmap &= ~BIT_ULL(i);
1102 }
1103 }
1104
1105 /* Add all other ports to this port matrix. */
1106 if (priv->ports[port].enable) {
1107 v = priv->r->traffic_get(port);
1108 v |= port_bitmap;
1109 priv->r->traffic_set(port, v);
1110 }
1111 priv->ports[port].pm &= ~port_bitmap;
1112
1113 mutex_unlock(&priv->reg_mutex);
1114 }
1115
1116 void rtl83xx_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1117 {
1118 u32 msti = 0;
1119 u32 port_state[4];
1120 int index, bit;
1121 int pos = port;
1122 struct rtl838x_switch_priv *priv = ds->priv;
1123 int n = priv->port_width << 1;
1124
1125 /* Ports above or equal CPU port can never be configured */
1126 if (port >= priv->cpu_port)
1127 return;
1128
1129 mutex_lock(&priv->reg_mutex);
1130
1131 /* For the RTL839x and following, the bits are left-aligned, 838x and 930x
1132 * have 64 bit fields, 839x and 931x have 128 bit fields
1133 */
1134 if (priv->family_id == RTL8390_FAMILY_ID)
1135 pos += 12;
1136 if (priv->family_id == RTL9300_FAMILY_ID)
1137 pos += 3;
1138 if (priv->family_id == RTL9310_FAMILY_ID)
1139 pos += 8;
1140
1141 index = n - (pos >> 4) - 1;
1142 bit = (pos << 1) % 32;
1143
1144 priv->r->stp_get(priv, msti, port_state);
1145
1146 pr_debug("Current state, port %d: %d\n", port, (port_state[index] >> bit) & 3);
1147 port_state[index] &= ~(3 << bit);
1148
1149 switch (state) {
1150 case BR_STATE_DISABLED: /* 0 */
1151 port_state[index] |= (0 << bit);
1152 break;
1153 case BR_STATE_BLOCKING: /* 4 */
1154 case BR_STATE_LISTENING: /* 1 */
1155 port_state[index] |= (1 << bit);
1156 break;
1157 case BR_STATE_LEARNING: /* 2 */
1158 port_state[index] |= (2 << bit);
1159 break;
1160 case BR_STATE_FORWARDING: /* 3*/
1161 port_state[index] |= (3 << bit);
1162 default:
1163 break;
1164 }
1165
1166 priv->r->stp_set(priv, msti, port_state);
1167
1168 mutex_unlock(&priv->reg_mutex);
1169 }
1170
1171 void rtl83xx_fast_age(struct dsa_switch *ds, int port)
1172 {
1173 struct rtl838x_switch_priv *priv = ds->priv;
1174 int s = priv->family_id == RTL8390_FAMILY_ID ? 2 : 0;
1175
1176 pr_debug("FAST AGE port %d\n", port);
1177 mutex_lock(&priv->reg_mutex);
1178 /* RTL838X_L2_TBL_FLUSH_CTRL register bits, 839x has 1 bit larger
1179 * port fields:
1180 * 0-4: Replacing port
1181 * 5-9: Flushed/replaced port
1182 * 10-21: FVID
1183 * 22: Entry types: 1: dynamic, 0: also static
1184 * 23: Match flush port
1185 * 24: Match FVID
1186 * 25: Flush (0) or replace (1) L2 entries
1187 * 26: Status of action (1: Start, 0: Done)
1188 */
1189 sw_w32(1 << (26 + s) | 1 << (23 + s) | port << (5 + (s / 2)), priv->r->l2_tbl_flush_ctrl);
1190
1191 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(26 + s));
1192
1193 mutex_unlock(&priv->reg_mutex);
1194 }
1195
1196 void rtl930x_fast_age(struct dsa_switch *ds, int port)
1197 {
1198 struct rtl838x_switch_priv *priv = ds->priv;
1199
1200 pr_debug("FAST AGE port %d\n", port);
1201 mutex_lock(&priv->reg_mutex);
1202 sw_w32(port << 11, RTL930X_L2_TBL_FLUSH_CTRL + 4);
1203
1204 sw_w32(BIT(26) | BIT(30), RTL930X_L2_TBL_FLUSH_CTRL);
1205
1206 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(30));
1207
1208 mutex_unlock(&priv->reg_mutex);
1209 }
1210
1211 static int rtl83xx_vlan_filtering(struct dsa_switch *ds, int port,
1212 bool vlan_filtering,
1213 struct switchdev_trans *trans)
1214 {
1215 struct rtl838x_switch_priv *priv = ds->priv;
1216
1217 pr_debug("%s: port %d\n", __func__, port);
1218 mutex_lock(&priv->reg_mutex);
1219
1220 if (vlan_filtering) {
1221 /* Enable ingress and egress filtering
1222 * The VLAN_PORT_IGR_FILTER register uses 2 bits for each port to define
1223 * the filter action:
1224 * 0: Always Forward
1225 * 1: Drop packet
1226 * 2: Trap packet to CPU port
1227 * The Egress filter used 1 bit per state (0: DISABLED, 1: ENABLED)
1228 */
1229 if (port != priv->cpu_port)
1230 priv->r->set_vlan_igr_filter(port, IGR_DROP);
1231
1232 priv->r->set_vlan_egr_filter(port, EGR_ENABLE);
1233 } else {
1234 /* Disable ingress and egress filtering */
1235 if (port != priv->cpu_port)
1236 priv->r->set_vlan_igr_filter(port, IGR_FORWARD);
1237
1238 priv->r->set_vlan_egr_filter(port, EGR_DISABLE);
1239 }
1240
1241 /* Do we need to do something to the CPU-Port, too? */
1242 mutex_unlock(&priv->reg_mutex);
1243
1244 return 0;
1245 }
1246
1247 static int rtl83xx_vlan_prepare(struct dsa_switch *ds, int port,
1248 const struct switchdev_obj_port_vlan *vlan)
1249 {
1250 struct rtl838x_vlan_info info;
1251 struct rtl838x_switch_priv *priv = ds->priv;
1252
1253 priv->r->vlan_tables_read(0, &info);
1254
1255 pr_debug("VLAN 0: Tagged ports %llx, untag %llx, profile %d, MC# %d, UC# %d, FID %x\n",
1256 info.tagged_ports, info.untagged_ports, info.profile_id,
1257 info.hash_mc_fid, info.hash_uc_fid, info.fid);
1258
1259 priv->r->vlan_tables_read(1, &info);
1260 pr_debug("VLAN 1: Tagged ports %llx, untag %llx, profile %d, MC# %d, UC# %d, FID %x\n",
1261 info.tagged_ports, info.untagged_ports, info.profile_id,
1262 info.hash_mc_fid, info.hash_uc_fid, info.fid);
1263 priv->r->vlan_set_untagged(1, info.untagged_ports);
1264 pr_debug("SET: Untagged ports, VLAN %d: %llx\n", 1, info.untagged_ports);
1265
1266 priv->r->vlan_set_tagged(1, &info);
1267 pr_debug("SET: Tagged ports, VLAN %d: %llx\n", 1, info.tagged_ports);
1268
1269 mutex_unlock(&priv->reg_mutex);
1270 return 0;
1271 }
1272
1273 static void rtl83xx_vlan_add(struct dsa_switch *ds, int port,
1274 const struct switchdev_obj_port_vlan *vlan)
1275 {
1276 struct rtl838x_vlan_info info;
1277 struct rtl838x_switch_priv *priv = ds->priv;
1278 int v;
1279
1280 pr_debug("%s port %d, vid_end %d, vid_end %d, flags %x\n", __func__,
1281 port, vlan->vid_begin, vlan->vid_end, vlan->flags);
1282
1283 if (vlan->vid_begin > 4095 || vlan->vid_end > 4095) {
1284 dev_err(priv->dev, "VLAN out of range: %d - %d",
1285 vlan->vid_begin, vlan->vid_end);
1286 return;
1287 }
1288
1289 mutex_lock(&priv->reg_mutex);
1290
1291 if (vlan->flags & BRIDGE_VLAN_INFO_PVID) {
1292 for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
1293 if (!v)
1294 continue;
1295 /* Set both inner and outer PVID of the port */
1296 priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_INNER, v);
1297 priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_OUTER, v);
1298 priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_INNER,
1299 PBVLAN_MODE_UNTAG_AND_PRITAG);
1300 priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_OUTER,
1301 PBVLAN_MODE_UNTAG_AND_PRITAG);
1302
1303 priv->ports[port].pvid = vlan->vid_end;
1304 }
1305 }
1306
1307 for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
1308 /* Get port memberships of this vlan */
1309 priv->r->vlan_tables_read(v, &info);
1310
1311 /* new VLAN? */
1312 if (!info.tagged_ports) {
1313 info.fid = 0;
1314 info.hash_mc_fid = false;
1315 info.hash_uc_fid = false;
1316 info.profile_id = 0;
1317 }
1318
1319 /* sanitize untagged_ports - must be a subset */
1320 if (info.untagged_ports & ~info.tagged_ports)
1321 info.untagged_ports = 0;
1322
1323 info.tagged_ports |= BIT_ULL(port);
1324 if (vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED)
1325 info.untagged_ports |= BIT_ULL(port);
1326
1327 priv->r->vlan_set_untagged(v, info.untagged_ports);
1328 pr_debug("Untagged ports, VLAN %d: %llx\n", v, info.untagged_ports);
1329
1330 priv->r->vlan_set_tagged(v, &info);
1331 pr_debug("Tagged ports, VLAN %d: %llx\n", v, info.tagged_ports);
1332 }
1333
1334 mutex_unlock(&priv->reg_mutex);
1335 }
1336
1337 static int rtl83xx_vlan_del(struct dsa_switch *ds, int port,
1338 const struct switchdev_obj_port_vlan *vlan)
1339 {
1340 struct rtl838x_vlan_info info;
1341 struct rtl838x_switch_priv *priv = ds->priv;
1342 int v;
1343 u16 pvid;
1344
1345 pr_debug("%s: port %d, vid_end %d, vid_end %d, flags %x\n", __func__,
1346 port, vlan->vid_begin, vlan->vid_end, vlan->flags);
1347
1348 if (vlan->vid_begin > 4095 || vlan->vid_end > 4095) {
1349 dev_err(priv->dev, "VLAN out of range: %d - %d",
1350 vlan->vid_begin, vlan->vid_end);
1351 return -ENOTSUPP;
1352 }
1353
1354 mutex_lock(&priv->reg_mutex);
1355 pvid = priv->ports[port].pvid;
1356
1357 for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
1358 /* Reset to default if removing the current PVID */
1359 if (v == pvid) {
1360 priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_INNER, 0);
1361 priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_OUTER, 0);
1362 priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_INNER,
1363 PBVLAN_MODE_UNTAG_AND_PRITAG);
1364 priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_OUTER,
1365 PBVLAN_MODE_UNTAG_AND_PRITAG);
1366 }
1367 /* Get port memberships of this vlan */
1368 priv->r->vlan_tables_read(v, &info);
1369
1370 /* remove port from both tables */
1371 info.untagged_ports &= (~BIT_ULL(port));
1372 info.tagged_ports &= (~BIT_ULL(port));
1373
1374 priv->r->vlan_set_untagged(v, info.untagged_ports);
1375 pr_debug("Untagged ports, VLAN %d: %llx\n", v, info.untagged_ports);
1376
1377 priv->r->vlan_set_tagged(v, &info);
1378 pr_debug("Tagged ports, VLAN %d: %llx\n", v, info.tagged_ports);
1379 }
1380 mutex_unlock(&priv->reg_mutex);
1381
1382 return 0;
1383 }
1384
1385 static void dump_l2_entry(struct rtl838x_l2_entry *e)
1386 {
1387 pr_info("MAC: %02x:%02x:%02x:%02x:%02x:%02x vid: %d, rvid: %d, port: %d, valid: %d\n",
1388 e->mac[0], e->mac[1], e->mac[2], e->mac[3], e->mac[4], e->mac[5],
1389 e->vid, e->rvid, e->port, e->valid);
1390
1391 if (e->type != L2_MULTICAST) {
1392 pr_info("Type: %d, is_static: %d, is_ip_mc: %d, is_ipv6_mc: %d, block_da: %d\n",
1393 e->type, e->is_static, e->is_ip_mc, e->is_ipv6_mc, e->block_da);
1394 pr_info(" block_sa: %d, susp: %d, nh: %d, age: %d, is_trunk: %d, trunk: %d\n",
1395 e->block_sa, e->suspended, e->next_hop, e->age, e->is_trunk, e->trunk);
1396 }
1397 if (e->type == L2_MULTICAST)
1398 pr_info(" L2_MULTICAST mc_portmask_index: %d\n", e->mc_portmask_index);
1399 if (e->is_ip_mc || e->is_ipv6_mc)
1400 pr_info(" mc_portmask_index: %d, mc_gip: %d, mc_sip: %d\n",
1401 e->mc_portmask_index, e->mc_gip, e->mc_sip);
1402 pr_info(" stack_dev: %d\n", e->stack_dev);
1403 if (e->next_hop)
1404 pr_info(" nh_route_id: %d\n", e->nh_route_id);
1405 }
1406
1407 static void rtl83xx_setup_l2_uc_entry(struct rtl838x_l2_entry *e, int port, int vid, u64 mac)
1408 {
1409 e->is_ip_mc = e->is_ipv6_mc = false;
1410 e->valid = true;
1411 e->age = 3;
1412 e->port = port,
1413 e->vid = vid;
1414 u64_to_ether_addr(mac, e->mac);
1415 }
1416
1417 static void rtl83xx_setup_l2_mc_entry(struct rtl838x_switch_priv *priv,
1418 struct rtl838x_l2_entry *e, int vid, u64 mac, int mc_group)
1419 {
1420 e->is_ip_mc = e->is_ipv6_mc = false;
1421 e->valid = true;
1422 e->mc_portmask_index = mc_group;
1423 e->type = L2_MULTICAST;
1424 e->rvid = e->vid = vid;
1425 pr_debug("%s: vid: %d, rvid: %d\n", __func__, e->vid, e->rvid);
1426 u64_to_ether_addr(mac, e->mac);
1427 }
1428
1429 /*
1430 * Uses the seed to identify a hash bucket in the L2 using the derived hash key and then loops
1431 * over the entries in the bucket until either a matching entry is found or an empty slot
1432 * Returns the filled in rtl838x_l2_entry and the index in the bucket when an entry was found
1433 * when an empty slot was found and must exist is false, the index of the slot is returned
1434 * when no slots are available returns -1
1435 */
1436 static int rtl83xx_find_l2_hash_entry(struct rtl838x_switch_priv *priv, u64 seed,
1437 bool must_exist, struct rtl838x_l2_entry *e)
1438 {
1439 int i, idx = -1;
1440 u32 key = priv->r->l2_hash_key(priv, seed);
1441 u64 entry;
1442
1443 pr_debug("%s: using key %x, for seed %016llx\n", __func__, key, seed);
1444 // Loop over all entries in the hash-bucket and over the second block on 93xx SoCs
1445 for (i = 0; i < priv->l2_bucket_size; i++) {
1446 entry = priv->r->read_l2_entry_using_hash(key, i, e);
1447 pr_debug("valid %d, mac %016llx\n", e->valid, ether_addr_to_u64(&e->mac[0]));
1448 if (must_exist && !e->valid)
1449 continue;
1450 if (!e->valid || ((entry & 0x0fffffffffffffffULL) == seed)) {
1451 idx = i > 3 ? ((key >> 14) & 0xffff) | i >> 1 : ((key << 2) | i) & 0xffff;
1452 break;
1453 }
1454 }
1455
1456 return idx;
1457 }
1458
1459 /*
1460 * Uses the seed to identify an entry in the CAM by looping over all its entries
1461 * Returns the filled in rtl838x_l2_entry and the index in the CAM when an entry was found
1462 * when an empty slot was found the index of the slot is returned
1463 * when no slots are available returns -1
1464 */
1465 static int rtl83xx_find_l2_cam_entry(struct rtl838x_switch_priv *priv, u64 seed,
1466 bool must_exist, struct rtl838x_l2_entry *e)
1467 {
1468 int i, idx = -1;
1469 u64 entry;
1470
1471 for (i = 0; i < 64; i++) {
1472 entry = priv->r->read_cam(i, e);
1473 if (!must_exist && !e->valid) {
1474 if (idx < 0) /* First empty entry? */
1475 idx = i;
1476 break;
1477 } else if ((entry & 0x0fffffffffffffffULL) == seed) {
1478 pr_debug("Found entry in CAM\n");
1479 idx = i;
1480 break;
1481 }
1482 }
1483 return idx;
1484 }
1485
1486 static int rtl83xx_port_fdb_add(struct dsa_switch *ds, int port,
1487 const unsigned char *addr, u16 vid)
1488 {
1489 struct rtl838x_switch_priv *priv = ds->priv;
1490 u64 mac = ether_addr_to_u64(addr);
1491 struct rtl838x_l2_entry e;
1492 int err = 0, idx;
1493 u64 seed = priv->r->l2_hash_seed(mac, vid);
1494
1495 mutex_lock(&priv->reg_mutex);
1496
1497 idx = rtl83xx_find_l2_hash_entry(priv, seed, false, &e);
1498
1499 // Found an existing or empty entry
1500 if (idx >= 0) {
1501 rtl83xx_setup_l2_uc_entry(&e, port, vid, mac);
1502 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1503 goto out;
1504 }
1505
1506 // Hash buckets full, try CAM
1507 rtl83xx_find_l2_cam_entry(priv, seed, false, &e);
1508
1509 if (idx >= 0) {
1510 rtl83xx_setup_l2_uc_entry(&e, port, vid, mac);
1511 priv->r->write_cam(idx, &e);
1512 goto out;
1513 }
1514
1515 err = -ENOTSUPP;
1516 out:
1517 mutex_unlock(&priv->reg_mutex);
1518 return err;
1519 }
1520
1521 static int rtl83xx_port_fdb_del(struct dsa_switch *ds, int port,
1522 const unsigned char *addr, u16 vid)
1523 {
1524 struct rtl838x_switch_priv *priv = ds->priv;
1525 u64 mac = ether_addr_to_u64(addr);
1526 struct rtl838x_l2_entry e;
1527 int err = 0, idx;
1528 u64 seed = priv->r->l2_hash_seed(mac, vid);
1529
1530 pr_info("In %s, mac %llx, vid: %d\n", __func__, mac, vid);
1531 mutex_lock(&priv->reg_mutex);
1532
1533 idx = rtl83xx_find_l2_hash_entry(priv, seed, true, &e);
1534
1535 pr_info("Found entry index %d, key %d and bucket %d\n", idx, idx >> 2, idx & 3);
1536 if (idx >= 0) {
1537 e.valid = false;
1538 dump_l2_entry(&e);
1539 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1540 goto out;
1541 }
1542
1543 /* Check CAM for spillover from hash buckets */
1544 rtl83xx_find_l2_cam_entry(priv, seed, true, &e);
1545
1546 if (idx >= 0) {
1547 e.valid = false;
1548 priv->r->write_cam(idx, &e);
1549 goto out;
1550 }
1551 err = -ENOENT;
1552 out:
1553 mutex_unlock(&priv->reg_mutex);
1554 return err;
1555 }
1556
1557 static int rtl83xx_port_fdb_dump(struct dsa_switch *ds, int port,
1558 dsa_fdb_dump_cb_t *cb, void *data)
1559 {
1560 struct rtl838x_l2_entry e;
1561 struct rtl838x_switch_priv *priv = ds->priv;
1562 int i;
1563 u32 fid, pkey;
1564 u64 mac;
1565
1566 mutex_lock(&priv->reg_mutex);
1567
1568 for (i = 0; i < priv->fib_entries; i++) {
1569 priv->r->read_l2_entry_using_hash(i >> 2, i & 0x3, &e);
1570
1571 if (!e.valid)
1572 continue;
1573
1574 if (e.port == port || e.port == RTL930X_PORT_IGNORE) {
1575 u64 seed;
1576 u32 key;
1577
1578 fid = ((i >> 2) & 0x3ff) | (e.rvid & ~0x3ff);
1579 mac = ether_addr_to_u64(&e.mac[0]);
1580 pkey = priv->r->l2_hash_key(priv, priv->r->l2_hash_seed(mac, fid));
1581 fid = (pkey & 0x3ff) | (fid & ~0x3ff);
1582 pr_info("-> index %d, key %x, bucket %d, dmac %016llx, fid: %x rvid: %x\n",
1583 i, i >> 2, i & 0x3, mac, fid, e.rvid);
1584 dump_l2_entry(&e);
1585 seed = priv->r->l2_hash_seed(mac, e.rvid);
1586 key = priv->r->l2_hash_key(priv, seed);
1587 pr_info("seed: %016llx, key based on rvid: %08x\n", seed, key);
1588 cb(e.mac, e.vid, e.is_static, data);
1589 }
1590 if (e.type == L2_MULTICAST) {
1591 u64 portmask = priv->r->read_mcast_pmask(e.mc_portmask_index);
1592
1593 if (portmask & BIT_ULL(port)) {
1594 dump_l2_entry(&e);
1595 pr_info(" PM: %016llx\n", portmask);
1596 }
1597 }
1598 }
1599
1600 for (i = 0; i < 64; i++) {
1601 priv->r->read_cam(i, &e);
1602
1603 if (!e.valid)
1604 continue;
1605
1606 if (e.port == port)
1607 cb(e.mac, e.vid, e.is_static, data);
1608 }
1609
1610 mutex_unlock(&priv->reg_mutex);
1611 return 0;
1612 }
1613
1614 static int rtl83xx_port_mdb_prepare(struct dsa_switch *ds, int port,
1615 const struct switchdev_obj_port_mdb *mdb)
1616 {
1617 struct rtl838x_switch_priv *priv = ds->priv;
1618
1619 if (priv->id >= 0x9300)
1620 return -EOPNOTSUPP;
1621
1622 return 0;
1623 }
1624
1625 static int rtl83xx_mc_group_alloc(struct rtl838x_switch_priv *priv, int port)
1626 {
1627 int mc_group = find_first_zero_bit(priv->mc_group_bm, MAX_MC_GROUPS - 1);
1628 u64 portmask;
1629
1630 if (mc_group >= MAX_MC_GROUPS - 1)
1631 return -1;
1632
1633 pr_debug("Using MC group %d\n", mc_group);
1634 set_bit(mc_group, priv->mc_group_bm);
1635 mc_group++; // We cannot use group 0, as this is used for lookup miss flooding
1636 portmask = BIT_ULL(port);
1637 priv->r->write_mcast_pmask(mc_group, portmask);
1638
1639 return mc_group;
1640 }
1641
1642 static u64 rtl83xx_mc_group_add_port(struct rtl838x_switch_priv *priv, int mc_group, int port)
1643 {
1644 u64 portmask = priv->r->read_mcast_pmask(mc_group);
1645
1646 portmask |= BIT_ULL(port);
1647 priv->r->write_mcast_pmask(mc_group, portmask);
1648
1649 return portmask;
1650 }
1651
1652 static u64 rtl83xx_mc_group_del_port(struct rtl838x_switch_priv *priv, int mc_group, int port)
1653 {
1654 u64 portmask = priv->r->read_mcast_pmask(mc_group);
1655
1656 portmask &= ~BIT_ULL(port);
1657 priv->r->write_mcast_pmask(mc_group, portmask);
1658 if (!portmask)
1659 clear_bit(mc_group, priv->mc_group_bm);
1660
1661 return portmask;
1662 }
1663
1664 static void rtl83xx_port_mdb_add(struct dsa_switch *ds, int port,
1665 const struct switchdev_obj_port_mdb *mdb)
1666 {
1667 struct rtl838x_switch_priv *priv = ds->priv;
1668 u64 mac = ether_addr_to_u64(mdb->addr);
1669 struct rtl838x_l2_entry e;
1670 int err = 0, idx;
1671 int vid = mdb->vid;
1672 u64 seed = priv->r->l2_hash_seed(mac, vid);
1673 int mc_group;
1674
1675 pr_debug("In %s port %d, mac %llx, vid: %d\n", __func__, port, mac, vid);
1676 mutex_lock(&priv->reg_mutex);
1677
1678 idx = rtl83xx_find_l2_hash_entry(priv, seed, false, &e);
1679
1680 // Found an existing or empty entry
1681 if (idx >= 0) {
1682 if (e.valid) {
1683 pr_debug("Found an existing entry %016llx, mc_group %d\n",
1684 ether_addr_to_u64(e.mac), e.mc_portmask_index);
1685 rtl83xx_mc_group_add_port(priv, e.mc_portmask_index, port);
1686 } else {
1687 pr_debug("New entry for seed %016llx\n", seed);
1688 mc_group = rtl83xx_mc_group_alloc(priv, port);
1689 if (mc_group < 0) {
1690 err = -ENOTSUPP;
1691 goto out;
1692 }
1693 rtl83xx_setup_l2_mc_entry(priv, &e, vid, mac, mc_group);
1694 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1695 }
1696 goto out;
1697 }
1698
1699 // Hash buckets full, try CAM
1700 rtl83xx_find_l2_cam_entry(priv, seed, false, &e);
1701
1702 if (idx >= 0) {
1703 if (e.valid) {
1704 pr_debug("Found existing CAM entry %016llx, mc_group %d\n",
1705 ether_addr_to_u64(e.mac), e.mc_portmask_index);
1706 rtl83xx_mc_group_add_port(priv, e.mc_portmask_index, port);
1707 } else {
1708 pr_debug("New entry\n");
1709 mc_group = rtl83xx_mc_group_alloc(priv, port);
1710 if (mc_group < 0) {
1711 err = -ENOTSUPP;
1712 goto out;
1713 }
1714 rtl83xx_setup_l2_mc_entry(priv, &e, vid, mac, mc_group);
1715 priv->r->write_cam(idx, &e);
1716 }
1717 goto out;
1718 }
1719
1720 err = -ENOTSUPP;
1721 out:
1722 mutex_unlock(&priv->reg_mutex);
1723 if (err)
1724 dev_err(ds->dev, "failed to add MDB entry\n");
1725 }
1726
1727 int rtl83xx_port_mdb_del(struct dsa_switch *ds, int port,
1728 const struct switchdev_obj_port_mdb *mdb)
1729 {
1730 struct rtl838x_switch_priv *priv = ds->priv;
1731 u64 mac = ether_addr_to_u64(mdb->addr);
1732 struct rtl838x_l2_entry e;
1733 int err = 0, idx;
1734 int vid = mdb->vid;
1735 u64 seed = priv->r->l2_hash_seed(mac, vid);
1736 u64 portmask;
1737
1738 pr_debug("In %s, port %d, mac %llx, vid: %d\n", __func__, port, mac, vid);
1739 mutex_lock(&priv->reg_mutex);
1740
1741 idx = rtl83xx_find_l2_hash_entry(priv, seed, true, &e);
1742
1743 pr_debug("Found entry index %d, key %d and bucket %d\n", idx, idx >> 2, idx & 3);
1744 if (idx >= 0) {
1745 portmask = rtl83xx_mc_group_del_port(priv, e.mc_portmask_index, port);
1746 if (!portmask) {
1747 e.valid = false;
1748 // dump_l2_entry(&e);
1749 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1750 }
1751 goto out;
1752 }
1753
1754 /* Check CAM for spillover from hash buckets */
1755 rtl83xx_find_l2_cam_entry(priv, seed, true, &e);
1756
1757 if (idx >= 0) {
1758 portmask = rtl83xx_mc_group_del_port(priv, e.mc_portmask_index, port);
1759 if (!portmask) {
1760 e.valid = false;
1761 // dump_l2_entry(&e);
1762 priv->r->write_cam(idx, &e);
1763 }
1764 goto out;
1765 }
1766 // TODO: Re-enable with a newer kernel: err = -ENOENT;
1767 out:
1768 mutex_unlock(&priv->reg_mutex);
1769 return err;
1770 }
1771
1772 static int rtl83xx_port_mirror_add(struct dsa_switch *ds, int port,
1773 struct dsa_mall_mirror_tc_entry *mirror,
1774 bool ingress)
1775 {
1776 /* We support 4 mirror groups, one destination port per group */
1777 int group;
1778 struct rtl838x_switch_priv *priv = ds->priv;
1779 int ctrl_reg, dpm_reg, spm_reg;
1780
1781 pr_debug("In %s\n", __func__);
1782
1783 for (group = 0; group < 4; group++) {
1784 if (priv->mirror_group_ports[group] == mirror->to_local_port)
1785 break;
1786 }
1787 if (group >= 4) {
1788 for (group = 0; group < 4; group++) {
1789 if (priv->mirror_group_ports[group] < 0)
1790 break;
1791 }
1792 }
1793
1794 if (group >= 4)
1795 return -ENOSPC;
1796
1797 ctrl_reg = priv->r->mir_ctrl + group * 4;
1798 dpm_reg = priv->r->mir_dpm + group * 4 * priv->port_width;
1799 spm_reg = priv->r->mir_spm + group * 4 * priv->port_width;
1800
1801 pr_debug("Using group %d\n", group);
1802 mutex_lock(&priv->reg_mutex);
1803
1804 if (priv->family_id == RTL8380_FAMILY_ID) {
1805 /* Enable mirroring to port across VLANs (bit 11) */
1806 sw_w32(1 << 11 | (mirror->to_local_port << 4) | 1, ctrl_reg);
1807 } else {
1808 /* Enable mirroring to destination port */
1809 sw_w32((mirror->to_local_port << 4) | 1, ctrl_reg);
1810 }
1811
1812 if (ingress && (priv->r->get_port_reg_be(spm_reg) & (1ULL << port))) {
1813 mutex_unlock(&priv->reg_mutex);
1814 return -EEXIST;
1815 }
1816 if ((!ingress) && (priv->r->get_port_reg_be(dpm_reg) & (1ULL << port))) {
1817 mutex_unlock(&priv->reg_mutex);
1818 return -EEXIST;
1819 }
1820
1821 if (ingress)
1822 priv->r->mask_port_reg_be(0, 1ULL << port, spm_reg);
1823 else
1824 priv->r->mask_port_reg_be(0, 1ULL << port, dpm_reg);
1825
1826 priv->mirror_group_ports[group] = mirror->to_local_port;
1827 mutex_unlock(&priv->reg_mutex);
1828 return 0;
1829 }
1830
1831 static void rtl83xx_port_mirror_del(struct dsa_switch *ds, int port,
1832 struct dsa_mall_mirror_tc_entry *mirror)
1833 {
1834 int group = 0;
1835 struct rtl838x_switch_priv *priv = ds->priv;
1836 int ctrl_reg, dpm_reg, spm_reg;
1837
1838 pr_debug("In %s\n", __func__);
1839 for (group = 0; group < 4; group++) {
1840 if (priv->mirror_group_ports[group] == mirror->to_local_port)
1841 break;
1842 }
1843 if (group >= 4)
1844 return;
1845
1846 ctrl_reg = priv->r->mir_ctrl + group * 4;
1847 dpm_reg = priv->r->mir_dpm + group * 4 * priv->port_width;
1848 spm_reg = priv->r->mir_spm + group * 4 * priv->port_width;
1849
1850 mutex_lock(&priv->reg_mutex);
1851 if (mirror->ingress) {
1852 /* Ingress, clear source port matrix */
1853 priv->r->mask_port_reg_be(1ULL << port, 0, spm_reg);
1854 } else {
1855 /* Egress, clear destination port matrix */
1856 priv->r->mask_port_reg_be(1ULL << port, 0, dpm_reg);
1857 }
1858
1859 if (!(sw_r32(spm_reg) || sw_r32(dpm_reg))) {
1860 priv->mirror_group_ports[group] = -1;
1861 sw_w32(0, ctrl_reg);
1862 }
1863
1864 mutex_unlock(&priv->reg_mutex);
1865 }
1866
1867 int dsa_phy_read(struct dsa_switch *ds, int phy_addr, int phy_reg)
1868 {
1869 u32 val;
1870 u32 offset = 0;
1871 struct rtl838x_switch_priv *priv = ds->priv;
1872
1873 if (phy_addr >= 24 && phy_addr <= 27
1874 && priv->ports[24].phy == PHY_RTL838X_SDS) {
1875 if (phy_addr == 26)
1876 offset = 0x100;
1877 val = sw_r32(RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2)) & 0xffff;
1878 return val;
1879 }
1880
1881 read_phy(phy_addr, 0, phy_reg, &val);
1882 return val;
1883 }
1884
1885 int dsa_phy_write(struct dsa_switch *ds, int phy_addr, int phy_reg, u16 val)
1886 {
1887 u32 offset = 0;
1888 struct rtl838x_switch_priv *priv = ds->priv;
1889
1890 if (phy_addr >= 24 && phy_addr <= 27
1891 && priv->ports[24].phy == PHY_RTL838X_SDS) {
1892 if (phy_addr == 26)
1893 offset = 0x100;
1894 sw_w32(val, RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2));
1895 return 0;
1896 }
1897 return write_phy(phy_addr, 0, phy_reg, val);
1898 }
1899
1900 const struct dsa_switch_ops rtl83xx_switch_ops = {
1901 .get_tag_protocol = rtl83xx_get_tag_protocol,
1902 .setup = rtl83xx_setup,
1903
1904 .phy_read = dsa_phy_read,
1905 .phy_write = dsa_phy_write,
1906
1907 .phylink_validate = rtl83xx_phylink_validate,
1908 .phylink_mac_link_state = rtl83xx_phylink_mac_link_state,
1909 .phylink_mac_config = rtl83xx_phylink_mac_config,
1910 .phylink_mac_link_down = rtl83xx_phylink_mac_link_down,
1911 .phylink_mac_link_up = rtl83xx_phylink_mac_link_up,
1912
1913 .get_strings = rtl83xx_get_strings,
1914 .get_ethtool_stats = rtl83xx_get_ethtool_stats,
1915 .get_sset_count = rtl83xx_get_sset_count,
1916
1917 .port_enable = rtl83xx_port_enable,
1918 .port_disable = rtl83xx_port_disable,
1919
1920 .get_mac_eee = rtl83xx_get_mac_eee,
1921 .set_mac_eee = rtl83xx_set_mac_eee,
1922
1923 .set_ageing_time = rtl83xx_set_l2aging,
1924 .port_bridge_join = rtl83xx_port_bridge_join,
1925 .port_bridge_leave = rtl83xx_port_bridge_leave,
1926 .port_stp_state_set = rtl83xx_port_stp_state_set,
1927 .port_fast_age = rtl83xx_fast_age,
1928
1929 .port_vlan_filtering = rtl83xx_vlan_filtering,
1930 .port_vlan_prepare = rtl83xx_vlan_prepare,
1931 .port_vlan_add = rtl83xx_vlan_add,
1932 .port_vlan_del = rtl83xx_vlan_del,
1933
1934 .port_fdb_add = rtl83xx_port_fdb_add,
1935 .port_fdb_del = rtl83xx_port_fdb_del,
1936 .port_fdb_dump = rtl83xx_port_fdb_dump,
1937
1938 .port_mdb_prepare = rtl83xx_port_mdb_prepare,
1939 .port_mdb_add = rtl83xx_port_mdb_add,
1940 .port_mdb_del = rtl83xx_port_mdb_del,
1941
1942 .port_mirror_add = rtl83xx_port_mirror_add,
1943 .port_mirror_del = rtl83xx_port_mirror_del,
1944 };
1945
1946 const struct dsa_switch_ops rtl930x_switch_ops = {
1947 .get_tag_protocol = rtl83xx_get_tag_protocol,
1948 .setup = rtl93xx_setup,
1949
1950 .phy_read = dsa_phy_read,
1951 .phy_write = dsa_phy_write,
1952
1953 .phylink_validate = rtl93xx_phylink_validate,
1954 .phylink_mac_link_state = rtl93xx_phylink_mac_link_state,
1955 .phylink_mac_config = rtl93xx_phylink_mac_config,
1956 .phylink_mac_link_down = rtl93xx_phylink_mac_link_down,
1957 .phylink_mac_link_up = rtl93xx_phylink_mac_link_up,
1958
1959 .get_strings = rtl83xx_get_strings,
1960 .get_ethtool_stats = rtl83xx_get_ethtool_stats,
1961 .get_sset_count = rtl83xx_get_sset_count,
1962
1963 .port_enable = rtl83xx_port_enable,
1964 .port_disable = rtl83xx_port_disable,
1965
1966 .get_mac_eee = rtl93xx_get_mac_eee,
1967 .set_mac_eee = rtl83xx_set_mac_eee,
1968
1969 .set_ageing_time = rtl83xx_set_l2aging,
1970 .port_bridge_join = rtl83xx_port_bridge_join,
1971 .port_bridge_leave = rtl83xx_port_bridge_leave,
1972 .port_stp_state_set = rtl83xx_port_stp_state_set,
1973 .port_fast_age = rtl930x_fast_age,
1974
1975 .port_vlan_filtering = rtl83xx_vlan_filtering,
1976 .port_vlan_prepare = rtl83xx_vlan_prepare,
1977 .port_vlan_add = rtl83xx_vlan_add,
1978 .port_vlan_del = rtl83xx_vlan_del,
1979
1980 .port_fdb_add = rtl83xx_port_fdb_add,
1981 .port_fdb_del = rtl83xx_port_fdb_del,
1982 .port_fdb_dump = rtl83xx_port_fdb_dump,
1983
1984 .port_mdb_prepare = rtl83xx_port_mdb_prepare,
1985 .port_mdb_add = rtl83xx_port_mdb_add,
1986 .port_mdb_del = rtl83xx_port_mdb_del,
1987
1988 };
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