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[openwrt/staging/wigyori.git] / target / linux / realtek / files-5.10 / drivers / net / dsa / rtl83xx / dsa.c
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <net/dsa.h>
4 #include <linux/if_bridge.h>
5
6 #include <asm/mach-rtl838x/mach-rtl83xx.h>
7 #include "rtl83xx.h"
8
9
10 extern struct rtl83xx_soc_info soc_info;
11
12
13 static void rtl83xx_init_stats(struct rtl838x_switch_priv *priv)
14 {
15 mutex_lock(&priv->reg_mutex);
16
17 /* Enable statistics module: all counters plus debug.
18 * On RTL839x all counters are enabled by default
19 */
20 if (priv->family_id == RTL8380_FAMILY_ID)
21 sw_w32_mask(0, 3, RTL838X_STAT_CTRL);
22
23 /* Reset statistics counters */
24 sw_w32_mask(0, 1, priv->r->stat_rst);
25
26 mutex_unlock(&priv->reg_mutex);
27 }
28
29 static void rtl83xx_enable_phy_polling(struct rtl838x_switch_priv *priv)
30 {
31 int i;
32 u64 v = 0;
33
34 msleep(1000);
35 /* Enable all ports with a PHY, including the SFP-ports */
36 for (i = 0; i < priv->cpu_port; i++) {
37 if (priv->ports[i].phy)
38 v |= BIT_ULL(i);
39 }
40
41 pr_debug("%s: %16llx\n", __func__, v);
42 priv->r->set_port_reg_le(v, priv->r->smi_poll_ctrl);
43
44 /* PHY update complete, there is no global PHY polling enable bit on the 9300 */
45 if (priv->family_id == RTL8390_FAMILY_ID)
46 sw_w32_mask(0, BIT(7), RTL839X_SMI_GLB_CTRL);
47 else if(priv->family_id == RTL9300_FAMILY_ID)
48 sw_w32_mask(0, 0x8000, RTL838X_SMI_GLB_CTRL);
49 }
50
51 const struct rtl83xx_mib_desc rtl83xx_mib[] = {
52 MIB_DESC(2, 0xf8, "ifInOctets"),
53 MIB_DESC(2, 0xf0, "ifOutOctets"),
54 MIB_DESC(1, 0xec, "dot1dTpPortInDiscards"),
55 MIB_DESC(1, 0xe8, "ifInUcastPkts"),
56 MIB_DESC(1, 0xe4, "ifInMulticastPkts"),
57 MIB_DESC(1, 0xe0, "ifInBroadcastPkts"),
58 MIB_DESC(1, 0xdc, "ifOutUcastPkts"),
59 MIB_DESC(1, 0xd8, "ifOutMulticastPkts"),
60 MIB_DESC(1, 0xd4, "ifOutBroadcastPkts"),
61 MIB_DESC(1, 0xd0, "ifOutDiscards"),
62 MIB_DESC(1, 0xcc, ".3SingleCollisionFrames"),
63 MIB_DESC(1, 0xc8, ".3MultipleCollisionFrames"),
64 MIB_DESC(1, 0xc4, ".3DeferredTransmissions"),
65 MIB_DESC(1, 0xc0, ".3LateCollisions"),
66 MIB_DESC(1, 0xbc, ".3ExcessiveCollisions"),
67 MIB_DESC(1, 0xb8, ".3SymbolErrors"),
68 MIB_DESC(1, 0xb4, ".3ControlInUnknownOpcodes"),
69 MIB_DESC(1, 0xb0, ".3InPauseFrames"),
70 MIB_DESC(1, 0xac, ".3OutPauseFrames"),
71 MIB_DESC(1, 0xa8, "DropEvents"),
72 MIB_DESC(1, 0xa4, "tx_BroadcastPkts"),
73 MIB_DESC(1, 0xa0, "tx_MulticastPkts"),
74 MIB_DESC(1, 0x9c, "CRCAlignErrors"),
75 MIB_DESC(1, 0x98, "tx_UndersizePkts"),
76 MIB_DESC(1, 0x94, "rx_UndersizePkts"),
77 MIB_DESC(1, 0x90, "rx_UndersizedropPkts"),
78 MIB_DESC(1, 0x8c, "tx_OversizePkts"),
79 MIB_DESC(1, 0x88, "rx_OversizePkts"),
80 MIB_DESC(1, 0x84, "Fragments"),
81 MIB_DESC(1, 0x80, "Jabbers"),
82 MIB_DESC(1, 0x7c, "Collisions"),
83 MIB_DESC(1, 0x78, "tx_Pkts64Octets"),
84 MIB_DESC(1, 0x74, "rx_Pkts64Octets"),
85 MIB_DESC(1, 0x70, "tx_Pkts65to127Octets"),
86 MIB_DESC(1, 0x6c, "rx_Pkts65to127Octets"),
87 MIB_DESC(1, 0x68, "tx_Pkts128to255Octets"),
88 MIB_DESC(1, 0x64, "rx_Pkts128to255Octets"),
89 MIB_DESC(1, 0x60, "tx_Pkts256to511Octets"),
90 MIB_DESC(1, 0x5c, "rx_Pkts256to511Octets"),
91 MIB_DESC(1, 0x58, "tx_Pkts512to1023Octets"),
92 MIB_DESC(1, 0x54, "rx_Pkts512to1023Octets"),
93 MIB_DESC(1, 0x50, "tx_Pkts1024to1518Octets"),
94 MIB_DESC(1, 0x4c, "rx_StatsPkts1024to1518Octets"),
95 MIB_DESC(1, 0x48, "tx_Pkts1519toMaxOctets"),
96 MIB_DESC(1, 0x44, "rx_Pkts1519toMaxOctets"),
97 MIB_DESC(1, 0x40, "rxMacDiscards")
98 };
99
100
101 /* DSA callbacks */
102
103
104 static enum dsa_tag_protocol rtl83xx_get_tag_protocol(struct dsa_switch *ds,
105 int port,
106 enum dsa_tag_protocol mprot)
107 {
108 /* The switch does not tag the frames, instead internally the header
109 * structure for each packet is tagged accordingly.
110 */
111 return DSA_TAG_PROTO_TRAILER;
112 }
113
114 /*
115 * Initialize all VLANS
116 */
117 static void rtl83xx_vlan_setup(struct rtl838x_switch_priv *priv)
118 {
119 struct rtl838x_vlan_info info;
120 int i;
121
122 pr_info("In %s\n", __func__);
123
124 priv->r->vlan_profile_setup(0);
125 priv->r->vlan_profile_setup(1);
126 pr_info("UNKNOWN_MC_PMASK: %016llx\n", priv->r->read_mcast_pmask(UNKNOWN_MC_PMASK));
127 priv->r->vlan_profile_dump(0);
128
129 info.fid = 0; // Default Forwarding ID / MSTI
130 info.hash_uc_fid = false; // Do not build the L2 lookup hash with FID, but VID
131 info.hash_mc_fid = false; // Do the same for Multicast packets
132 info.profile_id = 0; // Use default Vlan Profile 0
133 info.tagged_ports = 0; // Initially no port members
134
135 // Initialize all vlans 0-4095
136 for (i = 0; i < MAX_VLANS; i ++)
137 priv->r->vlan_set_tagged(i, &info);
138
139 // reset PVIDs; defaults to 1 on reset
140 for (i = 0; i <= priv->ds->num_ports; i++)
141 sw_w32(0, priv->r->vlan_port_pb + (i << 2));
142
143 // Set forwarding action based on inner VLAN tag
144 for (i = 0; i < priv->cpu_port; i++)
145 priv->r->vlan_fwd_on_inner(i, true);
146 }
147
148 static int rtl83xx_setup(struct dsa_switch *ds)
149 {
150 int i;
151 struct rtl838x_switch_priv *priv = ds->priv;
152 u64 port_bitmap = BIT_ULL(priv->cpu_port);
153
154 pr_debug("%s called\n", __func__);
155
156 /* Disable MAC polling the PHY so that we can start configuration */
157 priv->r->set_port_reg_le(0ULL, priv->r->smi_poll_ctrl);
158
159 for (i = 0; i < ds->num_ports; i++)
160 priv->ports[i].enable = false;
161 priv->ports[priv->cpu_port].enable = true;
162
163 /* Isolate ports from each other: traffic only CPU <-> port */
164 /* Setting bit j in register RTL838X_PORT_ISO_CTRL(i) allows
165 * traffic from source port i to destination port j
166 */
167 for (i = 0; i < priv->cpu_port; i++) {
168 if (priv->ports[i].phy) {
169 priv->r->set_port_reg_be(BIT_ULL(priv->cpu_port) | BIT_ULL(i),
170 priv->r->port_iso_ctrl(i));
171 port_bitmap |= BIT_ULL(i);
172 }
173 }
174 priv->r->set_port_reg_be(port_bitmap, priv->r->port_iso_ctrl(priv->cpu_port));
175
176 if (priv->family_id == RTL8380_FAMILY_ID)
177 rtl838x_print_matrix();
178 else
179 rtl839x_print_matrix();
180
181 rtl83xx_init_stats(priv);
182
183 rtl83xx_vlan_setup(priv);
184
185 ds->configure_vlan_while_not_filtering = true;
186
187 priv->r->l2_learning_setup();
188
189 /* Enable MAC Polling PHY again */
190 rtl83xx_enable_phy_polling(priv);
191 pr_debug("Please wait until PHY is settled\n");
192 msleep(1000);
193 priv->r->pie_init(priv);
194
195 return 0;
196 }
197
198 static int rtl930x_setup(struct dsa_switch *ds)
199 {
200 int i;
201 struct rtl838x_switch_priv *priv = ds->priv;
202 u32 port_bitmap = BIT(priv->cpu_port);
203
204 pr_info("%s called\n", __func__);
205
206 // Enable CSTI STP mode
207 // sw_w32(1, RTL930X_ST_CTRL);
208
209 /* Disable MAC polling the PHY so that we can start configuration */
210 sw_w32(0, RTL930X_SMI_POLL_CTRL);
211
212 // Disable all ports except CPU port
213 for (i = 0; i < ds->num_ports; i++)
214 priv->ports[i].enable = false;
215 priv->ports[priv->cpu_port].enable = true;
216
217 for (i = 0; i < priv->cpu_port; i++) {
218 if (priv->ports[i].phy) {
219 priv->r->traffic_set(i, BIT_ULL(priv->cpu_port) | BIT_ULL(i));
220 port_bitmap |= BIT_ULL(i);
221 }
222 }
223 priv->r->traffic_set(priv->cpu_port, port_bitmap);
224
225 rtl930x_print_matrix();
226
227 // TODO: Initialize statistics
228
229 rtl83xx_vlan_setup(priv);
230
231 ds->configure_vlan_while_not_filtering = true;
232
233 priv->r->l2_learning_setup();
234
235 rtl83xx_enable_phy_polling(priv);
236
237 priv->r->pie_init(priv);
238
239 return 0;
240 }
241
242 static void rtl83xx_phylink_validate(struct dsa_switch *ds, int port,
243 unsigned long *supported,
244 struct phylink_link_state *state)
245 {
246 struct rtl838x_switch_priv *priv = ds->priv;
247 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
248
249 pr_debug("In %s port %d, state is %d", __func__, port, state->interface);
250
251 if (!phy_interface_mode_is_rgmii(state->interface) &&
252 state->interface != PHY_INTERFACE_MODE_NA &&
253 state->interface != PHY_INTERFACE_MODE_1000BASEX &&
254 state->interface != PHY_INTERFACE_MODE_MII &&
255 state->interface != PHY_INTERFACE_MODE_REVMII &&
256 state->interface != PHY_INTERFACE_MODE_GMII &&
257 state->interface != PHY_INTERFACE_MODE_QSGMII &&
258 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
259 state->interface != PHY_INTERFACE_MODE_SGMII) {
260 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
261 dev_err(ds->dev,
262 "Unsupported interface: %d for port %d\n",
263 state->interface, port);
264 return;
265 }
266
267 /* Allow all the expected bits */
268 phylink_set(mask, Autoneg);
269 phylink_set_port_modes(mask);
270 phylink_set(mask, Pause);
271 phylink_set(mask, Asym_Pause);
272
273 /* With the exclusion of MII and Reverse MII, we support Gigabit,
274 * including Half duplex
275 */
276 if (state->interface != PHY_INTERFACE_MODE_MII &&
277 state->interface != PHY_INTERFACE_MODE_REVMII) {
278 phylink_set(mask, 1000baseT_Full);
279 phylink_set(mask, 1000baseT_Half);
280 }
281
282 /* On both the 8380 and 8382, ports 24-27 are SFP ports */
283 if (port >= 24 && port <= 27 && priv->family_id == RTL8380_FAMILY_ID)
284 phylink_set(mask, 1000baseX_Full);
285
286 /* On the RTL839x family of SoCs, ports 48 to 51 are SFP ports */
287 if (port >= 48 && port <= 51 && priv->family_id == RTL8390_FAMILY_ID)
288 phylink_set(mask, 1000baseX_Full);
289
290 phylink_set(mask, 10baseT_Half);
291 phylink_set(mask, 10baseT_Full);
292 phylink_set(mask, 100baseT_Half);
293 phylink_set(mask, 100baseT_Full);
294
295 bitmap_and(supported, supported, mask,
296 __ETHTOOL_LINK_MODE_MASK_NBITS);
297 bitmap_and(state->advertising, state->advertising, mask,
298 __ETHTOOL_LINK_MODE_MASK_NBITS);
299 }
300
301 static void rtl93xx_phylink_validate(struct dsa_switch *ds, int port,
302 unsigned long *supported,
303 struct phylink_link_state *state)
304 {
305 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
306
307 pr_debug("In %s port %d, state is %d (%s)", __func__, port, state->interface,
308 phy_modes(state->interface));
309
310 if (!phy_interface_mode_is_rgmii(state->interface) &&
311 state->interface != PHY_INTERFACE_MODE_NA &&
312 state->interface != PHY_INTERFACE_MODE_1000BASEX &&
313 state->interface != PHY_INTERFACE_MODE_MII &&
314 state->interface != PHY_INTERFACE_MODE_REVMII &&
315 state->interface != PHY_INTERFACE_MODE_GMII &&
316 state->interface != PHY_INTERFACE_MODE_QSGMII &&
317 state->interface != PHY_INTERFACE_MODE_XGMII &&
318 state->interface != PHY_INTERFACE_MODE_HSGMII &&
319 state->interface != PHY_INTERFACE_MODE_10GKR &&
320 state->interface != PHY_INTERFACE_MODE_USXGMII &&
321 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
322 state->interface != PHY_INTERFACE_MODE_SGMII) {
323 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
324 dev_err(ds->dev,
325 "Unsupported interface: %d for port %d\n",
326 state->interface, port);
327 return;
328 }
329
330 /* Allow all the expected bits */
331 phylink_set(mask, Autoneg);
332 phylink_set_port_modes(mask);
333 phylink_set(mask, Pause);
334 phylink_set(mask, Asym_Pause);
335
336 /* With the exclusion of MII and Reverse MII, we support Gigabit,
337 * including Half duplex
338 */
339 if (state->interface != PHY_INTERFACE_MODE_MII &&
340 state->interface != PHY_INTERFACE_MODE_REVMII) {
341 phylink_set(mask, 1000baseT_Full);
342 phylink_set(mask, 1000baseT_Half);
343 }
344
345 /* On the RTL9300 family of SoCs, ports 26 to 27 may be SFP ports TODO: take out of .dts */
346 if (port >= 26 && port <= 27)
347 phylink_set(mask, 1000baseX_Full);
348 if (port >= 26 && port <= 27)
349 phylink_set(mask, 10000baseKR_Full);
350
351 phylink_set(mask, 10baseT_Half);
352 phylink_set(mask, 10baseT_Full);
353 phylink_set(mask, 100baseT_Half);
354 phylink_set(mask, 100baseT_Full);
355
356 bitmap_and(supported, supported, mask,
357 __ETHTOOL_LINK_MODE_MASK_NBITS);
358 bitmap_and(state->advertising, state->advertising, mask,
359 __ETHTOOL_LINK_MODE_MASK_NBITS);
360 }
361
362 static int rtl83xx_phylink_mac_link_state(struct dsa_switch *ds, int port,
363 struct phylink_link_state *state)
364 {
365 struct rtl838x_switch_priv *priv = ds->priv;
366 u64 speed;
367 u64 link;
368
369 if (port < 0 || port > priv->cpu_port)
370 return -EINVAL;
371
372 state->link = 0;
373 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
374 if (link & BIT_ULL(port))
375 state->link = 1;
376 pr_debug("%s: link state port %d: %llx\n", __func__, port, link & BIT_ULL(port));
377
378 state->duplex = 0;
379 if (priv->r->get_port_reg_le(priv->r->mac_link_dup_sts) & BIT_ULL(port))
380 state->duplex = 1;
381
382 speed = priv->r->get_port_reg_le(priv->r->mac_link_spd_sts(port));
383 speed >>= (port % 16) << 1;
384 switch (speed & 0x3) {
385 case 0:
386 state->speed = SPEED_10;
387 break;
388 case 1:
389 state->speed = SPEED_100;
390 break;
391 case 2:
392 state->speed = SPEED_1000;
393 break;
394 case 3:
395 if (priv->family_id == RTL9300_FAMILY_ID
396 && (port == 24 || port == 26)) /* Internal serdes */
397 state->speed = SPEED_2500;
398 else
399 state->speed = SPEED_100; /* Is in fact 500Mbit */
400 }
401
402 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
403 if (priv->r->get_port_reg_le(priv->r->mac_rx_pause_sts) & BIT_ULL(port))
404 state->pause |= MLO_PAUSE_RX;
405 if (priv->r->get_port_reg_le(priv->r->mac_tx_pause_sts) & BIT_ULL(port))
406 state->pause |= MLO_PAUSE_TX;
407 return 1;
408 }
409
410 static int rtl93xx_phylink_mac_link_state(struct dsa_switch *ds, int port,
411 struct phylink_link_state *state)
412 {
413 struct rtl838x_switch_priv *priv = ds->priv;
414 u64 speed;
415 u64 link;
416
417 if (port < 0 || port > priv->cpu_port)
418 return -EINVAL;
419
420 /*
421 * On the RTL9300 for at least the RTL8226B PHY, the MAC-side link
422 * state needs to be read twice in order to read a correct result.
423 * This would not be necessary for ports connected e.g. to RTL8218D
424 * PHYs.
425 */
426 state->link = 0;
427 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
428 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
429 if (link & BIT_ULL(port))
430 state->link = 1;
431 pr_debug("%s: link state port %d: %llx, media %08x\n", __func__, port,
432 link & BIT_ULL(port), sw_r32(RTL930X_MAC_LINK_MEDIA_STS));
433
434 state->duplex = 0;
435 if (priv->r->get_port_reg_le(priv->r->mac_link_dup_sts) & BIT_ULL(port))
436 state->duplex = 1;
437
438 speed = priv->r->get_port_reg_le(priv->r->mac_link_spd_sts(port));
439 speed >>= (port % 8) << 2;
440 switch (speed & 0xf) {
441 case 0:
442 state->speed = SPEED_10;
443 break;
444 case 1:
445 state->speed = SPEED_100;
446 break;
447 case 2:
448 case 7:
449 state->speed = SPEED_1000;
450 break;
451 case 4:
452 state->speed = SPEED_10000;
453 break;
454 case 5:
455 case 8:
456 state->speed = SPEED_2500;
457 break;
458 case 6:
459 state->speed = SPEED_5000;
460 break;
461 default:
462 pr_err("%s: unknown speed: %d\n", __func__, (u32)speed & 0xf);
463 }
464
465 pr_debug("%s: speed is: %d %d\n", __func__, (u32)speed & 0xf, state->speed);
466 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
467 if (priv->r->get_port_reg_le(priv->r->mac_rx_pause_sts) & BIT_ULL(port))
468 state->pause |= MLO_PAUSE_RX;
469 if (priv->r->get_port_reg_le(priv->r->mac_tx_pause_sts) & BIT_ULL(port))
470 state->pause |= MLO_PAUSE_TX;
471 return 1;
472 }
473
474 static void rtl83xx_config_interface(int port, phy_interface_t interface)
475 {
476 u32 old, int_shift, sds_shift;
477
478 switch (port) {
479 case 24:
480 int_shift = 0;
481 sds_shift = 5;
482 break;
483 case 26:
484 int_shift = 3;
485 sds_shift = 0;
486 break;
487 default:
488 return;
489 }
490
491 old = sw_r32(RTL838X_SDS_MODE_SEL);
492 switch (interface) {
493 case PHY_INTERFACE_MODE_1000BASEX:
494 if ((old >> sds_shift & 0x1f) == 4)
495 return;
496 sw_w32_mask(0x7 << int_shift, 1 << int_shift, RTL838X_INT_MODE_CTRL);
497 sw_w32_mask(0x1f << sds_shift, 4 << sds_shift, RTL838X_SDS_MODE_SEL);
498 break;
499 case PHY_INTERFACE_MODE_SGMII:
500 if ((old >> sds_shift & 0x1f) == 2)
501 return;
502 sw_w32_mask(0x7 << int_shift, 2 << int_shift, RTL838X_INT_MODE_CTRL);
503 sw_w32_mask(0x1f << sds_shift, 2 << sds_shift, RTL838X_SDS_MODE_SEL);
504 break;
505 default:
506 return;
507 }
508 pr_debug("configured port %d for interface %s\n", port, phy_modes(interface));
509 }
510
511 static void rtl83xx_phylink_mac_config(struct dsa_switch *ds, int port,
512 unsigned int mode,
513 const struct phylink_link_state *state)
514 {
515 struct rtl838x_switch_priv *priv = ds->priv;
516 u32 reg;
517 int speed_bit = priv->family_id == RTL8380_FAMILY_ID ? 4 : 3;
518
519 pr_debug("%s port %d, mode %x\n", __func__, port, mode);
520
521 if (port == priv->cpu_port) {
522 /* Set Speed, duplex, flow control
523 * FORCE_EN | LINK_EN | NWAY_EN | DUP_SEL
524 * | SPD_SEL = 0b10 | FORCE_FC_EN | PHY_MASTER_SLV_MANUAL_EN
525 * | MEDIA_SEL
526 */
527 if (priv->family_id == RTL8380_FAMILY_ID) {
528 sw_w32(0x6192F, priv->r->mac_force_mode_ctrl(priv->cpu_port));
529 /* allow CRC errors on CPU-port */
530 sw_w32_mask(0, 0x8, RTL838X_MAC_PORT_CTRL(priv->cpu_port));
531 } else {
532 sw_w32_mask(0, 3, priv->r->mac_force_mode_ctrl(priv->cpu_port));
533 }
534 return;
535 }
536
537 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
538 /* Auto-Negotiation does not work for MAC in RTL8390 */
539 if (priv->family_id == RTL8380_FAMILY_ID) {
540 if (mode == MLO_AN_PHY || phylink_autoneg_inband(mode)) {
541 pr_debug("PHY autonegotiates\n");
542 reg |= BIT(2);
543 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
544 rtl83xx_config_interface(port, state->interface);
545 return;
546 }
547 }
548
549 if (mode != MLO_AN_FIXED)
550 pr_debug("Fixed state.\n");
551
552 if (priv->family_id == RTL8380_FAMILY_ID) {
553 /* Clear id_mode_dis bit, and the existing port mode, let
554 * RGMII_MODE_EN bet set by mac_link_{up,down}
555 */
556 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN);
557
558 if (state->pause & MLO_PAUSE_TXRX_MASK) {
559 if (state->pause & MLO_PAUSE_TX)
560 reg |= TX_PAUSE_EN;
561 reg |= RX_PAUSE_EN;
562 }
563 }
564
565 reg &= ~(3 << speed_bit);
566 switch (state->speed) {
567 case SPEED_1000:
568 reg |= 2 << speed_bit;
569 break;
570 case SPEED_100:
571 reg |= 1 << speed_bit;
572 break;
573 }
574
575 if (priv->family_id == RTL8380_FAMILY_ID) {
576 reg &= ~(DUPLEX_FULL | FORCE_LINK_EN);
577 if (state->link)
578 reg |= FORCE_LINK_EN;
579 if (state->duplex == DUPLEX_FULL)
580 reg |= DUPLX_MODE;
581 }
582
583 // Disable AN
584 if (priv->family_id == RTL8380_FAMILY_ID)
585 reg &= ~BIT(2);
586 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
587 }
588
589 static void rtl93xx_phylink_mac_config(struct dsa_switch *ds, int port,
590 unsigned int mode,
591 const struct phylink_link_state *state)
592 {
593 struct rtl838x_switch_priv *priv = ds->priv;
594 int sds_num, sds_mode;
595 u32 reg;
596
597 pr_debug("%s port %d, mode %x, phy-mode: %s, speed %d, link %d\n", __func__,
598 port, mode, phy_modes(state->interface), state->speed, state->link);
599
600 // Nothing to be done for the CPU-port
601 if (port == priv->cpu_port)
602 return;
603
604 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
605 reg &= ~(0xf << 3);
606
607 // On the RTL930X, ports 24 to 27 are using an internal SerDes
608 if (port >=24 && port <= 27) {
609 sds_num = port - 18; // Port 24 mapped to SerDes 6, 25 to 7 ...
610 switch (state->interface) {
611 case PHY_INTERFACE_MODE_HSGMII:
612 sds_mode = 0x12;
613 break;
614 case PHY_INTERFACE_MODE_1000BASEX:
615 sds_mode = 0x1b; // 10G 1000X Auto
616 break;
617 case PHY_INTERFACE_MODE_XGMII:
618 sds_mode = 0x10;
619 break;
620 case PHY_INTERFACE_MODE_10GKR:
621 sds_mode = 0x1a;
622 // We need to use media sel for fibre media:
623 reg |= BIT(16);
624 break;
625 case PHY_INTERFACE_MODE_USXGMII:
626 sds_mode = 0x0d;
627 break;
628 default:
629 pr_err("%s: unknown serdes mode: %s\n",
630 __func__, phy_modes(state->interface));
631 return;
632 }
633 rtl9300_sds_rst(sds_num, sds_mode);
634 }
635
636 switch (state->speed) {
637 case SPEED_10000:
638 reg |= 4 << 3;
639 break;
640 case SPEED_5000:
641 reg |= 6 << 3;
642 break;
643 case SPEED_2500:
644 reg |= 5 << 3;
645 break;
646 case SPEED_1000:
647 reg |= 2 << 3;
648 break;
649 default:
650 reg |= 2 << 3;
651 break;
652 }
653
654 if (state->link)
655 reg |= FORCE_LINK_EN;
656
657 if (state->duplex == DUPLEX_FULL)
658 reg |= BIT(2);
659
660 reg |= 1; // Force Link up
661 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
662 }
663
664 static void rtl83xx_phylink_mac_link_down(struct dsa_switch *ds, int port,
665 unsigned int mode,
666 phy_interface_t interface)
667 {
668 struct rtl838x_switch_priv *priv = ds->priv;
669 /* Stop TX/RX to port */
670 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(port));
671 }
672
673 static void rtl93xx_phylink_mac_link_down(struct dsa_switch *ds, int port,
674 unsigned int mode,
675 phy_interface_t interface)
676 {
677 struct rtl838x_switch_priv *priv = ds->priv;
678 /* Stop TX/RX to port */
679 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(port));
680
681 // No longer force link
682 sw_w32_mask(3, 0, priv->r->mac_force_mode_ctrl(port));
683 }
684
685 static void rtl83xx_phylink_mac_link_up(struct dsa_switch *ds, int port,
686 unsigned int mode,
687 phy_interface_t interface,
688 struct phy_device *phydev,
689 int speed, int duplex,
690 bool tx_pause, bool rx_pause)
691 {
692 struct rtl838x_switch_priv *priv = ds->priv;
693 /* Restart TX/RX to port */
694 sw_w32_mask(0, 0x3, priv->r->mac_port_ctrl(port));
695 // TODO: Set speed/duplex/pauses
696 }
697
698 static void rtl93xx_phylink_mac_link_up(struct dsa_switch *ds, int port,
699 unsigned int mode,
700 phy_interface_t interface,
701 struct phy_device *phydev,
702 int speed, int duplex,
703 bool tx_pause, bool rx_pause)
704 {
705 struct rtl838x_switch_priv *priv = ds->priv;
706
707 /* Restart TX/RX to port */
708 sw_w32_mask(0, 0x3, priv->r->mac_port_ctrl(port));
709 // TODO: Set speed/duplex/pauses
710 }
711
712 static void rtl83xx_get_strings(struct dsa_switch *ds,
713 int port, u32 stringset, u8 *data)
714 {
715 int i;
716
717 if (stringset != ETH_SS_STATS)
718 return;
719
720 for (i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++)
721 strncpy(data + i * ETH_GSTRING_LEN, rtl83xx_mib[i].name,
722 ETH_GSTRING_LEN);
723 }
724
725 static void rtl83xx_get_ethtool_stats(struct dsa_switch *ds, int port,
726 uint64_t *data)
727 {
728 struct rtl838x_switch_priv *priv = ds->priv;
729 const struct rtl83xx_mib_desc *mib;
730 int i;
731 u64 h;
732
733 for (i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++) {
734 mib = &rtl83xx_mib[i];
735
736 data[i] = sw_r32(priv->r->stat_port_std_mib + (port << 8) + 252 - mib->offset);
737 if (mib->size == 2) {
738 h = sw_r32(priv->r->stat_port_std_mib + (port << 8) + 248 - mib->offset);
739 data[i] |= h << 32;
740 }
741 }
742 }
743
744 static int rtl83xx_get_sset_count(struct dsa_switch *ds, int port, int sset)
745 {
746 if (sset != ETH_SS_STATS)
747 return 0;
748
749 return ARRAY_SIZE(rtl83xx_mib);
750 }
751
752 static int rtl83xx_port_enable(struct dsa_switch *ds, int port,
753 struct phy_device *phydev)
754 {
755 struct rtl838x_switch_priv *priv = ds->priv;
756 u64 v;
757
758 pr_debug("%s: %x %d", __func__, (u32) priv, port);
759 priv->ports[port].enable = true;
760
761 /* enable inner tagging on egress, do not keep any tags */
762 if (priv->family_id == RTL9310_FAMILY_ID)
763 sw_w32(BIT(4), priv->r->vlan_port_tag_sts_ctrl + (port << 2));
764 else
765 sw_w32(1, priv->r->vlan_port_tag_sts_ctrl + (port << 2));
766
767 if (dsa_is_cpu_port(ds, port))
768 return 0;
769
770 /* add port to switch mask of CPU_PORT */
771 priv->r->traffic_enable(priv->cpu_port, port);
772
773 /* add all other ports in the same bridge to switch mask of port */
774 v = priv->r->traffic_get(port);
775 v |= priv->ports[port].pm;
776 priv->r->traffic_set(port, v);
777
778 // TODO: Figure out if this is necessary
779 if (priv->family_id == RTL9300_FAMILY_ID) {
780 sw_w32_mask(0, BIT(port), RTL930X_L2_PORT_SABLK_CTRL);
781 sw_w32_mask(0, BIT(port), RTL930X_L2_PORT_DABLK_CTRL);
782 }
783
784 return 0;
785 }
786
787 static void rtl83xx_port_disable(struct dsa_switch *ds, int port)
788 {
789 struct rtl838x_switch_priv *priv = ds->priv;
790 u64 v;
791
792 pr_debug("%s %x: %d", __func__, (u32)priv, port);
793 /* you can only disable user ports */
794 if (!dsa_is_user_port(ds, port))
795 return;
796
797 // BUG: This does not work on RTL931X
798 /* remove port from switch mask of CPU_PORT */
799 priv->r->traffic_disable(priv->cpu_port, port);
800
801 /* remove all other ports in the same bridge from switch mask of port */
802 v = priv->r->traffic_get(port);
803 v &= ~priv->ports[port].pm;
804 priv->r->traffic_set(port, v);
805
806 priv->ports[port].enable = false;
807 }
808
809 static int rtl83xx_set_mac_eee(struct dsa_switch *ds, int port,
810 struct ethtool_eee *e)
811 {
812 struct rtl838x_switch_priv *priv = ds->priv;
813
814 if (e->eee_enabled && !priv->eee_enabled) {
815 pr_info("Globally enabling EEE\n");
816 priv->r->init_eee(priv, true);
817 }
818
819 priv->r->port_eee_set(priv, port, e->eee_enabled);
820
821 if (e->eee_enabled)
822 pr_info("Enabled EEE for port %d\n", port);
823 else
824 pr_info("Disabled EEE for port %d\n", port);
825 return 0;
826 }
827
828 static int rtl83xx_get_mac_eee(struct dsa_switch *ds, int port,
829 struct ethtool_eee *e)
830 {
831 struct rtl838x_switch_priv *priv = ds->priv;
832
833 e->supported = SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full;
834
835 priv->r->eee_port_ability(priv, e, port);
836
837 e->eee_enabled = priv->ports[port].eee_enabled;
838
839 e->eee_active = !!(e->advertised & e->lp_advertised);
840
841 return 0;
842 }
843
844 static int rtl93xx_get_mac_eee(struct dsa_switch *ds, int port,
845 struct ethtool_eee *e)
846 {
847 struct rtl838x_switch_priv *priv = ds->priv;
848
849 e->supported = SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full
850 | SUPPORTED_2500baseX_Full;
851
852 priv->r->eee_port_ability(priv, e, port);
853
854 e->eee_enabled = priv->ports[port].eee_enabled;
855
856 e->eee_active = !!(e->advertised & e->lp_advertised);
857
858 return 0;
859 }
860
861 /*
862 * Set Switch L2 Aging time, t is time in milliseconds
863 * t = 0: aging is disabled
864 */
865 static int rtl83xx_set_l2aging(struct dsa_switch *ds, u32 t)
866 {
867 struct rtl838x_switch_priv *priv = ds->priv;
868 int t_max = priv->family_id == RTL8380_FAMILY_ID ? 0x7fffff : 0x1FFFFF;
869
870 /* Convert time in mseconds to internal value */
871 if (t > 0x10000000) { /* Set to maximum */
872 t = t_max;
873 } else {
874 if (priv->family_id == RTL8380_FAMILY_ID)
875 t = ((t * 625) / 1000 + 127) / 128;
876 else
877 t = (t * 5 + 2) / 3;
878 }
879 sw_w32(t, priv->r->l2_ctrl_1);
880 return 0;
881 }
882
883 static int rtl83xx_port_bridge_join(struct dsa_switch *ds, int port,
884 struct net_device *bridge)
885 {
886 struct rtl838x_switch_priv *priv = ds->priv;
887 u64 port_bitmap = BIT_ULL(priv->cpu_port), v;
888 int i;
889
890 pr_debug("%s %x: %d %llx", __func__, (u32)priv, port, port_bitmap);
891 mutex_lock(&priv->reg_mutex);
892 for (i = 0; i < ds->num_ports; i++) {
893 /* Add this port to the port matrix of the other ports in the
894 * same bridge. If the port is disabled, port matrix is kept
895 * and not being setup until the port becomes enabled.
896 */
897 if (dsa_is_user_port(ds, i) && i != port) {
898 if (dsa_to_port(ds, i)->bridge_dev != bridge)
899 continue;
900 if (priv->ports[i].enable)
901 priv->r->traffic_enable(i, port);
902
903 priv->ports[i].pm |= BIT_ULL(port);
904 port_bitmap |= BIT_ULL(i);
905 }
906 }
907
908 /* Add all other ports to this port matrix. */
909 if (priv->ports[port].enable) {
910 priv->r->traffic_enable(priv->cpu_port, port);
911 v = priv->r->traffic_get(port);
912 v |= port_bitmap;
913 priv->r->traffic_set(port, v);
914 }
915 priv->ports[port].pm |= port_bitmap;
916 mutex_unlock(&priv->reg_mutex);
917
918 return 0;
919 }
920
921 static void rtl83xx_port_bridge_leave(struct dsa_switch *ds, int port,
922 struct net_device *bridge)
923 {
924 struct rtl838x_switch_priv *priv = ds->priv;
925 u64 port_bitmap = BIT_ULL(priv->cpu_port), v;
926 int i;
927
928 pr_debug("%s %x: %d", __func__, (u32)priv, port);
929 mutex_lock(&priv->reg_mutex);
930 for (i = 0; i < ds->num_ports; i++) {
931 /* Remove this port from the port matrix of the other ports
932 * in the same bridge. If the port is disabled, port matrix
933 * is kept and not being setup until the port becomes enabled.
934 * And the other port's port matrix cannot be broken when the
935 * other port is still a VLAN-aware port.
936 */
937 if (dsa_is_user_port(ds, i) && i != port) {
938 if (dsa_to_port(ds, i)->bridge_dev != bridge)
939 continue;
940 if (priv->ports[i].enable)
941 priv->r->traffic_disable(i, port);
942
943 priv->ports[i].pm |= BIT_ULL(port);
944 port_bitmap &= ~BIT_ULL(i);
945 }
946 }
947
948 /* Add all other ports to this port matrix. */
949 if (priv->ports[port].enable) {
950 v = priv->r->traffic_get(port);
951 v |= port_bitmap;
952 priv->r->traffic_set(port, v);
953 }
954 priv->ports[port].pm &= ~port_bitmap;
955
956 mutex_unlock(&priv->reg_mutex);
957 }
958
959 void rtl83xx_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
960 {
961 u32 msti = 0;
962 u32 port_state[4];
963 int index, bit;
964 int pos = port;
965 struct rtl838x_switch_priv *priv = ds->priv;
966 int n = priv->port_width << 1;
967
968 /* Ports above or equal CPU port can never be configured */
969 if (port >= priv->cpu_port)
970 return;
971
972 mutex_lock(&priv->reg_mutex);
973
974 /* For the RTL839x and following, the bits are left-aligned, 838x and 930x
975 * have 64 bit fields, 839x and 931x have 128 bit fields
976 */
977 if (priv->family_id == RTL8390_FAMILY_ID)
978 pos += 12;
979 if (priv->family_id == RTL9300_FAMILY_ID)
980 pos += 3;
981 if (priv->family_id == RTL9310_FAMILY_ID)
982 pos += 8;
983
984 index = n - (pos >> 4) - 1;
985 bit = (pos << 1) % 32;
986
987 priv->r->stp_get(priv, msti, port_state);
988
989 pr_debug("Current state, port %d: %d\n", port, (port_state[index] >> bit) & 3);
990 port_state[index] &= ~(3 << bit);
991
992 switch (state) {
993 case BR_STATE_DISABLED: /* 0 */
994 port_state[index] |= (0 << bit);
995 break;
996 case BR_STATE_BLOCKING: /* 4 */
997 case BR_STATE_LISTENING: /* 1 */
998 port_state[index] |= (1 << bit);
999 break;
1000 case BR_STATE_LEARNING: /* 2 */
1001 port_state[index] |= (2 << bit);
1002 break;
1003 case BR_STATE_FORWARDING: /* 3*/
1004 port_state[index] |= (3 << bit);
1005 default:
1006 break;
1007 }
1008
1009 priv->r->stp_set(priv, msti, port_state);
1010
1011 mutex_unlock(&priv->reg_mutex);
1012 }
1013
1014 void rtl83xx_fast_age(struct dsa_switch *ds, int port)
1015 {
1016 struct rtl838x_switch_priv *priv = ds->priv;
1017 int s = priv->family_id == RTL8390_FAMILY_ID ? 2 : 0;
1018
1019 pr_debug("FAST AGE port %d\n", port);
1020 mutex_lock(&priv->reg_mutex);
1021 /* RTL838X_L2_TBL_FLUSH_CTRL register bits, 839x has 1 bit larger
1022 * port fields:
1023 * 0-4: Replacing port
1024 * 5-9: Flushed/replaced port
1025 * 10-21: FVID
1026 * 22: Entry types: 1: dynamic, 0: also static
1027 * 23: Match flush port
1028 * 24: Match FVID
1029 * 25: Flush (0) or replace (1) L2 entries
1030 * 26: Status of action (1: Start, 0: Done)
1031 */
1032 sw_w32(1 << (26 + s) | 1 << (23 + s) | port << (5 + (s / 2)), priv->r->l2_tbl_flush_ctrl);
1033
1034 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(26 + s));
1035
1036 mutex_unlock(&priv->reg_mutex);
1037 }
1038
1039 void rtl930x_fast_age(struct dsa_switch *ds, int port)
1040 {
1041 struct rtl838x_switch_priv *priv = ds->priv;
1042
1043 pr_debug("FAST AGE port %d\n", port);
1044 mutex_lock(&priv->reg_mutex);
1045 sw_w32(port << 11, RTL930X_L2_TBL_FLUSH_CTRL + 4);
1046
1047 sw_w32(BIT(26) | BIT(30), RTL930X_L2_TBL_FLUSH_CTRL);
1048
1049 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(30));
1050
1051 mutex_unlock(&priv->reg_mutex);
1052 }
1053
1054 static int rtl83xx_vlan_filtering(struct dsa_switch *ds, int port,
1055 bool vlan_filtering,
1056 struct switchdev_trans *trans)
1057 {
1058 struct rtl838x_switch_priv *priv = ds->priv;
1059
1060 pr_debug("%s: port %d\n", __func__, port);
1061 mutex_lock(&priv->reg_mutex);
1062
1063 if (vlan_filtering) {
1064 /* Enable ingress and egress filtering
1065 * The VLAN_PORT_IGR_FILTER register uses 2 bits for each port to define
1066 * the filter action:
1067 * 0: Always Forward
1068 * 1: Drop packet
1069 * 2: Trap packet to CPU port
1070 * The Egress filter used 1 bit per state (0: DISABLED, 1: ENABLED)
1071 */
1072 if (port != priv->cpu_port)
1073 sw_w32_mask(0b10 << ((port % 16) << 1), 0b01 << ((port % 16) << 1),
1074 priv->r->vlan_port_igr_filter + ((port >> 4) << 2));
1075 sw_w32_mask(0, BIT(port % 32), priv->r->vlan_port_egr_filter + ((port >> 5) << 2));
1076 } else {
1077 /* Disable ingress and egress filtering */
1078 if (port != priv->cpu_port)
1079 sw_w32_mask(0b11 << ((port % 16) << 1), 0,
1080 priv->r->vlan_port_igr_filter + ((port >> 4) << 2));
1081 sw_w32_mask(BIT(port % 32), 0, priv->r->vlan_port_egr_filter + ((port >> 5) << 2));
1082 }
1083
1084 /* Do we need to do something to the CPU-Port, too? */
1085 mutex_unlock(&priv->reg_mutex);
1086
1087 return 0;
1088 }
1089
1090 static int rtl83xx_vlan_prepare(struct dsa_switch *ds, int port,
1091 const struct switchdev_obj_port_vlan *vlan)
1092 {
1093 struct rtl838x_vlan_info info;
1094 struct rtl838x_switch_priv *priv = ds->priv;
1095
1096 priv->r->vlan_tables_read(0, &info);
1097
1098 pr_debug("VLAN 0: Tagged ports %llx, untag %llx, profile %d, MC# %d, UC# %d, FID %x\n",
1099 info.tagged_ports, info.untagged_ports, info.profile_id,
1100 info.hash_mc_fid, info.hash_uc_fid, info.fid);
1101
1102 priv->r->vlan_tables_read(1, &info);
1103 pr_debug("VLAN 1: Tagged ports %llx, untag %llx, profile %d, MC# %d, UC# %d, FID %x\n",
1104 info.tagged_ports, info.untagged_ports, info.profile_id,
1105 info.hash_mc_fid, info.hash_uc_fid, info.fid);
1106 priv->r->vlan_set_untagged(1, info.untagged_ports);
1107 pr_debug("SET: Untagged ports, VLAN %d: %llx\n", 1, info.untagged_ports);
1108
1109 priv->r->vlan_set_tagged(1, &info);
1110 pr_debug("SET: Tagged ports, VLAN %d: %llx\n", 1, info.tagged_ports);
1111
1112 mutex_unlock(&priv->reg_mutex);
1113 return 0;
1114 }
1115
1116 static void rtl83xx_vlan_add(struct dsa_switch *ds, int port,
1117 const struct switchdev_obj_port_vlan *vlan)
1118 {
1119 struct rtl838x_vlan_info info;
1120 struct rtl838x_switch_priv *priv = ds->priv;
1121 int v;
1122
1123 pr_debug("%s port %d, vid_end %d, vid_end %d, flags %x\n", __func__,
1124 port, vlan->vid_begin, vlan->vid_end, vlan->flags);
1125
1126 if (vlan->vid_begin > 4095 || vlan->vid_end > 4095) {
1127 dev_err(priv->dev, "VLAN out of range: %d - %d",
1128 vlan->vid_begin, vlan->vid_end);
1129 return;
1130 }
1131
1132 mutex_lock(&priv->reg_mutex);
1133
1134 if (vlan->flags & BRIDGE_VLAN_INFO_PVID) {
1135 for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
1136 if (!v)
1137 continue;
1138 /* Set both inner and outer PVID of the port */
1139 sw_w32((v << 16) | v << 2, priv->r->vlan_port_pb + (port << 2));
1140 priv->ports[port].pvid = vlan->vid_end;
1141 }
1142 }
1143
1144 for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
1145 /* Get port memberships of this vlan */
1146 priv->r->vlan_tables_read(v, &info);
1147
1148 /* new VLAN? */
1149 if (!info.tagged_ports) {
1150 info.fid = 0;
1151 info.hash_mc_fid = false;
1152 info.hash_uc_fid = false;
1153 info.profile_id = 0;
1154 }
1155
1156 /* sanitize untagged_ports - must be a subset */
1157 if (info.untagged_ports & ~info.tagged_ports)
1158 info.untagged_ports = 0;
1159
1160 info.tagged_ports |= BIT_ULL(port);
1161 if (vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED)
1162 info.untagged_ports |= BIT_ULL(port);
1163
1164 priv->r->vlan_set_untagged(v, info.untagged_ports);
1165 pr_debug("Untagged ports, VLAN %d: %llx\n", v, info.untagged_ports);
1166
1167 priv->r->vlan_set_tagged(v, &info);
1168 pr_debug("Tagged ports, VLAN %d: %llx\n", v, info.tagged_ports);
1169 }
1170
1171 mutex_unlock(&priv->reg_mutex);
1172 }
1173
1174 static int rtl83xx_vlan_del(struct dsa_switch *ds, int port,
1175 const struct switchdev_obj_port_vlan *vlan)
1176 {
1177 struct rtl838x_vlan_info info;
1178 struct rtl838x_switch_priv *priv = ds->priv;
1179 int v;
1180 u16 pvid;
1181
1182 pr_debug("%s: port %d, vid_end %d, vid_end %d, flags %x\n", __func__,
1183 port, vlan->vid_begin, vlan->vid_end, vlan->flags);
1184
1185 if (vlan->vid_begin > 4095 || vlan->vid_end > 4095) {
1186 dev_err(priv->dev, "VLAN out of range: %d - %d",
1187 vlan->vid_begin, vlan->vid_end);
1188 return -ENOTSUPP;
1189 }
1190
1191 mutex_lock(&priv->reg_mutex);
1192 pvid = priv->ports[port].pvid;
1193
1194 for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
1195 /* Reset to default if removing the current PVID */
1196 if (v == pvid)
1197 sw_w32(0, priv->r->vlan_port_pb + (port << 2));
1198
1199 /* Get port memberships of this vlan */
1200 priv->r->vlan_tables_read(v, &info);
1201
1202 /* remove port from both tables */
1203 info.untagged_ports &= (~BIT_ULL(port));
1204 info.tagged_ports &= (~BIT_ULL(port));
1205
1206 priv->r->vlan_set_untagged(v, info.untagged_ports);
1207 pr_debug("Untagged ports, VLAN %d: %llx\n", v, info.untagged_ports);
1208
1209 priv->r->vlan_set_tagged(v, &info);
1210 pr_debug("Tagged ports, VLAN %d: %llx\n", v, info.tagged_ports);
1211 }
1212 mutex_unlock(&priv->reg_mutex);
1213
1214 return 0;
1215 }
1216
1217 static void dump_l2_entry(struct rtl838x_l2_entry *e)
1218 {
1219 pr_info("MAC: %02x:%02x:%02x:%02x:%02x:%02x vid: %d, rvid: %d, port: %d, valid: %d\n",
1220 e->mac[0], e->mac[1], e->mac[2], e->mac[3], e->mac[4], e->mac[5],
1221 e->vid, e->rvid, e->port, e->valid);
1222
1223 if (e->type != L2_MULTICAST) {
1224 pr_info("Type: %d, is_static: %d, is_ip_mc: %d, is_ipv6_mc: %d, block_da: %d\n",
1225 e->type, e->is_static, e->is_ip_mc, e->is_ipv6_mc, e->block_da);
1226 pr_info(" block_sa: %d, susp: %d, nh: %d, age: %d, is_trunk: %d, trunk: %d\n",
1227 e->block_sa, e->suspended, e->next_hop, e->age, e->is_trunk, e->trunk);
1228 }
1229 if (e->type == L2_MULTICAST)
1230 pr_info(" L2_MULTICAST mc_portmask_index: %d\n", e->mc_portmask_index);
1231 if (e->is_ip_mc || e->is_ipv6_mc)
1232 pr_info(" mc_portmask_index: %d, mc_gip: %d, mc_sip: %d\n",
1233 e->mc_portmask_index, e->mc_gip, e->mc_sip);
1234 pr_info(" stack_dev: %d\n", e->stack_dev);
1235 if (e->next_hop)
1236 pr_info(" nh_route_id: %d\n", e->nh_route_id);
1237 }
1238
1239 static void rtl83xx_setup_l2_uc_entry(struct rtl838x_l2_entry *e, int port, int vid, u64 mac)
1240 {
1241 e->is_ip_mc = e->is_ipv6_mc = false;
1242 e->valid = true;
1243 e->age = 3;
1244 e->port = port,
1245 e->vid = vid;
1246 u64_to_ether_addr(mac, e->mac);
1247 }
1248
1249 static void rtl83xx_setup_l2_mc_entry(struct rtl838x_switch_priv *priv,
1250 struct rtl838x_l2_entry *e, int vid, u64 mac, int mc_group)
1251 {
1252 e->is_ip_mc = e->is_ipv6_mc = false;
1253 e->valid = true;
1254 e->mc_portmask_index = mc_group;
1255 e->type = L2_MULTICAST;
1256 e->rvid = e->vid = vid;
1257 pr_debug("%s: vid: %d, rvid: %d\n", __func__, e->vid, e->rvid);
1258 u64_to_ether_addr(mac, e->mac);
1259 }
1260
1261 /*
1262 * Uses the seed to identify a hash bucket in the L2 using the derived hash key and then loops
1263 * over the entries in the bucket until either a matching entry is found or an empty slot
1264 * Returns the filled in rtl838x_l2_entry and the index in the bucket when an entry was found
1265 * when an empty slot was found and must exist is false, the index of the slot is returned
1266 * when no slots are available returns -1
1267 */
1268 static int rtl83xx_find_l2_hash_entry(struct rtl838x_switch_priv *priv, u64 seed,
1269 bool must_exist, struct rtl838x_l2_entry *e)
1270 {
1271 int i, idx = -1;
1272 u32 key = priv->r->l2_hash_key(priv, seed);
1273 u64 entry;
1274
1275 pr_debug("%s: using key %x, for seed %016llx\n", __func__, key, seed);
1276 // Loop over all entries in the hash-bucket and over the second block on 93xx SoCs
1277 for (i = 0; i < priv->l2_bucket_size; i++) {
1278 entry = priv->r->read_l2_entry_using_hash(key, i, e);
1279 pr_debug("valid %d, mac %016llx\n", e->valid, ether_addr_to_u64(&e->mac[0]));
1280 if (must_exist && !e->valid)
1281 continue;
1282 if (!e->valid || ((entry & 0x0fffffffffffffffULL) == seed)) {
1283 idx = i > 3 ? ((key >> 14) & 0xffff) | i >> 1 : ((key << 2) | i) & 0xffff;
1284 break;
1285 }
1286 }
1287
1288 return idx;
1289 }
1290
1291 /*
1292 * Uses the seed to identify an entry in the CAM by looping over all its entries
1293 * Returns the filled in rtl838x_l2_entry and the index in the CAM when an entry was found
1294 * when an empty slot was found the index of the slot is returned
1295 * when no slots are available returns -1
1296 */
1297 static int rtl83xx_find_l2_cam_entry(struct rtl838x_switch_priv *priv, u64 seed,
1298 bool must_exist, struct rtl838x_l2_entry *e)
1299 {
1300 int i, idx = -1;
1301 u64 entry;
1302
1303 for (i = 0; i < 64; i++) {
1304 entry = priv->r->read_cam(i, e);
1305 if (!must_exist && !e->valid) {
1306 if (idx < 0) /* First empty entry? */
1307 idx = i;
1308 break;
1309 } else if ((entry & 0x0fffffffffffffffULL) == seed) {
1310 pr_debug("Found entry in CAM\n");
1311 idx = i;
1312 break;
1313 }
1314 }
1315 return idx;
1316 }
1317
1318 static int rtl83xx_port_fdb_add(struct dsa_switch *ds, int port,
1319 const unsigned char *addr, u16 vid)
1320 {
1321 struct rtl838x_switch_priv *priv = ds->priv;
1322 u64 mac = ether_addr_to_u64(addr);
1323 struct rtl838x_l2_entry e;
1324 int err = 0, idx;
1325 u64 seed = priv->r->l2_hash_seed(mac, vid);
1326
1327 mutex_lock(&priv->reg_mutex);
1328
1329 idx = rtl83xx_find_l2_hash_entry(priv, seed, false, &e);
1330
1331 // Found an existing or empty entry
1332 if (idx >= 0) {
1333 rtl83xx_setup_l2_uc_entry(&e, port, vid, mac);
1334 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1335 goto out;
1336 }
1337
1338 // Hash buckets full, try CAM
1339 rtl83xx_find_l2_cam_entry(priv, seed, false, &e);
1340
1341 if (idx >= 0) {
1342 rtl83xx_setup_l2_uc_entry(&e, port, vid, mac);
1343 priv->r->write_cam(idx, &e);
1344 goto out;
1345 }
1346
1347 err = -ENOTSUPP;
1348 out:
1349 mutex_unlock(&priv->reg_mutex);
1350 return err;
1351 }
1352
1353 static int rtl83xx_port_fdb_del(struct dsa_switch *ds, int port,
1354 const unsigned char *addr, u16 vid)
1355 {
1356 struct rtl838x_switch_priv *priv = ds->priv;
1357 u64 mac = ether_addr_to_u64(addr);
1358 struct rtl838x_l2_entry e;
1359 int err = 0, idx;
1360 u64 seed = priv->r->l2_hash_seed(mac, vid);
1361
1362 pr_info("In %s, mac %llx, vid: %d\n", __func__, mac, vid);
1363 mutex_lock(&priv->reg_mutex);
1364
1365 idx = rtl83xx_find_l2_hash_entry(priv, seed, true, &e);
1366
1367 pr_info("Found entry index %d, key %d and bucket %d\n", idx, idx >> 2, idx & 3);
1368 if (idx >= 0) {
1369 e.valid = false;
1370 dump_l2_entry(&e);
1371 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1372 goto out;
1373 }
1374
1375 /* Check CAM for spillover from hash buckets */
1376 rtl83xx_find_l2_cam_entry(priv, seed, true, &e);
1377
1378 if (idx >= 0) {
1379 e.valid = false;
1380 priv->r->write_cam(idx, &e);
1381 goto out;
1382 }
1383 err = -ENOENT;
1384 out:
1385 mutex_unlock(&priv->reg_mutex);
1386 return err;
1387 }
1388
1389 static int rtl83xx_port_fdb_dump(struct dsa_switch *ds, int port,
1390 dsa_fdb_dump_cb_t *cb, void *data)
1391 {
1392 struct rtl838x_l2_entry e;
1393 struct rtl838x_switch_priv *priv = ds->priv;
1394 int i;
1395 u32 fid, pkey;
1396 u64 mac;
1397
1398 mutex_lock(&priv->reg_mutex);
1399
1400 for (i = 0; i < priv->fib_entries; i++) {
1401 priv->r->read_l2_entry_using_hash(i >> 2, i & 0x3, &e);
1402
1403 if (!e.valid)
1404 continue;
1405
1406 if (e.port == port || e.port == RTL930X_PORT_IGNORE) {
1407 u64 seed;
1408 u32 key;
1409
1410 fid = ((i >> 2) & 0x3ff) | (e.rvid & ~0x3ff);
1411 mac = ether_addr_to_u64(&e.mac[0]);
1412 pkey = priv->r->l2_hash_key(priv, priv->r->l2_hash_seed(mac, fid));
1413 fid = (pkey & 0x3ff) | (fid & ~0x3ff);
1414 pr_info("-> index %d, key %x, bucket %d, dmac %016llx, fid: %x rvid: %x\n",
1415 i, i >> 2, i & 0x3, mac, fid, e.rvid);
1416 dump_l2_entry(&e);
1417 seed = priv->r->l2_hash_seed(mac, e.rvid);
1418 key = priv->r->l2_hash_key(priv, seed);
1419 pr_info("seed: %016llx, key based on rvid: %08x\n", seed, key);
1420 cb(e.mac, e.vid, e.is_static, data);
1421 }
1422 if (e.type == L2_MULTICAST) {
1423 u64 portmask = priv->r->read_mcast_pmask(e.mc_portmask_index);
1424
1425 if (portmask & BIT_ULL(port)) {
1426 dump_l2_entry(&e);
1427 pr_info(" PM: %016llx\n", portmask);
1428 }
1429 }
1430 }
1431
1432 for (i = 0; i < 64; i++) {
1433 priv->r->read_cam(i, &e);
1434
1435 if (!e.valid)
1436 continue;
1437
1438 if (e.port == port)
1439 cb(e.mac, e.vid, e.is_static, data);
1440 }
1441
1442 mutex_unlock(&priv->reg_mutex);
1443 return 0;
1444 }
1445
1446 static int rtl83xx_port_mdb_prepare(struct dsa_switch *ds, int port,
1447 const struct switchdev_obj_port_mdb *mdb)
1448 {
1449 struct rtl838x_switch_priv *priv = ds->priv;
1450
1451 if (priv->id >= 0x9300)
1452 return -EOPNOTSUPP;
1453
1454 return 0;
1455 }
1456
1457 static int rtl83xx_mc_group_alloc(struct rtl838x_switch_priv *priv, int port)
1458 {
1459 int mc_group = find_first_zero_bit(priv->mc_group_bm, MAX_MC_GROUPS - 1);
1460 u64 portmask;
1461
1462 if (mc_group >= MAX_MC_GROUPS - 1)
1463 return -1;
1464
1465 pr_debug("Using MC group %d\n", mc_group);
1466 set_bit(mc_group, priv->mc_group_bm);
1467 mc_group++; // We cannot use group 0, as this is used for lookup miss flooding
1468 portmask = BIT_ULL(port);
1469 priv->r->write_mcast_pmask(mc_group, portmask);
1470
1471 return mc_group;
1472 }
1473
1474 static u64 rtl83xx_mc_group_add_port(struct rtl838x_switch_priv *priv, int mc_group, int port)
1475 {
1476 u64 portmask = priv->r->read_mcast_pmask(mc_group);
1477
1478 portmask |= BIT_ULL(port);
1479 priv->r->write_mcast_pmask(mc_group, portmask);
1480
1481 return portmask;
1482 }
1483
1484 static u64 rtl83xx_mc_group_del_port(struct rtl838x_switch_priv *priv, int mc_group, int port)
1485 {
1486 u64 portmask = priv->r->read_mcast_pmask(mc_group);
1487
1488 portmask &= ~BIT_ULL(port);
1489 priv->r->write_mcast_pmask(mc_group, portmask);
1490 if (!portmask)
1491 clear_bit(mc_group, priv->mc_group_bm);
1492
1493 return portmask;
1494 }
1495
1496 static void rtl83xx_port_mdb_add(struct dsa_switch *ds, int port,
1497 const struct switchdev_obj_port_mdb *mdb)
1498 {
1499 struct rtl838x_switch_priv *priv = ds->priv;
1500 u64 mac = ether_addr_to_u64(mdb->addr);
1501 struct rtl838x_l2_entry e;
1502 int err = 0, idx;
1503 int vid = mdb->vid;
1504 u64 seed = priv->r->l2_hash_seed(mac, vid);
1505 int mc_group;
1506
1507 pr_debug("In %s port %d, mac %llx, vid: %d\n", __func__, port, mac, vid);
1508 mutex_lock(&priv->reg_mutex);
1509
1510 idx = rtl83xx_find_l2_hash_entry(priv, seed, false, &e);
1511
1512 // Found an existing or empty entry
1513 if (idx >= 0) {
1514 if (e.valid) {
1515 pr_debug("Found an existing entry %016llx, mc_group %d\n",
1516 ether_addr_to_u64(e.mac), e.mc_portmask_index);
1517 rtl83xx_mc_group_add_port(priv, e.mc_portmask_index, port);
1518 } else {
1519 pr_debug("New entry for seed %016llx\n", seed);
1520 mc_group = rtl83xx_mc_group_alloc(priv, port);
1521 if (mc_group < 0) {
1522 err = -ENOTSUPP;
1523 goto out;
1524 }
1525 rtl83xx_setup_l2_mc_entry(priv, &e, vid, mac, mc_group);
1526 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1527 }
1528 goto out;
1529 }
1530
1531 // Hash buckets full, try CAM
1532 rtl83xx_find_l2_cam_entry(priv, seed, false, &e);
1533
1534 if (idx >= 0) {
1535 if (e.valid) {
1536 pr_debug("Found existing CAM entry %016llx, mc_group %d\n",
1537 ether_addr_to_u64(e.mac), e.mc_portmask_index);
1538 rtl83xx_mc_group_add_port(priv, e.mc_portmask_index, port);
1539 } else {
1540 pr_debug("New entry\n");
1541 mc_group = rtl83xx_mc_group_alloc(priv, port);
1542 if (mc_group < 0) {
1543 err = -ENOTSUPP;
1544 goto out;
1545 }
1546 rtl83xx_setup_l2_mc_entry(priv, &e, vid, mac, mc_group);
1547 priv->r->write_cam(idx, &e);
1548 }
1549 goto out;
1550 }
1551
1552 err = -ENOTSUPP;
1553 out:
1554 mutex_unlock(&priv->reg_mutex);
1555 if (err)
1556 dev_err(ds->dev, "failed to add MDB entry\n");
1557 }
1558
1559 int rtl83xx_port_mdb_del(struct dsa_switch *ds, int port,
1560 const struct switchdev_obj_port_mdb *mdb)
1561 {
1562 struct rtl838x_switch_priv *priv = ds->priv;
1563 u64 mac = ether_addr_to_u64(mdb->addr);
1564 struct rtl838x_l2_entry e;
1565 int err = 0, idx;
1566 int vid = mdb->vid;
1567 u64 seed = priv->r->l2_hash_seed(mac, vid);
1568 u64 portmask;
1569
1570 pr_debug("In %s, port %d, mac %llx, vid: %d\n", __func__, port, mac, vid);
1571 mutex_lock(&priv->reg_mutex);
1572
1573 idx = rtl83xx_find_l2_hash_entry(priv, seed, true, &e);
1574
1575 pr_debug("Found entry index %d, key %d and bucket %d\n", idx, idx >> 2, idx & 3);
1576 if (idx >= 0) {
1577 portmask = rtl83xx_mc_group_del_port(priv, e.mc_portmask_index, port);
1578 if (!portmask) {
1579 e.valid = false;
1580 // dump_l2_entry(&e);
1581 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1582 }
1583 goto out;
1584 }
1585
1586 /* Check CAM for spillover from hash buckets */
1587 rtl83xx_find_l2_cam_entry(priv, seed, true, &e);
1588
1589 if (idx >= 0) {
1590 portmask = rtl83xx_mc_group_del_port(priv, e.mc_portmask_index, port);
1591 if (!portmask) {
1592 e.valid = false;
1593 // dump_l2_entry(&e);
1594 priv->r->write_cam(idx, &e);
1595 }
1596 goto out;
1597 }
1598 // TODO: Re-enable with a newer kernel: err = -ENOENT;
1599 out:
1600 mutex_unlock(&priv->reg_mutex);
1601 return err;
1602 }
1603
1604 static int rtl83xx_port_mirror_add(struct dsa_switch *ds, int port,
1605 struct dsa_mall_mirror_tc_entry *mirror,
1606 bool ingress)
1607 {
1608 /* We support 4 mirror groups, one destination port per group */
1609 int group;
1610 struct rtl838x_switch_priv *priv = ds->priv;
1611 int ctrl_reg, dpm_reg, spm_reg;
1612
1613 pr_debug("In %s\n", __func__);
1614
1615 for (group = 0; group < 4; group++) {
1616 if (priv->mirror_group_ports[group] == mirror->to_local_port)
1617 break;
1618 }
1619 if (group >= 4) {
1620 for (group = 0; group < 4; group++) {
1621 if (priv->mirror_group_ports[group] < 0)
1622 break;
1623 }
1624 }
1625
1626 if (group >= 4)
1627 return -ENOSPC;
1628
1629 ctrl_reg = priv->r->mir_ctrl + group * 4;
1630 dpm_reg = priv->r->mir_dpm + group * 4 * priv->port_width;
1631 spm_reg = priv->r->mir_spm + group * 4 * priv->port_width;
1632
1633 pr_debug("Using group %d\n", group);
1634 mutex_lock(&priv->reg_mutex);
1635
1636 if (priv->family_id == RTL8380_FAMILY_ID) {
1637 /* Enable mirroring to port across VLANs (bit 11) */
1638 sw_w32(1 << 11 | (mirror->to_local_port << 4) | 1, ctrl_reg);
1639 } else {
1640 /* Enable mirroring to destination port */
1641 sw_w32((mirror->to_local_port << 4) | 1, ctrl_reg);
1642 }
1643
1644 if (ingress && (priv->r->get_port_reg_be(spm_reg) & (1ULL << port))) {
1645 mutex_unlock(&priv->reg_mutex);
1646 return -EEXIST;
1647 }
1648 if ((!ingress) && (priv->r->get_port_reg_be(dpm_reg) & (1ULL << port))) {
1649 mutex_unlock(&priv->reg_mutex);
1650 return -EEXIST;
1651 }
1652
1653 if (ingress)
1654 priv->r->mask_port_reg_be(0, 1ULL << port, spm_reg);
1655 else
1656 priv->r->mask_port_reg_be(0, 1ULL << port, dpm_reg);
1657
1658 priv->mirror_group_ports[group] = mirror->to_local_port;
1659 mutex_unlock(&priv->reg_mutex);
1660 return 0;
1661 }
1662
1663 static void rtl83xx_port_mirror_del(struct dsa_switch *ds, int port,
1664 struct dsa_mall_mirror_tc_entry *mirror)
1665 {
1666 int group = 0;
1667 struct rtl838x_switch_priv *priv = ds->priv;
1668 int ctrl_reg, dpm_reg, spm_reg;
1669
1670 pr_debug("In %s\n", __func__);
1671 for (group = 0; group < 4; group++) {
1672 if (priv->mirror_group_ports[group] == mirror->to_local_port)
1673 break;
1674 }
1675 if (group >= 4)
1676 return;
1677
1678 ctrl_reg = priv->r->mir_ctrl + group * 4;
1679 dpm_reg = priv->r->mir_dpm + group * 4 * priv->port_width;
1680 spm_reg = priv->r->mir_spm + group * 4 * priv->port_width;
1681
1682 mutex_lock(&priv->reg_mutex);
1683 if (mirror->ingress) {
1684 /* Ingress, clear source port matrix */
1685 priv->r->mask_port_reg_be(1ULL << port, 0, spm_reg);
1686 } else {
1687 /* Egress, clear destination port matrix */
1688 priv->r->mask_port_reg_be(1ULL << port, 0, dpm_reg);
1689 }
1690
1691 if (!(sw_r32(spm_reg) || sw_r32(dpm_reg))) {
1692 priv->mirror_group_ports[group] = -1;
1693 sw_w32(0, ctrl_reg);
1694 }
1695
1696 mutex_unlock(&priv->reg_mutex);
1697 }
1698
1699 int dsa_phy_read(struct dsa_switch *ds, int phy_addr, int phy_reg)
1700 {
1701 u32 val;
1702 u32 offset = 0;
1703 struct rtl838x_switch_priv *priv = ds->priv;
1704
1705 if (phy_addr >= 24 && phy_addr <= 27
1706 && priv->ports[24].phy == PHY_RTL838X_SDS) {
1707 if (phy_addr == 26)
1708 offset = 0x100;
1709 val = sw_r32(RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2)) & 0xffff;
1710 return val;
1711 }
1712
1713 read_phy(phy_addr, 0, phy_reg, &val);
1714 return val;
1715 }
1716
1717 int dsa_phy_write(struct dsa_switch *ds, int phy_addr, int phy_reg, u16 val)
1718 {
1719 u32 offset = 0;
1720 struct rtl838x_switch_priv *priv = ds->priv;
1721
1722 if (phy_addr >= 24 && phy_addr <= 27
1723 && priv->ports[24].phy == PHY_RTL838X_SDS) {
1724 if (phy_addr == 26)
1725 offset = 0x100;
1726 sw_w32(val, RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2));
1727 return 0;
1728 }
1729 return write_phy(phy_addr, 0, phy_reg, val);
1730 }
1731
1732 const struct dsa_switch_ops rtl83xx_switch_ops = {
1733 .get_tag_protocol = rtl83xx_get_tag_protocol,
1734 .setup = rtl83xx_setup,
1735
1736 .phy_read = dsa_phy_read,
1737 .phy_write = dsa_phy_write,
1738
1739 .phylink_validate = rtl83xx_phylink_validate,
1740 .phylink_mac_link_state = rtl83xx_phylink_mac_link_state,
1741 .phylink_mac_config = rtl83xx_phylink_mac_config,
1742 .phylink_mac_link_down = rtl83xx_phylink_mac_link_down,
1743 .phylink_mac_link_up = rtl83xx_phylink_mac_link_up,
1744
1745 .get_strings = rtl83xx_get_strings,
1746 .get_ethtool_stats = rtl83xx_get_ethtool_stats,
1747 .get_sset_count = rtl83xx_get_sset_count,
1748
1749 .port_enable = rtl83xx_port_enable,
1750 .port_disable = rtl83xx_port_disable,
1751
1752 .get_mac_eee = rtl83xx_get_mac_eee,
1753 .set_mac_eee = rtl83xx_set_mac_eee,
1754
1755 .set_ageing_time = rtl83xx_set_l2aging,
1756 .port_bridge_join = rtl83xx_port_bridge_join,
1757 .port_bridge_leave = rtl83xx_port_bridge_leave,
1758 .port_stp_state_set = rtl83xx_port_stp_state_set,
1759 .port_fast_age = rtl83xx_fast_age,
1760
1761 .port_vlan_filtering = rtl83xx_vlan_filtering,
1762 .port_vlan_prepare = rtl83xx_vlan_prepare,
1763 .port_vlan_add = rtl83xx_vlan_add,
1764 .port_vlan_del = rtl83xx_vlan_del,
1765
1766 .port_fdb_add = rtl83xx_port_fdb_add,
1767 .port_fdb_del = rtl83xx_port_fdb_del,
1768 .port_fdb_dump = rtl83xx_port_fdb_dump,
1769
1770 .port_mdb_prepare = rtl83xx_port_mdb_prepare,
1771 .port_mdb_add = rtl83xx_port_mdb_add,
1772 .port_mdb_del = rtl83xx_port_mdb_del,
1773
1774 .port_mirror_add = rtl83xx_port_mirror_add,
1775 .port_mirror_del = rtl83xx_port_mirror_del,
1776 };
1777
1778 const struct dsa_switch_ops rtl930x_switch_ops = {
1779 .get_tag_protocol = rtl83xx_get_tag_protocol,
1780 .setup = rtl930x_setup,
1781
1782 .phy_read = dsa_phy_read,
1783 .phy_write = dsa_phy_write,
1784
1785 .phylink_validate = rtl93xx_phylink_validate,
1786 .phylink_mac_link_state = rtl93xx_phylink_mac_link_state,
1787 .phylink_mac_config = rtl93xx_phylink_mac_config,
1788 .phylink_mac_link_down = rtl93xx_phylink_mac_link_down,
1789 .phylink_mac_link_up = rtl93xx_phylink_mac_link_up,
1790
1791 .get_strings = rtl83xx_get_strings,
1792 .get_ethtool_stats = rtl83xx_get_ethtool_stats,
1793 .get_sset_count = rtl83xx_get_sset_count,
1794
1795 .port_enable = rtl83xx_port_enable,
1796 .port_disable = rtl83xx_port_disable,
1797
1798 .get_mac_eee = rtl93xx_get_mac_eee,
1799 .set_mac_eee = rtl83xx_set_mac_eee,
1800
1801 .set_ageing_time = rtl83xx_set_l2aging,
1802 .port_bridge_join = rtl83xx_port_bridge_join,
1803 .port_bridge_leave = rtl83xx_port_bridge_leave,
1804 .port_stp_state_set = rtl83xx_port_stp_state_set,
1805 .port_fast_age = rtl930x_fast_age,
1806
1807 .port_vlan_filtering = rtl83xx_vlan_filtering,
1808 .port_vlan_prepare = rtl83xx_vlan_prepare,
1809 .port_vlan_add = rtl83xx_vlan_add,
1810 .port_vlan_del = rtl83xx_vlan_del,
1811
1812 .port_fdb_add = rtl83xx_port_fdb_add,
1813 .port_fdb_del = rtl83xx_port_fdb_del,
1814 .port_fdb_dump = rtl83xx_port_fdb_dump,
1815
1816 .port_mdb_prepare = rtl83xx_port_mdb_prepare,
1817 .port_mdb_add = rtl83xx_port_mdb_add,
1818 .port_mdb_del = rtl83xx_port_mdb_del,
1819
1820 };
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