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realtek: Fix link status detection on RTL9302 for SFP modules
[openwrt/staging/ldir.git] / target / linux / realtek / files-5.10 / drivers / net / dsa / rtl83xx / dsa.c
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <net/dsa.h>
4 #include <linux/if_bridge.h>
5
6 #include <asm/mach-rtl838x/mach-rtl83xx.h>
7 #include "rtl83xx.h"
8
9
10 extern struct rtl83xx_soc_info soc_info;
11
12
13 static void rtl83xx_init_stats(struct rtl838x_switch_priv *priv)
14 {
15 mutex_lock(&priv->reg_mutex);
16
17 /* Enable statistics module: all counters plus debug.
18 * On RTL839x all counters are enabled by default
19 */
20 if (priv->family_id == RTL8380_FAMILY_ID)
21 sw_w32_mask(0, 3, RTL838X_STAT_CTRL);
22
23 /* Reset statistics counters */
24 sw_w32_mask(0, 1, priv->r->stat_rst);
25
26 mutex_unlock(&priv->reg_mutex);
27 }
28
29 static void rtl83xx_enable_phy_polling(struct rtl838x_switch_priv *priv)
30 {
31 int i;
32 u64 v = 0;
33
34 msleep(1000);
35 /* Enable all ports with a PHY, including the SFP-ports */
36 for (i = 0; i < priv->cpu_port; i++) {
37 if (priv->ports[i].phy)
38 v |= BIT_ULL(i);
39 }
40
41 pr_info("%s: %16llx\n", __func__, v);
42 priv->r->set_port_reg_le(v, priv->r->smi_poll_ctrl);
43
44 /* PHY update complete, there is no global PHY polling enable bit on the 9300 */
45 if (priv->family_id == RTL8390_FAMILY_ID)
46 sw_w32_mask(0, BIT(7), RTL839X_SMI_GLB_CTRL);
47 else if(priv->family_id == RTL9300_FAMILY_ID)
48 sw_w32_mask(0, 0x8000, RTL838X_SMI_GLB_CTRL);
49 }
50
51 const struct rtl83xx_mib_desc rtl83xx_mib[] = {
52 MIB_DESC(2, 0xf8, "ifInOctets"),
53 MIB_DESC(2, 0xf0, "ifOutOctets"),
54 MIB_DESC(1, 0xec, "dot1dTpPortInDiscards"),
55 MIB_DESC(1, 0xe8, "ifInUcastPkts"),
56 MIB_DESC(1, 0xe4, "ifInMulticastPkts"),
57 MIB_DESC(1, 0xe0, "ifInBroadcastPkts"),
58 MIB_DESC(1, 0xdc, "ifOutUcastPkts"),
59 MIB_DESC(1, 0xd8, "ifOutMulticastPkts"),
60 MIB_DESC(1, 0xd4, "ifOutBroadcastPkts"),
61 MIB_DESC(1, 0xd0, "ifOutDiscards"),
62 MIB_DESC(1, 0xcc, ".3SingleCollisionFrames"),
63 MIB_DESC(1, 0xc8, ".3MultipleCollisionFrames"),
64 MIB_DESC(1, 0xc4, ".3DeferredTransmissions"),
65 MIB_DESC(1, 0xc0, ".3LateCollisions"),
66 MIB_DESC(1, 0xbc, ".3ExcessiveCollisions"),
67 MIB_DESC(1, 0xb8, ".3SymbolErrors"),
68 MIB_DESC(1, 0xb4, ".3ControlInUnknownOpcodes"),
69 MIB_DESC(1, 0xb0, ".3InPauseFrames"),
70 MIB_DESC(1, 0xac, ".3OutPauseFrames"),
71 MIB_DESC(1, 0xa8, "DropEvents"),
72 MIB_DESC(1, 0xa4, "tx_BroadcastPkts"),
73 MIB_DESC(1, 0xa0, "tx_MulticastPkts"),
74 MIB_DESC(1, 0x9c, "CRCAlignErrors"),
75 MIB_DESC(1, 0x98, "tx_UndersizePkts"),
76 MIB_DESC(1, 0x94, "rx_UndersizePkts"),
77 MIB_DESC(1, 0x90, "rx_UndersizedropPkts"),
78 MIB_DESC(1, 0x8c, "tx_OversizePkts"),
79 MIB_DESC(1, 0x88, "rx_OversizePkts"),
80 MIB_DESC(1, 0x84, "Fragments"),
81 MIB_DESC(1, 0x80, "Jabbers"),
82 MIB_DESC(1, 0x7c, "Collisions"),
83 MIB_DESC(1, 0x78, "tx_Pkts64Octets"),
84 MIB_DESC(1, 0x74, "rx_Pkts64Octets"),
85 MIB_DESC(1, 0x70, "tx_Pkts65to127Octets"),
86 MIB_DESC(1, 0x6c, "rx_Pkts65to127Octets"),
87 MIB_DESC(1, 0x68, "tx_Pkts128to255Octets"),
88 MIB_DESC(1, 0x64, "rx_Pkts128to255Octets"),
89 MIB_DESC(1, 0x60, "tx_Pkts256to511Octets"),
90 MIB_DESC(1, 0x5c, "rx_Pkts256to511Octets"),
91 MIB_DESC(1, 0x58, "tx_Pkts512to1023Octets"),
92 MIB_DESC(1, 0x54, "rx_Pkts512to1023Octets"),
93 MIB_DESC(1, 0x50, "tx_Pkts1024to1518Octets"),
94 MIB_DESC(1, 0x4c, "rx_StatsPkts1024to1518Octets"),
95 MIB_DESC(1, 0x48, "tx_Pkts1519toMaxOctets"),
96 MIB_DESC(1, 0x44, "rx_Pkts1519toMaxOctets"),
97 MIB_DESC(1, 0x40, "rxMacDiscards")
98 };
99
100
101 /* DSA callbacks */
102
103
104 static enum dsa_tag_protocol rtl83xx_get_tag_protocol(struct dsa_switch *ds,
105 int port,
106 enum dsa_tag_protocol mprot)
107 {
108 /* The switch does not tag the frames, instead internally the header
109 * structure for each packet is tagged accordingly.
110 */
111 return DSA_TAG_PROTO_TRAILER;
112 }
113
114 /*
115 * Initialize all VLANS
116 */
117 static void rtl83xx_vlan_setup(struct rtl838x_switch_priv *priv)
118 {
119 struct rtl838x_vlan_info info;
120 int i;
121
122 pr_info("In %s\n", __func__);
123
124 priv->r->vlan_profile_setup(0);
125 priv->r->vlan_profile_setup(1);
126 pr_info("UNKNOWN_MC_PMASK: %016llx\n", priv->r->read_mcast_pmask(UNKNOWN_MC_PMASK));
127 priv->r->vlan_profile_dump(0);
128
129 info.fid = 0; // Default Forwarding ID / MSTI
130 info.hash_uc_fid = false; // Do not build the L2 lookup hash with FID, but VID
131 info.hash_mc_fid = false; // Do the same for Multicast packets
132 info.profile_id = 0; // Use default Vlan Profile 0
133 info.tagged_ports = 0; // Initially no port members
134 if (priv->family_id == RTL9310_FAMILY_ID) {
135 info.if_id = 0;
136 info.multicast_grp_mask = 0;
137 info.l2_tunnel_list_id = -1;
138 }
139
140 // Initialize all vlans 0-4095
141 for (i = 0; i < MAX_VLANS; i ++)
142 priv->r->vlan_set_tagged(i, &info);
143
144 // reset PVIDs; defaults to 1 on reset
145 for (i = 0; i <= priv->ds->num_ports; i++) {
146 priv->r->vlan_port_pvid_set(i, PBVLAN_TYPE_INNER, 0);
147 priv->r->vlan_port_pvid_set(i, PBVLAN_TYPE_OUTER, 0);
148 priv->r->vlan_port_pvidmode_set(i, PBVLAN_TYPE_INNER, PBVLAN_MODE_UNTAG_AND_PRITAG);
149 priv->r->vlan_port_pvidmode_set(i, PBVLAN_TYPE_OUTER, PBVLAN_MODE_UNTAG_AND_PRITAG);
150 }
151
152 // Set forwarding action based on inner VLAN tag
153 for (i = 0; i < priv->cpu_port; i++)
154 priv->r->vlan_fwd_on_inner(i, true);
155 }
156
157 static void rtl83xx_setup_bpdu_traps(struct rtl838x_switch_priv *priv)
158 {
159 int i;
160
161 for (i = 0; i < priv->cpu_port; i++)
162 priv->r->set_receive_management_action(i, BPDU, COPY2CPU);
163 }
164
165 static int rtl83xx_setup(struct dsa_switch *ds)
166 {
167 int i;
168 struct rtl838x_switch_priv *priv = ds->priv;
169 u64 port_bitmap = BIT_ULL(priv->cpu_port);
170
171 pr_debug("%s called\n", __func__);
172
173 /* Disable MAC polling the PHY so that we can start configuration */
174 priv->r->set_port_reg_le(0ULL, priv->r->smi_poll_ctrl);
175
176 for (i = 0; i < ds->num_ports; i++)
177 priv->ports[i].enable = false;
178 priv->ports[priv->cpu_port].enable = true;
179
180 /* Isolate ports from each other: traffic only CPU <-> port */
181 /* Setting bit j in register RTL838X_PORT_ISO_CTRL(i) allows
182 * traffic from source port i to destination port j
183 */
184 for (i = 0; i < priv->cpu_port; i++) {
185 if (priv->ports[i].phy) {
186 priv->r->set_port_reg_be(BIT_ULL(priv->cpu_port) | BIT_ULL(i),
187 priv->r->port_iso_ctrl(i));
188 port_bitmap |= BIT_ULL(i);
189 }
190 }
191 priv->r->set_port_reg_be(port_bitmap, priv->r->port_iso_ctrl(priv->cpu_port));
192
193 if (priv->family_id == RTL8380_FAMILY_ID)
194 rtl838x_print_matrix();
195 else
196 rtl839x_print_matrix();
197
198 rtl83xx_init_stats(priv);
199
200 rtl83xx_vlan_setup(priv);
201
202 rtl83xx_setup_bpdu_traps(priv);
203
204 ds->configure_vlan_while_not_filtering = true;
205
206 priv->r->l2_learning_setup();
207
208 /* Enable MAC Polling PHY again */
209 rtl83xx_enable_phy_polling(priv);
210 pr_debug("Please wait until PHY is settled\n");
211 msleep(1000);
212 priv->r->pie_init(priv);
213
214 return 0;
215 }
216
217 static int rtl93xx_setup(struct dsa_switch *ds)
218 {
219 int i;
220 struct rtl838x_switch_priv *priv = ds->priv;
221 u32 port_bitmap = BIT(priv->cpu_port);
222
223 pr_info("%s called\n", __func__);
224
225 /* Disable MAC polling the PHY so that we can start configuration */
226 if (priv->family_id == RTL9300_FAMILY_ID)
227 sw_w32(0, RTL930X_SMI_POLL_CTRL);
228
229 if (priv->family_id == RTL9310_FAMILY_ID) {
230 sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL);
231 sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL + 4);
232 }
233
234 // Disable all ports except CPU port
235 for (i = 0; i < ds->num_ports; i++)
236 priv->ports[i].enable = false;
237 priv->ports[priv->cpu_port].enable = true;
238
239 for (i = 0; i < priv->cpu_port; i++) {
240 if (priv->ports[i].phy) {
241 priv->r->traffic_set(i, BIT_ULL(priv->cpu_port) | BIT_ULL(i));
242 port_bitmap |= BIT_ULL(i);
243 }
244 }
245 priv->r->traffic_set(priv->cpu_port, port_bitmap);
246
247 rtl930x_print_matrix();
248
249 // TODO: Initialize statistics
250
251 rtl83xx_vlan_setup(priv);
252
253 ds->configure_vlan_while_not_filtering = true;
254
255 priv->r->l2_learning_setup();
256
257 rtl83xx_enable_phy_polling(priv);
258
259 priv->r->pie_init(priv);
260
261 return 0;
262 }
263
264 static int rtl93xx_get_sds(struct phy_device *phydev)
265 {
266 struct device *dev = &phydev->mdio.dev;
267 struct device_node *dn;
268 u32 sds_num;
269
270 if (!dev)
271 return -1;
272 if (dev->of_node) {
273 dn = dev->of_node;
274 if (of_property_read_u32(dn, "sds", &sds_num))
275 sds_num = -1;
276 } else {
277 dev_err(dev, "No DT node.\n");
278 return -1;
279 }
280
281 return sds_num;
282 }
283
284 static void rtl83xx_phylink_validate(struct dsa_switch *ds, int port,
285 unsigned long *supported,
286 struct phylink_link_state *state)
287 {
288 struct rtl838x_switch_priv *priv = ds->priv;
289 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
290
291 pr_debug("In %s port %d, state is %d", __func__, port, state->interface);
292
293 if (!phy_interface_mode_is_rgmii(state->interface) &&
294 state->interface != PHY_INTERFACE_MODE_NA &&
295 state->interface != PHY_INTERFACE_MODE_1000BASEX &&
296 state->interface != PHY_INTERFACE_MODE_MII &&
297 state->interface != PHY_INTERFACE_MODE_REVMII &&
298 state->interface != PHY_INTERFACE_MODE_GMII &&
299 state->interface != PHY_INTERFACE_MODE_QSGMII &&
300 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
301 state->interface != PHY_INTERFACE_MODE_SGMII) {
302 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
303 dev_err(ds->dev,
304 "Unsupported interface: %d for port %d\n",
305 state->interface, port);
306 return;
307 }
308
309 /* Allow all the expected bits */
310 phylink_set(mask, Autoneg);
311 phylink_set_port_modes(mask);
312 phylink_set(mask, Pause);
313 phylink_set(mask, Asym_Pause);
314
315 /* With the exclusion of MII and Reverse MII, we support Gigabit,
316 * including Half duplex
317 */
318 if (state->interface != PHY_INTERFACE_MODE_MII &&
319 state->interface != PHY_INTERFACE_MODE_REVMII) {
320 phylink_set(mask, 1000baseT_Full);
321 phylink_set(mask, 1000baseT_Half);
322 }
323
324 /* On both the 8380 and 8382, ports 24-27 are SFP ports */
325 if (port >= 24 && port <= 27 && priv->family_id == RTL8380_FAMILY_ID)
326 phylink_set(mask, 1000baseX_Full);
327
328 /* On the RTL839x family of SoCs, ports 48 to 51 are SFP ports */
329 if (port >= 48 && port <= 51 && priv->family_id == RTL8390_FAMILY_ID)
330 phylink_set(mask, 1000baseX_Full);
331
332 phylink_set(mask, 10baseT_Half);
333 phylink_set(mask, 10baseT_Full);
334 phylink_set(mask, 100baseT_Half);
335 phylink_set(mask, 100baseT_Full);
336
337 bitmap_and(supported, supported, mask,
338 __ETHTOOL_LINK_MODE_MASK_NBITS);
339 bitmap_and(state->advertising, state->advertising, mask,
340 __ETHTOOL_LINK_MODE_MASK_NBITS);
341 }
342
343 static void rtl93xx_phylink_validate(struct dsa_switch *ds, int port,
344 unsigned long *supported,
345 struct phylink_link_state *state)
346 {
347 struct rtl838x_switch_priv *priv = ds->priv;
348 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
349
350 pr_debug("In %s port %d, state is %d (%s)", __func__, port, state->interface,
351 phy_modes(state->interface));
352
353 if (!phy_interface_mode_is_rgmii(state->interface) &&
354 state->interface != PHY_INTERFACE_MODE_NA &&
355 state->interface != PHY_INTERFACE_MODE_1000BASEX &&
356 state->interface != PHY_INTERFACE_MODE_MII &&
357 state->interface != PHY_INTERFACE_MODE_REVMII &&
358 state->interface != PHY_INTERFACE_MODE_GMII &&
359 state->interface != PHY_INTERFACE_MODE_QSGMII &&
360 state->interface != PHY_INTERFACE_MODE_XGMII &&
361 state->interface != PHY_INTERFACE_MODE_HSGMII &&
362 state->interface != PHY_INTERFACE_MODE_10GBASER &&
363 state->interface != PHY_INTERFACE_MODE_10GKR &&
364 state->interface != PHY_INTERFACE_MODE_USXGMII &&
365 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
366 state->interface != PHY_INTERFACE_MODE_SGMII) {
367 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
368 dev_err(ds->dev,
369 "Unsupported interface: %d for port %d\n",
370 state->interface, port);
371 return;
372 }
373
374 /* Allow all the expected bits */
375 phylink_set(mask, Autoneg);
376 phylink_set_port_modes(mask);
377 phylink_set(mask, Pause);
378 phylink_set(mask, Asym_Pause);
379
380 /* With the exclusion of MII and Reverse MII, we support Gigabit,
381 * including Half duplex
382 */
383 if (state->interface != PHY_INTERFACE_MODE_MII &&
384 state->interface != PHY_INTERFACE_MODE_REVMII) {
385 phylink_set(mask, 1000baseT_Full);
386 phylink_set(mask, 1000baseT_Half);
387 }
388
389 // Internal phys of the RTL93xx family provide 10G
390 if (priv->ports[port].phy_is_integrated
391 && state->interface == PHY_INTERFACE_MODE_1000BASEX) {
392 phylink_set(mask, 1000baseX_Full);
393 } else if (priv->ports[port].phy_is_integrated) {
394 phylink_set(mask, 1000baseX_Full);
395 phylink_set(mask, 10000baseKR_Full);
396 phylink_set(mask, 10000baseSR_Full);
397 phylink_set(mask, 10000baseCR_Full);
398 }
399 if (state->interface == PHY_INTERFACE_MODE_INTERNAL) {
400 phylink_set(mask, 1000baseX_Full);
401 phylink_set(mask, 1000baseT_Full);
402 phylink_set(mask, 10000baseKR_Full);
403 phylink_set(mask, 10000baseT_Full);
404 phylink_set(mask, 10000baseSR_Full);
405 phylink_set(mask, 10000baseCR_Full);
406 }
407
408 if (state->interface == PHY_INTERFACE_MODE_USXGMII)
409 phylink_set(mask, 10000baseT_Full);
410
411 phylink_set(mask, 10baseT_Half);
412 phylink_set(mask, 10baseT_Full);
413 phylink_set(mask, 100baseT_Half);
414 phylink_set(mask, 100baseT_Full);
415
416 bitmap_and(supported, supported, mask,
417 __ETHTOOL_LINK_MODE_MASK_NBITS);
418 bitmap_and(state->advertising, state->advertising, mask,
419 __ETHTOOL_LINK_MODE_MASK_NBITS);
420 pr_debug("%s leaving supported: %*pb", __func__, __ETHTOOL_LINK_MODE_MASK_NBITS, supported);
421 }
422
423 static int rtl83xx_phylink_mac_link_state(struct dsa_switch *ds, int port,
424 struct phylink_link_state *state)
425 {
426 struct rtl838x_switch_priv *priv = ds->priv;
427 u64 speed;
428 u64 link;
429
430 if (port < 0 || port > priv->cpu_port)
431 return -EINVAL;
432
433 state->link = 0;
434 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
435 if (link & BIT_ULL(port))
436 state->link = 1;
437 pr_debug("%s: link state port %d: %llx\n", __func__, port, link & BIT_ULL(port));
438
439 state->duplex = 0;
440 if (priv->r->get_port_reg_le(priv->r->mac_link_dup_sts) & BIT_ULL(port))
441 state->duplex = 1;
442
443 speed = priv->r->get_port_reg_le(priv->r->mac_link_spd_sts(port));
444 speed >>= (port % 16) << 1;
445 switch (speed & 0x3) {
446 case 0:
447 state->speed = SPEED_10;
448 break;
449 case 1:
450 state->speed = SPEED_100;
451 break;
452 case 2:
453 state->speed = SPEED_1000;
454 break;
455 case 3:
456 if (priv->family_id == RTL9300_FAMILY_ID
457 && (port == 24 || port == 26)) /* Internal serdes */
458 state->speed = SPEED_2500;
459 else
460 state->speed = SPEED_100; /* Is in fact 500Mbit */
461 }
462
463 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
464 if (priv->r->get_port_reg_le(priv->r->mac_rx_pause_sts) & BIT_ULL(port))
465 state->pause |= MLO_PAUSE_RX;
466 if (priv->r->get_port_reg_le(priv->r->mac_tx_pause_sts) & BIT_ULL(port))
467 state->pause |= MLO_PAUSE_TX;
468 return 1;
469 }
470
471 static int rtl93xx_phylink_mac_link_state(struct dsa_switch *ds, int port,
472 struct phylink_link_state *state)
473 {
474 struct rtl838x_switch_priv *priv = ds->priv;
475 u64 speed;
476 u64 link;
477 u64 media;
478
479 if (port < 0 || port > priv->cpu_port)
480 return -EINVAL;
481
482 /*
483 * On the RTL9300 for at least the RTL8226B PHY, the MAC-side link
484 * state needs to be read twice in order to read a correct result.
485 * This would not be necessary for ports connected e.g. to RTL8218D
486 * PHYs.
487 */
488 state->link = 0;
489 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
490 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
491 if (link & BIT_ULL(port))
492 state->link = 1;
493
494 if (priv->family_id == RTL9310_FAMILY_ID)
495 media = priv->r->get_port_reg_le(RTL931X_MAC_LINK_MEDIA_STS);
496
497 if (priv->family_id == RTL9300_FAMILY_ID)
498 media = sw_r32(RTL930X_MAC_LINK_MEDIA_STS);
499
500 if (media & BIT_ULL(port))
501 state->link = 1;
502
503 pr_debug("%s: link state port %d: %llx, media %llx\n", __func__, port,
504 link & BIT_ULL(port), media);
505
506 state->duplex = 0;
507 if (priv->r->get_port_reg_le(priv->r->mac_link_dup_sts) & BIT_ULL(port))
508 state->duplex = 1;
509
510 speed = priv->r->get_port_reg_le(priv->r->mac_link_spd_sts(port));
511 speed >>= (port % 8) << 2;
512 switch (speed & 0xf) {
513 case 0:
514 state->speed = SPEED_10;
515 break;
516 case 1:
517 state->speed = SPEED_100;
518 break;
519 case 2:
520 case 7:
521 state->speed = SPEED_1000;
522 break;
523 case 4:
524 state->speed = SPEED_10000;
525 break;
526 case 5:
527 case 8:
528 state->speed = SPEED_2500;
529 break;
530 case 6:
531 state->speed = SPEED_5000;
532 break;
533 default:
534 pr_err("%s: unknown speed: %d\n", __func__, (u32)speed & 0xf);
535 }
536
537 if (priv->family_id == RTL9310_FAMILY_ID
538 && (port >= 52 || port <= 55)) { /* Internal serdes */
539 state->speed = SPEED_10000;
540 state->link = 1;
541 state->duplex = 1;
542 }
543
544 pr_debug("%s: speed is: %d %d\n", __func__, (u32)speed & 0xf, state->speed);
545 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
546 if (priv->r->get_port_reg_le(priv->r->mac_rx_pause_sts) & BIT_ULL(port))
547 state->pause |= MLO_PAUSE_RX;
548 if (priv->r->get_port_reg_le(priv->r->mac_tx_pause_sts) & BIT_ULL(port))
549 state->pause |= MLO_PAUSE_TX;
550 return 1;
551 }
552
553 static void rtl83xx_config_interface(int port, phy_interface_t interface)
554 {
555 u32 old, int_shift, sds_shift;
556
557 switch (port) {
558 case 24:
559 int_shift = 0;
560 sds_shift = 5;
561 break;
562 case 26:
563 int_shift = 3;
564 sds_shift = 0;
565 break;
566 default:
567 return;
568 }
569
570 old = sw_r32(RTL838X_SDS_MODE_SEL);
571 switch (interface) {
572 case PHY_INTERFACE_MODE_1000BASEX:
573 if ((old >> sds_shift & 0x1f) == 4)
574 return;
575 sw_w32_mask(0x7 << int_shift, 1 << int_shift, RTL838X_INT_MODE_CTRL);
576 sw_w32_mask(0x1f << sds_shift, 4 << sds_shift, RTL838X_SDS_MODE_SEL);
577 break;
578 case PHY_INTERFACE_MODE_SGMII:
579 if ((old >> sds_shift & 0x1f) == 2)
580 return;
581 sw_w32_mask(0x7 << int_shift, 2 << int_shift, RTL838X_INT_MODE_CTRL);
582 sw_w32_mask(0x1f << sds_shift, 2 << sds_shift, RTL838X_SDS_MODE_SEL);
583 break;
584 default:
585 return;
586 }
587 pr_debug("configured port %d for interface %s\n", port, phy_modes(interface));
588 }
589
590 static void rtl83xx_phylink_mac_config(struct dsa_switch *ds, int port,
591 unsigned int mode,
592 const struct phylink_link_state *state)
593 {
594 struct rtl838x_switch_priv *priv = ds->priv;
595 u32 reg;
596 int speed_bit = priv->family_id == RTL8380_FAMILY_ID ? 4 : 3;
597
598 pr_debug("%s port %d, mode %x\n", __func__, port, mode);
599
600 if (port == priv->cpu_port) {
601 /* Set Speed, duplex, flow control
602 * FORCE_EN | LINK_EN | NWAY_EN | DUP_SEL
603 * | SPD_SEL = 0b10 | FORCE_FC_EN | PHY_MASTER_SLV_MANUAL_EN
604 * | MEDIA_SEL
605 */
606 if (priv->family_id == RTL8380_FAMILY_ID) {
607 sw_w32(0x6192F, priv->r->mac_force_mode_ctrl(priv->cpu_port));
608 /* allow CRC errors on CPU-port */
609 sw_w32_mask(0, 0x8, RTL838X_MAC_PORT_CTRL(priv->cpu_port));
610 } else {
611 sw_w32_mask(0, 3, priv->r->mac_force_mode_ctrl(priv->cpu_port));
612 }
613 return;
614 }
615
616 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
617 /* Auto-Negotiation does not work for MAC in RTL8390 */
618 if (priv->family_id == RTL8380_FAMILY_ID) {
619 if (mode == MLO_AN_PHY || phylink_autoneg_inband(mode)) {
620 pr_debug("PHY autonegotiates\n");
621 reg |= RTL838X_NWAY_EN;
622 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
623 rtl83xx_config_interface(port, state->interface);
624 return;
625 }
626 }
627
628 if (mode != MLO_AN_FIXED)
629 pr_debug("Fixed state.\n");
630
631 /* Clear id_mode_dis bit, and the existing port mode, let
632 * RGMII_MODE_EN bet set by mac_link_{up,down} */
633 if (priv->family_id == RTL8380_FAMILY_ID) {
634 reg &= ~(RTL838X_RX_PAUSE_EN | RTL838X_TX_PAUSE_EN);
635 if (state->pause & MLO_PAUSE_TXRX_MASK) {
636 if (state->pause & MLO_PAUSE_TX)
637 reg |= RTL838X_TX_PAUSE_EN;
638 reg |= RTL838X_RX_PAUSE_EN;
639 }
640 } else if (priv->family_id == RTL8390_FAMILY_ID) {
641 reg &= ~(RTL839X_RX_PAUSE_EN | RTL839X_TX_PAUSE_EN);
642 if (state->pause & MLO_PAUSE_TXRX_MASK) {
643 if (state->pause & MLO_PAUSE_TX)
644 reg |= RTL839X_TX_PAUSE_EN;
645 reg |= RTL839X_RX_PAUSE_EN;
646 }
647 }
648
649
650 reg &= ~(3 << speed_bit);
651 switch (state->speed) {
652 case SPEED_1000:
653 reg |= 2 << speed_bit;
654 break;
655 case SPEED_100:
656 reg |= 1 << speed_bit;
657 break;
658 default:
659 break; // Ignore, including 10MBit which has a speed value of 0
660 }
661
662 if (priv->family_id == RTL8380_FAMILY_ID) {
663 reg &= ~(RTL838X_DUPLEX_MODE | RTL838X_FORCE_LINK_EN);
664 if (state->link)
665 reg |= RTL838X_FORCE_LINK_EN;
666 if (state->duplex == RTL838X_DUPLEX_MODE)
667 reg |= RTL838X_DUPLEX_MODE;
668 } else if (priv->family_id == RTL8390_FAMILY_ID) {
669 reg &= ~(RTL839X_DUPLEX_MODE | RTL839X_FORCE_LINK_EN);
670 if (state->link)
671 reg |= RTL839X_FORCE_LINK_EN;
672 if (state->duplex == RTL839X_DUPLEX_MODE)
673 reg |= RTL839X_DUPLEX_MODE;
674 }
675
676 // LAG members must use DUPLEX and we need to enable the link
677 if (priv->lagmembers & BIT_ULL(port)) {
678 switch(priv->family_id) {
679 case RTL8380_FAMILY_ID:
680 reg |= (RTL838X_DUPLEX_MODE | RTL838X_FORCE_LINK_EN);
681 break;
682 case RTL8390_FAMILY_ID:
683 reg |= (RTL839X_DUPLEX_MODE | RTL839X_FORCE_LINK_EN);
684 break;
685 }
686 }
687
688 // Disable AN
689 if (priv->family_id == RTL8380_FAMILY_ID)
690 reg &= ~RTL838X_NWAY_EN;
691 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
692 }
693
694 static void rtl931x_phylink_mac_config(struct dsa_switch *ds, int port,
695 unsigned int mode,
696 const struct phylink_link_state *state)
697 {
698 struct rtl838x_switch_priv *priv = ds->priv;
699 int sds_num;
700 u32 reg, band;
701
702 sds_num = priv->ports[port].sds_num;
703 pr_info("%s: speed %d sds_num %d\n", __func__, state->speed, sds_num);
704
705 switch (state->interface) {
706 case PHY_INTERFACE_MODE_HSGMII:
707 pr_info("%s setting mode PHY_INTERFACE_MODE_HSGMII\n", __func__);
708 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_HSGMII);
709 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_HSGMII);
710 band = rtl931x_sds_cmu_band_set(sds_num, true, 62, PHY_INTERFACE_MODE_HSGMII);
711 break;
712 case PHY_INTERFACE_MODE_1000BASEX:
713 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_1000BASEX);
714 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_1000BASEX);
715 break;
716 case PHY_INTERFACE_MODE_XGMII:
717 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_XGMII);
718 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_XGMII);
719 break;
720 case PHY_INTERFACE_MODE_10GBASER:
721 case PHY_INTERFACE_MODE_10GKR:
722 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_10GBASER);
723 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_10GBASER);
724 break;
725 case PHY_INTERFACE_MODE_USXGMII:
726 // Translates to MII_USXGMII_10GSXGMII
727 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_USXGMII);
728 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_USXGMII);
729 break;
730 case PHY_INTERFACE_MODE_SGMII:
731 pr_info("%s setting mode PHY_INTERFACE_MODE_SGMII\n", __func__);
732 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_SGMII);
733 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_SGMII);
734 band = rtl931x_sds_cmu_band_set(sds_num, true, 62, PHY_INTERFACE_MODE_SGMII);
735 break;
736 case PHY_INTERFACE_MODE_QSGMII:
737 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_QSGMII);
738 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_QSGMII);
739 break;
740 default:
741 pr_err("%s: unknown serdes mode: %s\n",
742 __func__, phy_modes(state->interface));
743 return;
744 }
745
746 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
747 pr_info("%s reading FORCE_MODE_CTRL: %08x\n", __func__, reg);
748
749 reg &= ~(RTL931X_DUPLEX_MODE | RTL931X_FORCE_EN | RTL931X_FORCE_LINK_EN);
750
751 reg &= ~(0xf << 12);
752 reg |= 0x2 << 12; // Set SMI speed to 0x2
753
754 reg |= RTL931X_TX_PAUSE_EN | RTL931X_RX_PAUSE_EN;
755
756 if (priv->lagmembers & BIT_ULL(port))
757 reg |= RTL931X_DUPLEX_MODE;
758
759 if (state->duplex == DUPLEX_FULL)
760 reg |= RTL931X_DUPLEX_MODE;
761
762 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
763
764 }
765
766 static void rtl93xx_phylink_mac_config(struct dsa_switch *ds, int port,
767 unsigned int mode,
768 const struct phylink_link_state *state)
769 {
770 struct rtl838x_switch_priv *priv = ds->priv;
771 int sds_num, sds_mode;
772 u32 reg;
773
774 pr_info("%s port %d, mode %x, phy-mode: %s, speed %d, link %d\n", __func__,
775 port, mode, phy_modes(state->interface), state->speed, state->link);
776
777 // Nothing to be done for the CPU-port
778 if (port == priv->cpu_port)
779 return;
780
781 if (priv->family_id == RTL9310_FAMILY_ID)
782 return rtl931x_phylink_mac_config(ds, port, mode, state);
783
784 sds_num = priv->ports[port].sds_num;
785 pr_info("%s SDS is %d\n", __func__, sds_num);
786 if (sds_num >= 0) {
787 switch (state->interface) {
788 case PHY_INTERFACE_MODE_HSGMII:
789 sds_mode = 0x12;
790 break;
791 case PHY_INTERFACE_MODE_1000BASEX:
792 sds_mode = 0x04;
793 break;
794 case PHY_INTERFACE_MODE_XGMII:
795 sds_mode = 0x10;
796 break;
797 case PHY_INTERFACE_MODE_10GBASER:
798 case PHY_INTERFACE_MODE_10GKR:
799 sds_mode = 0x1b; // 10G 1000X Auto
800 break;
801 case PHY_INTERFACE_MODE_USXGMII:
802 sds_mode = 0x0d;
803 break;
804 default:
805 pr_err("%s: unknown serdes mode: %s\n",
806 __func__, phy_modes(state->interface));
807 return;
808 }
809 rtl9300_sds_rst(sds_num, sds_mode);
810 }
811
812 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
813 reg &= ~(0xf << 3);
814
815 switch (state->speed) {
816 case SPEED_10000:
817 reg |= 4 << 3;
818 break;
819 case SPEED_5000:
820 reg |= 6 << 3;
821 break;
822 case SPEED_2500:
823 reg |= 5 << 3;
824 break;
825 case SPEED_1000:
826 reg |= 2 << 3;
827 break;
828 default:
829 reg |= 2 << 3;
830 break;
831 }
832
833 if (state->link)
834 reg |= RTL930X_FORCE_LINK_EN;
835
836 if (priv->lagmembers & BIT_ULL(port))
837 reg |= RTL930X_DUPLEX_MODE | RTL930X_FORCE_LINK_EN;
838
839 if (state->duplex == DUPLEX_FULL)
840 reg |= RTL930X_DUPLEX_MODE;
841
842 if (priv->ports[port].phy_is_integrated)
843 reg &= ~RTL930X_FORCE_EN; // Clear MAC_FORCE_EN to allow SDS-MAC link
844 else
845 reg |= RTL930X_FORCE_EN;
846
847 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
848 }
849
850 static void rtl83xx_phylink_mac_link_down(struct dsa_switch *ds, int port,
851 unsigned int mode,
852 phy_interface_t interface)
853 {
854 struct rtl838x_switch_priv *priv = ds->priv;
855 u32 v;
856
857 /* Stop TX/RX to port */
858 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(port));
859
860 // No longer force link
861 if (priv->family_id == RTL9300_FAMILY_ID)
862 v = RTL930X_FORCE_EN | RTL930X_FORCE_LINK_EN;
863 else if (priv->family_id == RTL9310_FAMILY_ID)
864 v = RTL931X_FORCE_EN | RTL931X_FORCE_LINK_EN;
865 sw_w32_mask(v, 0, priv->r->mac_port_ctrl(port));
866 }
867
868 static void rtl93xx_phylink_mac_link_down(struct dsa_switch *ds, int port,
869 unsigned int mode,
870 phy_interface_t interface)
871 {
872 struct rtl838x_switch_priv *priv = ds->priv;
873 /* Stop TX/RX to port */
874 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(port));
875
876 // No longer force link
877 sw_w32_mask(3, 0, priv->r->mac_force_mode_ctrl(port));
878 }
879
880 static void rtl83xx_phylink_mac_link_up(struct dsa_switch *ds, int port,
881 unsigned int mode,
882 phy_interface_t interface,
883 struct phy_device *phydev,
884 int speed, int duplex,
885 bool tx_pause, bool rx_pause)
886 {
887 struct rtl838x_switch_priv *priv = ds->priv;
888 /* Restart TX/RX to port */
889 sw_w32_mask(0, 0x3, priv->r->mac_port_ctrl(port));
890 // TODO: Set speed/duplex/pauses
891 }
892
893 static void rtl93xx_phylink_mac_link_up(struct dsa_switch *ds, int port,
894 unsigned int mode,
895 phy_interface_t interface,
896 struct phy_device *phydev,
897 int speed, int duplex,
898 bool tx_pause, bool rx_pause)
899 {
900 struct rtl838x_switch_priv *priv = ds->priv;
901
902 /* Restart TX/RX to port */
903 sw_w32_mask(0, 0x3, priv->r->mac_port_ctrl(port));
904 // TODO: Set speed/duplex/pauses
905 }
906
907 static void rtl83xx_get_strings(struct dsa_switch *ds,
908 int port, u32 stringset, u8 *data)
909 {
910 int i;
911
912 if (stringset != ETH_SS_STATS)
913 return;
914
915 for (i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++)
916 strncpy(data + i * ETH_GSTRING_LEN, rtl83xx_mib[i].name,
917 ETH_GSTRING_LEN);
918 }
919
920 static void rtl83xx_get_ethtool_stats(struct dsa_switch *ds, int port,
921 uint64_t *data)
922 {
923 struct rtl838x_switch_priv *priv = ds->priv;
924 const struct rtl83xx_mib_desc *mib;
925 int i;
926 u64 h;
927
928 for (i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++) {
929 mib = &rtl83xx_mib[i];
930
931 data[i] = sw_r32(priv->r->stat_port_std_mib + (port << 8) + 252 - mib->offset);
932 if (mib->size == 2) {
933 h = sw_r32(priv->r->stat_port_std_mib + (port << 8) + 248 - mib->offset);
934 data[i] |= h << 32;
935 }
936 }
937 }
938
939 static int rtl83xx_get_sset_count(struct dsa_switch *ds, int port, int sset)
940 {
941 if (sset != ETH_SS_STATS)
942 return 0;
943
944 return ARRAY_SIZE(rtl83xx_mib);
945 }
946
947 static int rtl83xx_mc_group_alloc(struct rtl838x_switch_priv *priv, int port)
948 {
949 int mc_group = find_first_zero_bit(priv->mc_group_bm, MAX_MC_GROUPS - 1);
950 u64 portmask;
951
952 if (mc_group >= MAX_MC_GROUPS - 1)
953 return -1;
954
955 if (priv->is_lagmember[port]) {
956 pr_info("%s: %d is lag slave. ignore\n", __func__, port);
957 return 0;
958 }
959
960 set_bit(mc_group, priv->mc_group_bm);
961 mc_group++; // We cannot use group 0, as this is used for lookup miss flooding
962 portmask = BIT_ULL(port) | BIT_ULL(priv->cpu_port);
963 priv->r->write_mcast_pmask(mc_group, portmask);
964
965 return mc_group;
966 }
967
968 static u64 rtl83xx_mc_group_add_port(struct rtl838x_switch_priv *priv, int mc_group, int port)
969 {
970 u64 portmask = priv->r->read_mcast_pmask(mc_group);
971
972 pr_debug("%s: %d\n", __func__, port);
973 if (priv->is_lagmember[port]) {
974 pr_info("%s: %d is lag slave. ignore\n", __func__, port);
975 return portmask;
976 }
977 portmask |= BIT_ULL(port);
978 priv->r->write_mcast_pmask(mc_group, portmask);
979
980 return portmask;
981 }
982
983 static u64 rtl83xx_mc_group_del_port(struct rtl838x_switch_priv *priv, int mc_group, int port)
984 {
985 u64 portmask = priv->r->read_mcast_pmask(mc_group);
986
987 pr_debug("%s: %d\n", __func__, port);
988 if (priv->is_lagmember[port]) {
989 pr_info("%s: %d is lag slave. ignore\n", __func__, port);
990 return portmask;
991 }
992 priv->r->write_mcast_pmask(mc_group, portmask);
993 if (portmask == BIT_ULL(priv->cpu_port)) {
994 portmask &= ~BIT_ULL(priv->cpu_port);
995 priv->r->write_mcast_pmask(mc_group, portmask);
996 clear_bit(mc_group, priv->mc_group_bm);
997 }
998
999 return portmask;
1000 }
1001
1002 static void store_mcgroups(struct rtl838x_switch_priv *priv, int port)
1003 {
1004 int mc_group;
1005
1006 for (mc_group = 0; mc_group < MAX_MC_GROUPS; mc_group++) {
1007 u64 portmask = priv->r->read_mcast_pmask(mc_group);
1008 if (portmask & BIT_ULL(port)) {
1009 priv->mc_group_saves[mc_group] = port;
1010 rtl83xx_mc_group_del_port(priv, mc_group, port);
1011 }
1012 }
1013 }
1014
1015 static void load_mcgroups(struct rtl838x_switch_priv *priv, int port)
1016 {
1017 int mc_group;
1018
1019 for (mc_group = 0; mc_group < MAX_MC_GROUPS; mc_group++) {
1020 if (priv->mc_group_saves[mc_group] == port) {
1021 rtl83xx_mc_group_add_port(priv, mc_group, port);
1022 priv->mc_group_saves[mc_group] = -1;
1023 }
1024 }
1025 }
1026
1027 static int rtl83xx_port_enable(struct dsa_switch *ds, int port,
1028 struct phy_device *phydev)
1029 {
1030 struct rtl838x_switch_priv *priv = ds->priv;
1031 u64 v;
1032
1033 pr_debug("%s: %x %d", __func__, (u32) priv, port);
1034 priv->ports[port].enable = true;
1035
1036 /* enable inner tagging on egress, do not keep any tags */
1037 if (priv->family_id == RTL9310_FAMILY_ID)
1038 sw_w32(BIT(4), priv->r->vlan_port_tag_sts_ctrl + (port << 2));
1039 else
1040 sw_w32(1, priv->r->vlan_port_tag_sts_ctrl + (port << 2));
1041
1042 if (dsa_is_cpu_port(ds, port))
1043 return 0;
1044
1045 /* add port to switch mask of CPU_PORT */
1046 priv->r->traffic_enable(priv->cpu_port, port);
1047
1048 load_mcgroups(priv, port);
1049
1050 if (priv->is_lagmember[port]) {
1051 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1052 return 0;
1053 }
1054
1055 /* add all other ports in the same bridge to switch mask of port */
1056 v = priv->r->traffic_get(port);
1057 v |= priv->ports[port].pm;
1058 priv->r->traffic_set(port, v);
1059
1060 // TODO: Figure out if this is necessary
1061 if (priv->family_id == RTL9300_FAMILY_ID) {
1062 sw_w32_mask(0, BIT(port), RTL930X_L2_PORT_SABLK_CTRL);
1063 sw_w32_mask(0, BIT(port), RTL930X_L2_PORT_DABLK_CTRL);
1064 }
1065
1066 if (priv->ports[port].sds_num < 0)
1067 priv->ports[port].sds_num = rtl93xx_get_sds(phydev);
1068
1069 return 0;
1070 }
1071
1072 static void rtl83xx_port_disable(struct dsa_switch *ds, int port)
1073 {
1074 struct rtl838x_switch_priv *priv = ds->priv;
1075 u64 v;
1076
1077 pr_debug("%s %x: %d", __func__, (u32)priv, port);
1078 /* you can only disable user ports */
1079 if (!dsa_is_user_port(ds, port))
1080 return;
1081
1082 // BUG: This does not work on RTL931X
1083 /* remove port from switch mask of CPU_PORT */
1084 priv->r->traffic_disable(priv->cpu_port, port);
1085 store_mcgroups(priv, port);
1086
1087 /* remove all other ports in the same bridge from switch mask of port */
1088 v = priv->r->traffic_get(port);
1089 v &= ~priv->ports[port].pm;
1090 priv->r->traffic_set(port, v);
1091
1092 priv->ports[port].enable = false;
1093 }
1094
1095 static int rtl83xx_set_mac_eee(struct dsa_switch *ds, int port,
1096 struct ethtool_eee *e)
1097 {
1098 struct rtl838x_switch_priv *priv = ds->priv;
1099
1100 if (e->eee_enabled && !priv->eee_enabled) {
1101 pr_info("Globally enabling EEE\n");
1102 priv->r->init_eee(priv, true);
1103 }
1104
1105 priv->r->port_eee_set(priv, port, e->eee_enabled);
1106
1107 if (e->eee_enabled)
1108 pr_info("Enabled EEE for port %d\n", port);
1109 else
1110 pr_info("Disabled EEE for port %d\n", port);
1111 return 0;
1112 }
1113
1114 static int rtl83xx_get_mac_eee(struct dsa_switch *ds, int port,
1115 struct ethtool_eee *e)
1116 {
1117 struct rtl838x_switch_priv *priv = ds->priv;
1118
1119 e->supported = SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full;
1120
1121 priv->r->eee_port_ability(priv, e, port);
1122
1123 e->eee_enabled = priv->ports[port].eee_enabled;
1124
1125 e->eee_active = !!(e->advertised & e->lp_advertised);
1126
1127 return 0;
1128 }
1129
1130 static int rtl93xx_get_mac_eee(struct dsa_switch *ds, int port,
1131 struct ethtool_eee *e)
1132 {
1133 struct rtl838x_switch_priv *priv = ds->priv;
1134
1135 e->supported = SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full
1136 | SUPPORTED_2500baseX_Full;
1137
1138 priv->r->eee_port_ability(priv, e, port);
1139
1140 e->eee_enabled = priv->ports[port].eee_enabled;
1141
1142 e->eee_active = !!(e->advertised & e->lp_advertised);
1143
1144 return 0;
1145 }
1146
1147 static int rtl83xx_set_ageing_time(struct dsa_switch *ds, unsigned int msec)
1148 {
1149 struct rtl838x_switch_priv *priv = ds->priv;
1150
1151 priv->r->set_ageing_time(msec);
1152 return 0;
1153 }
1154
1155 static int rtl83xx_port_bridge_join(struct dsa_switch *ds, int port,
1156 struct net_device *bridge)
1157 {
1158 struct rtl838x_switch_priv *priv = ds->priv;
1159 u64 port_bitmap = BIT_ULL(priv->cpu_port), v;
1160 int i;
1161
1162 pr_debug("%s %x: %d %llx", __func__, (u32)priv, port, port_bitmap);
1163
1164 if (priv->is_lagmember[port]) {
1165 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1166 return 0;
1167 }
1168
1169 mutex_lock(&priv->reg_mutex);
1170 for (i = 0; i < ds->num_ports; i++) {
1171 /* Add this port to the port matrix of the other ports in the
1172 * same bridge. If the port is disabled, port matrix is kept
1173 * and not being setup until the port becomes enabled.
1174 */
1175 if (dsa_is_user_port(ds, i) && !priv->is_lagmember[i] && i != port) {
1176 if (dsa_to_port(ds, i)->bridge_dev != bridge)
1177 continue;
1178 if (priv->ports[i].enable)
1179 priv->r->traffic_enable(i, port);
1180
1181 priv->ports[i].pm |= BIT_ULL(port);
1182 port_bitmap |= BIT_ULL(i);
1183 }
1184 }
1185 load_mcgroups(priv, port);
1186
1187 /* Add all other ports to this port matrix. */
1188 if (priv->ports[port].enable) {
1189 priv->r->traffic_enable(priv->cpu_port, port);
1190 v = priv->r->traffic_get(port);
1191 v |= port_bitmap;
1192 priv->r->traffic_set(port, v);
1193 }
1194 priv->ports[port].pm |= port_bitmap;
1195 mutex_unlock(&priv->reg_mutex);
1196
1197 return 0;
1198 }
1199
1200 static void rtl83xx_port_bridge_leave(struct dsa_switch *ds, int port,
1201 struct net_device *bridge)
1202 {
1203 struct rtl838x_switch_priv *priv = ds->priv;
1204 u64 port_bitmap = BIT_ULL(priv->cpu_port), v;
1205 int i;
1206
1207 pr_debug("%s %x: %d", __func__, (u32)priv, port);
1208 mutex_lock(&priv->reg_mutex);
1209 for (i = 0; i < ds->num_ports; i++) {
1210 /* Remove this port from the port matrix of the other ports
1211 * in the same bridge. If the port is disabled, port matrix
1212 * is kept and not being setup until the port becomes enabled.
1213 * And the other port's port matrix cannot be broken when the
1214 * other port is still a VLAN-aware port.
1215 */
1216 if (dsa_is_user_port(ds, i) && i != port) {
1217 if (dsa_to_port(ds, i)->bridge_dev != bridge)
1218 continue;
1219 if (priv->ports[i].enable)
1220 priv->r->traffic_disable(i, port);
1221
1222 priv->ports[i].pm |= BIT_ULL(port);
1223 port_bitmap &= ~BIT_ULL(i);
1224 }
1225 }
1226 store_mcgroups(priv, port);
1227
1228 /* Add all other ports to this port matrix. */
1229 if (priv->ports[port].enable) {
1230 v = priv->r->traffic_get(port);
1231 v |= port_bitmap;
1232 priv->r->traffic_set(port, v);
1233 }
1234 priv->ports[port].pm &= ~port_bitmap;
1235
1236 mutex_unlock(&priv->reg_mutex);
1237 }
1238
1239 void rtl83xx_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1240 {
1241 u32 msti = 0;
1242 u32 port_state[4];
1243 int index, bit;
1244 int pos = port;
1245 struct rtl838x_switch_priv *priv = ds->priv;
1246 int n = priv->port_width << 1;
1247
1248 /* Ports above or equal CPU port can never be configured */
1249 if (port >= priv->cpu_port)
1250 return;
1251
1252 mutex_lock(&priv->reg_mutex);
1253
1254 /* For the RTL839x and following, the bits are left-aligned, 838x and 930x
1255 * have 64 bit fields, 839x and 931x have 128 bit fields
1256 */
1257 if (priv->family_id == RTL8390_FAMILY_ID)
1258 pos += 12;
1259 if (priv->family_id == RTL9300_FAMILY_ID)
1260 pos += 3;
1261 if (priv->family_id == RTL9310_FAMILY_ID)
1262 pos += 8;
1263
1264 index = n - (pos >> 4) - 1;
1265 bit = (pos << 1) % 32;
1266
1267 priv->r->stp_get(priv, msti, port_state);
1268
1269 pr_debug("Current state, port %d: %d\n", port, (port_state[index] >> bit) & 3);
1270 port_state[index] &= ~(3 << bit);
1271
1272 switch (state) {
1273 case BR_STATE_DISABLED: /* 0 */
1274 port_state[index] |= (0 << bit);
1275 break;
1276 case BR_STATE_BLOCKING: /* 4 */
1277 case BR_STATE_LISTENING: /* 1 */
1278 port_state[index] |= (1 << bit);
1279 break;
1280 case BR_STATE_LEARNING: /* 2 */
1281 port_state[index] |= (2 << bit);
1282 break;
1283 case BR_STATE_FORWARDING: /* 3*/
1284 port_state[index] |= (3 << bit);
1285 default:
1286 break;
1287 }
1288
1289 priv->r->stp_set(priv, msti, port_state);
1290
1291 mutex_unlock(&priv->reg_mutex);
1292 }
1293
1294 void rtl83xx_fast_age(struct dsa_switch *ds, int port)
1295 {
1296 struct rtl838x_switch_priv *priv = ds->priv;
1297 int s = priv->family_id == RTL8390_FAMILY_ID ? 2 : 0;
1298
1299 pr_debug("FAST AGE port %d\n", port);
1300 mutex_lock(&priv->reg_mutex);
1301 /* RTL838X_L2_TBL_FLUSH_CTRL register bits, 839x has 1 bit larger
1302 * port fields:
1303 * 0-4: Replacing port
1304 * 5-9: Flushed/replaced port
1305 * 10-21: FVID
1306 * 22: Entry types: 1: dynamic, 0: also static
1307 * 23: Match flush port
1308 * 24: Match FVID
1309 * 25: Flush (0) or replace (1) L2 entries
1310 * 26: Status of action (1: Start, 0: Done)
1311 */
1312 sw_w32(1 << (26 + s) | 1 << (23 + s) | port << (5 + (s / 2)), priv->r->l2_tbl_flush_ctrl);
1313
1314 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(26 + s));
1315
1316 mutex_unlock(&priv->reg_mutex);
1317 }
1318
1319 void rtl931x_fast_age(struct dsa_switch *ds, int port)
1320 {
1321 struct rtl838x_switch_priv *priv = ds->priv;
1322
1323 pr_info("%s port %d\n", __func__, port);
1324 mutex_lock(&priv->reg_mutex);
1325 sw_w32(port << 11, RTL931X_L2_TBL_FLUSH_CTRL + 4);
1326
1327 sw_w32(BIT(24) | BIT(28), RTL931X_L2_TBL_FLUSH_CTRL);
1328
1329 do { } while (sw_r32(RTL931X_L2_TBL_FLUSH_CTRL) & BIT (28));
1330
1331 mutex_unlock(&priv->reg_mutex);
1332 }
1333
1334 void rtl930x_fast_age(struct dsa_switch *ds, int port)
1335 {
1336 struct rtl838x_switch_priv *priv = ds->priv;
1337
1338 if (priv->family_id == RTL9310_FAMILY_ID)
1339 return rtl931x_fast_age(ds, port);
1340
1341 pr_debug("FAST AGE port %d\n", port);
1342 mutex_lock(&priv->reg_mutex);
1343 sw_w32(port << 11, RTL930X_L2_TBL_FLUSH_CTRL + 4);
1344
1345 sw_w32(BIT(26) | BIT(30), RTL930X_L2_TBL_FLUSH_CTRL);
1346
1347 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(30));
1348
1349 mutex_unlock(&priv->reg_mutex);
1350 }
1351
1352 static int rtl83xx_vlan_filtering(struct dsa_switch *ds, int port,
1353 bool vlan_filtering,
1354 struct switchdev_trans *trans)
1355 {
1356 struct rtl838x_switch_priv *priv = ds->priv;
1357
1358 pr_debug("%s: port %d\n", __func__, port);
1359 mutex_lock(&priv->reg_mutex);
1360
1361 if (vlan_filtering) {
1362 /* Enable ingress and egress filtering
1363 * The VLAN_PORT_IGR_FILTER register uses 2 bits for each port to define
1364 * the filter action:
1365 * 0: Always Forward
1366 * 1: Drop packet
1367 * 2: Trap packet to CPU port
1368 * The Egress filter used 1 bit per state (0: DISABLED, 1: ENABLED)
1369 */
1370 if (port != priv->cpu_port)
1371 priv->r->set_vlan_igr_filter(port, IGR_DROP);
1372
1373 priv->r->set_vlan_egr_filter(port, EGR_ENABLE);
1374 } else {
1375 /* Disable ingress and egress filtering */
1376 if (port != priv->cpu_port)
1377 priv->r->set_vlan_igr_filter(port, IGR_FORWARD);
1378
1379 priv->r->set_vlan_egr_filter(port, EGR_DISABLE);
1380 }
1381
1382 /* Do we need to do something to the CPU-Port, too? */
1383 mutex_unlock(&priv->reg_mutex);
1384
1385 return 0;
1386 }
1387
1388 static int rtl83xx_vlan_prepare(struct dsa_switch *ds, int port,
1389 const struct switchdev_obj_port_vlan *vlan)
1390 {
1391 struct rtl838x_vlan_info info;
1392 struct rtl838x_switch_priv *priv = ds->priv;
1393
1394 priv->r->vlan_tables_read(0, &info);
1395
1396 pr_debug("VLAN 0: Tagged ports %llx, untag %llx, profile %d, MC# %d, UC# %d, FID %x\n",
1397 info.tagged_ports, info.untagged_ports, info.profile_id,
1398 info.hash_mc_fid, info.hash_uc_fid, info.fid);
1399
1400 priv->r->vlan_tables_read(1, &info);
1401 pr_debug("VLAN 1: Tagged ports %llx, untag %llx, profile %d, MC# %d, UC# %d, FID %x\n",
1402 info.tagged_ports, info.untagged_ports, info.profile_id,
1403 info.hash_mc_fid, info.hash_uc_fid, info.fid);
1404 priv->r->vlan_set_untagged(1, info.untagged_ports);
1405 pr_debug("SET: Untagged ports, VLAN %d: %llx\n", 1, info.untagged_ports);
1406
1407 priv->r->vlan_set_tagged(1, &info);
1408 pr_debug("SET: Tagged ports, VLAN %d: %llx\n", 1, info.tagged_ports);
1409
1410 mutex_unlock(&priv->reg_mutex);
1411 return 0;
1412 }
1413
1414 static void rtl83xx_vlan_add(struct dsa_switch *ds, int port,
1415 const struct switchdev_obj_port_vlan *vlan)
1416 {
1417 struct rtl838x_vlan_info info;
1418 struct rtl838x_switch_priv *priv = ds->priv;
1419 int v;
1420
1421 pr_debug("%s port %d, vid_end %d, vid_end %d, flags %x\n", __func__,
1422 port, vlan->vid_begin, vlan->vid_end, vlan->flags);
1423
1424 if (vlan->vid_begin > 4095 || vlan->vid_end > 4095) {
1425 dev_err(priv->dev, "VLAN out of range: %d - %d",
1426 vlan->vid_begin, vlan->vid_end);
1427 return;
1428 }
1429
1430 mutex_lock(&priv->reg_mutex);
1431
1432 if (vlan->flags & BRIDGE_VLAN_INFO_PVID) {
1433 for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
1434 if (!v)
1435 continue;
1436 /* Set both inner and outer PVID of the port */
1437 priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_INNER, v);
1438 priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_OUTER, v);
1439 priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_INNER,
1440 PBVLAN_MODE_UNTAG_AND_PRITAG);
1441 priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_OUTER,
1442 PBVLAN_MODE_UNTAG_AND_PRITAG);
1443
1444 priv->ports[port].pvid = vlan->vid_end;
1445 }
1446 }
1447
1448 for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
1449 /* Get port memberships of this vlan */
1450 priv->r->vlan_tables_read(v, &info);
1451
1452 /* new VLAN? */
1453 if (!info.tagged_ports) {
1454 info.fid = 0;
1455 info.hash_mc_fid = false;
1456 info.hash_uc_fid = false;
1457 info.profile_id = 0;
1458 }
1459
1460 /* sanitize untagged_ports - must be a subset */
1461 if (info.untagged_ports & ~info.tagged_ports)
1462 info.untagged_ports = 0;
1463
1464 info.tagged_ports |= BIT_ULL(port);
1465 if (vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED)
1466 info.untagged_ports |= BIT_ULL(port);
1467
1468 priv->r->vlan_set_untagged(v, info.untagged_ports);
1469 pr_debug("Untagged ports, VLAN %d: %llx\n", v, info.untagged_ports);
1470
1471 priv->r->vlan_set_tagged(v, &info);
1472 pr_debug("Tagged ports, VLAN %d: %llx\n", v, info.tagged_ports);
1473 }
1474
1475 mutex_unlock(&priv->reg_mutex);
1476 }
1477
1478 static int rtl83xx_vlan_del(struct dsa_switch *ds, int port,
1479 const struct switchdev_obj_port_vlan *vlan)
1480 {
1481 struct rtl838x_vlan_info info;
1482 struct rtl838x_switch_priv *priv = ds->priv;
1483 int v;
1484 u16 pvid;
1485
1486 pr_debug("%s: port %d, vid_end %d, vid_end %d, flags %x\n", __func__,
1487 port, vlan->vid_begin, vlan->vid_end, vlan->flags);
1488
1489 if (vlan->vid_begin > 4095 || vlan->vid_end > 4095) {
1490 dev_err(priv->dev, "VLAN out of range: %d - %d",
1491 vlan->vid_begin, vlan->vid_end);
1492 return -ENOTSUPP;
1493 }
1494
1495 mutex_lock(&priv->reg_mutex);
1496 pvid = priv->ports[port].pvid;
1497
1498 for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
1499 /* Reset to default if removing the current PVID */
1500 if (v == pvid) {
1501 priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_INNER, 0);
1502 priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_OUTER, 0);
1503 priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_INNER,
1504 PBVLAN_MODE_UNTAG_AND_PRITAG);
1505 priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_OUTER,
1506 PBVLAN_MODE_UNTAG_AND_PRITAG);
1507 }
1508 /* Get port memberships of this vlan */
1509 priv->r->vlan_tables_read(v, &info);
1510
1511 /* remove port from both tables */
1512 info.untagged_ports &= (~BIT_ULL(port));
1513 info.tagged_ports &= (~BIT_ULL(port));
1514
1515 priv->r->vlan_set_untagged(v, info.untagged_ports);
1516 pr_debug("Untagged ports, VLAN %d: %llx\n", v, info.untagged_ports);
1517
1518 priv->r->vlan_set_tagged(v, &info);
1519 pr_debug("Tagged ports, VLAN %d: %llx\n", v, info.tagged_ports);
1520 }
1521 mutex_unlock(&priv->reg_mutex);
1522
1523 return 0;
1524 }
1525
1526 static void dump_l2_entry(struct rtl838x_l2_entry *e)
1527 {
1528 pr_info("MAC: %02x:%02x:%02x:%02x:%02x:%02x vid: %d, rvid: %d, port: %d, valid: %d\n",
1529 e->mac[0], e->mac[1], e->mac[2], e->mac[3], e->mac[4], e->mac[5],
1530 e->vid, e->rvid, e->port, e->valid);
1531
1532 if (e->type != L2_MULTICAST) {
1533 pr_info("Type: %d, is_static: %d, is_ip_mc: %d, is_ipv6_mc: %d, block_da: %d\n",
1534 e->type, e->is_static, e->is_ip_mc, e->is_ipv6_mc, e->block_da);
1535 pr_info(" block_sa: %d, susp: %d, nh: %d, age: %d, is_trunk: %d, trunk: %d\n",
1536 e->block_sa, e->suspended, e->next_hop, e->age, e->is_trunk, e->trunk);
1537 }
1538 if (e->type == L2_MULTICAST)
1539 pr_info(" L2_MULTICAST mc_portmask_index: %d\n", e->mc_portmask_index);
1540 if (e->is_ip_mc || e->is_ipv6_mc)
1541 pr_info(" mc_portmask_index: %d, mc_gip: %d, mc_sip: %d\n",
1542 e->mc_portmask_index, e->mc_gip, e->mc_sip);
1543 pr_info(" stack_dev: %d\n", e->stack_dev);
1544 if (e->next_hop)
1545 pr_info(" nh_route_id: %d\n", e->nh_route_id);
1546 }
1547
1548 static void rtl83xx_setup_l2_uc_entry(struct rtl838x_l2_entry *e, int port, int vid, u64 mac)
1549 {
1550 e->is_ip_mc = e->is_ipv6_mc = false;
1551 e->valid = true;
1552 e->age = 3;
1553 e->port = port,
1554 e->vid = vid;
1555 u64_to_ether_addr(mac, e->mac);
1556 }
1557
1558 static void rtl83xx_setup_l2_mc_entry(struct rtl838x_switch_priv *priv,
1559 struct rtl838x_l2_entry *e, int vid, u64 mac, int mc_group)
1560 {
1561 e->is_ip_mc = e->is_ipv6_mc = false;
1562 e->valid = true;
1563 e->mc_portmask_index = mc_group;
1564 e->type = L2_MULTICAST;
1565 e->rvid = e->vid = vid;
1566 pr_debug("%s: vid: %d, rvid: %d\n", __func__, e->vid, e->rvid);
1567 u64_to_ether_addr(mac, e->mac);
1568 }
1569
1570 /*
1571 * Uses the seed to identify a hash bucket in the L2 using the derived hash key and then loops
1572 * over the entries in the bucket until either a matching entry is found or an empty slot
1573 * Returns the filled in rtl838x_l2_entry and the index in the bucket when an entry was found
1574 * when an empty slot was found and must exist is false, the index of the slot is returned
1575 * when no slots are available returns -1
1576 */
1577 static int rtl83xx_find_l2_hash_entry(struct rtl838x_switch_priv *priv, u64 seed,
1578 bool must_exist, struct rtl838x_l2_entry *e)
1579 {
1580 int i, idx = -1;
1581 u32 key = priv->r->l2_hash_key(priv, seed);
1582 u64 entry;
1583
1584 pr_debug("%s: using key %x, for seed %016llx\n", __func__, key, seed);
1585 // Loop over all entries in the hash-bucket and over the second block on 93xx SoCs
1586 for (i = 0; i < priv->l2_bucket_size; i++) {
1587 entry = priv->r->read_l2_entry_using_hash(key, i, e);
1588 pr_debug("valid %d, mac %016llx\n", e->valid, ether_addr_to_u64(&e->mac[0]));
1589 if (must_exist && !e->valid)
1590 continue;
1591 if (!e->valid || ((entry & 0x0fffffffffffffffULL) == seed)) {
1592 idx = i > 3 ? ((key >> 14) & 0xffff) | i >> 1 : ((key << 2) | i) & 0xffff;
1593 break;
1594 }
1595 }
1596
1597 return idx;
1598 }
1599
1600 /*
1601 * Uses the seed to identify an entry in the CAM by looping over all its entries
1602 * Returns the filled in rtl838x_l2_entry and the index in the CAM when an entry was found
1603 * when an empty slot was found the index of the slot is returned
1604 * when no slots are available returns -1
1605 */
1606 static int rtl83xx_find_l2_cam_entry(struct rtl838x_switch_priv *priv, u64 seed,
1607 bool must_exist, struct rtl838x_l2_entry *e)
1608 {
1609 int i, idx = -1;
1610 u64 entry;
1611
1612 for (i = 0; i < 64; i++) {
1613 entry = priv->r->read_cam(i, e);
1614 if (!must_exist && !e->valid) {
1615 if (idx < 0) /* First empty entry? */
1616 idx = i;
1617 break;
1618 } else if ((entry & 0x0fffffffffffffffULL) == seed) {
1619 pr_debug("Found entry in CAM\n");
1620 idx = i;
1621 break;
1622 }
1623 }
1624 return idx;
1625 }
1626
1627 static int rtl83xx_port_fdb_add(struct dsa_switch *ds, int port,
1628 const unsigned char *addr, u16 vid)
1629 {
1630 struct rtl838x_switch_priv *priv = ds->priv;
1631 u64 mac = ether_addr_to_u64(addr);
1632 struct rtl838x_l2_entry e;
1633 int err = 0, idx;
1634 u64 seed = priv->r->l2_hash_seed(mac, vid);
1635
1636 if (priv->is_lagmember[port]) {
1637 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1638 return 0;
1639 }
1640
1641 mutex_lock(&priv->reg_mutex);
1642
1643 idx = rtl83xx_find_l2_hash_entry(priv, seed, false, &e);
1644
1645 // Found an existing or empty entry
1646 if (idx >= 0) {
1647 rtl83xx_setup_l2_uc_entry(&e, port, vid, mac);
1648 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1649 goto out;
1650 }
1651
1652 // Hash buckets full, try CAM
1653 rtl83xx_find_l2_cam_entry(priv, seed, false, &e);
1654
1655 if (idx >= 0) {
1656 rtl83xx_setup_l2_uc_entry(&e, port, vid, mac);
1657 priv->r->write_cam(idx, &e);
1658 goto out;
1659 }
1660
1661 err = -ENOTSUPP;
1662 out:
1663 mutex_unlock(&priv->reg_mutex);
1664 return err;
1665 }
1666
1667 static int rtl83xx_port_fdb_del(struct dsa_switch *ds, int port,
1668 const unsigned char *addr, u16 vid)
1669 {
1670 struct rtl838x_switch_priv *priv = ds->priv;
1671 u64 mac = ether_addr_to_u64(addr);
1672 struct rtl838x_l2_entry e;
1673 int err = 0, idx;
1674 u64 seed = priv->r->l2_hash_seed(mac, vid);
1675
1676 pr_info("In %s, mac %llx, vid: %d\n", __func__, mac, vid);
1677 mutex_lock(&priv->reg_mutex);
1678
1679 idx = rtl83xx_find_l2_hash_entry(priv, seed, true, &e);
1680
1681 pr_info("Found entry index %d, key %d and bucket %d\n", idx, idx >> 2, idx & 3);
1682 if (idx >= 0) {
1683 e.valid = false;
1684 dump_l2_entry(&e);
1685 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1686 goto out;
1687 }
1688
1689 /* Check CAM for spillover from hash buckets */
1690 rtl83xx_find_l2_cam_entry(priv, seed, true, &e);
1691
1692 if (idx >= 0) {
1693 e.valid = false;
1694 priv->r->write_cam(idx, &e);
1695 goto out;
1696 }
1697 err = -ENOENT;
1698 out:
1699 mutex_unlock(&priv->reg_mutex);
1700 return err;
1701 }
1702
1703 static int rtl83xx_port_fdb_dump(struct dsa_switch *ds, int port,
1704 dsa_fdb_dump_cb_t *cb, void *data)
1705 {
1706 struct rtl838x_l2_entry e;
1707 struct rtl838x_switch_priv *priv = ds->priv;
1708 int i;
1709 u32 fid, pkey;
1710 u64 mac;
1711
1712 mutex_lock(&priv->reg_mutex);
1713
1714 for (i = 0; i < priv->fib_entries; i++) {
1715 priv->r->read_l2_entry_using_hash(i >> 2, i & 0x3, &e);
1716
1717 if (!e.valid)
1718 continue;
1719
1720 if (e.port == port || e.port == RTL930X_PORT_IGNORE) {
1721 u64 seed;
1722 u32 key;
1723
1724 fid = ((i >> 2) & 0x3ff) | (e.rvid & ~0x3ff);
1725 mac = ether_addr_to_u64(&e.mac[0]);
1726 pkey = priv->r->l2_hash_key(priv, priv->r->l2_hash_seed(mac, fid));
1727 fid = (pkey & 0x3ff) | (fid & ~0x3ff);
1728 pr_info("-> index %d, key %x, bucket %d, dmac %016llx, fid: %x rvid: %x\n",
1729 i, i >> 2, i & 0x3, mac, fid, e.rvid);
1730 dump_l2_entry(&e);
1731 seed = priv->r->l2_hash_seed(mac, e.rvid);
1732 key = priv->r->l2_hash_key(priv, seed);
1733 pr_info("seed: %016llx, key based on rvid: %08x\n", seed, key);
1734 cb(e.mac, e.vid, e.is_static, data);
1735 }
1736 if (e.type == L2_MULTICAST) {
1737 u64 portmask = priv->r->read_mcast_pmask(e.mc_portmask_index);
1738
1739 if (portmask & BIT_ULL(port)) {
1740 dump_l2_entry(&e);
1741 pr_info(" PM: %016llx\n", portmask);
1742 }
1743 }
1744 }
1745
1746 for (i = 0; i < 64; i++) {
1747 priv->r->read_cam(i, &e);
1748
1749 if (!e.valid)
1750 continue;
1751
1752 if (e.port == port)
1753 cb(e.mac, e.vid, e.is_static, data);
1754 }
1755
1756 mutex_unlock(&priv->reg_mutex);
1757 return 0;
1758 }
1759
1760 static int rtl83xx_port_mdb_prepare(struct dsa_switch *ds, int port,
1761 const struct switchdev_obj_port_mdb *mdb)
1762 {
1763 struct rtl838x_switch_priv *priv = ds->priv;
1764
1765 if (priv->id >= 0x9300)
1766 return -EOPNOTSUPP;
1767
1768 return 0;
1769 }
1770
1771 static void rtl83xx_port_mdb_add(struct dsa_switch *ds, int port,
1772 const struct switchdev_obj_port_mdb *mdb)
1773 {
1774 struct rtl838x_switch_priv *priv = ds->priv;
1775 u64 mac = ether_addr_to_u64(mdb->addr);
1776 struct rtl838x_l2_entry e;
1777 int err = 0, idx;
1778 int vid = mdb->vid;
1779 u64 seed = priv->r->l2_hash_seed(mac, vid);
1780 int mc_group;
1781
1782 pr_debug("In %s port %d, mac %llx, vid: %d\n", __func__, port, mac, vid);
1783
1784 if (priv->is_lagmember[port]) {
1785 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1786 return;
1787 }
1788
1789 mutex_lock(&priv->reg_mutex);
1790
1791 idx = rtl83xx_find_l2_hash_entry(priv, seed, false, &e);
1792
1793 // Found an existing or empty entry
1794 if (idx >= 0) {
1795 if (e.valid) {
1796 pr_debug("Found an existing entry %016llx, mc_group %d\n",
1797 ether_addr_to_u64(e.mac), e.mc_portmask_index);
1798 rtl83xx_mc_group_add_port(priv, e.mc_portmask_index, port);
1799 } else {
1800 pr_debug("New entry for seed %016llx\n", seed);
1801 mc_group = rtl83xx_mc_group_alloc(priv, port);
1802 if (mc_group < 0) {
1803 err = -ENOTSUPP;
1804 goto out;
1805 }
1806 rtl83xx_setup_l2_mc_entry(priv, &e, vid, mac, mc_group);
1807 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1808 }
1809 goto out;
1810 }
1811
1812 // Hash buckets full, try CAM
1813 rtl83xx_find_l2_cam_entry(priv, seed, false, &e);
1814
1815 if (idx >= 0) {
1816 if (e.valid) {
1817 pr_debug("Found existing CAM entry %016llx, mc_group %d\n",
1818 ether_addr_to_u64(e.mac), e.mc_portmask_index);
1819 rtl83xx_mc_group_add_port(priv, e.mc_portmask_index, port);
1820 } else {
1821 pr_debug("New entry\n");
1822 mc_group = rtl83xx_mc_group_alloc(priv, port);
1823 if (mc_group < 0) {
1824 err = -ENOTSUPP;
1825 goto out;
1826 }
1827 rtl83xx_setup_l2_mc_entry(priv, &e, vid, mac, mc_group);
1828 priv->r->write_cam(idx, &e);
1829 }
1830 goto out;
1831 }
1832
1833 err = -ENOTSUPP;
1834 out:
1835 mutex_unlock(&priv->reg_mutex);
1836 if (err)
1837 dev_err(ds->dev, "failed to add MDB entry\n");
1838 }
1839
1840 int rtl83xx_port_mdb_del(struct dsa_switch *ds, int port,
1841 const struct switchdev_obj_port_mdb *mdb)
1842 {
1843 struct rtl838x_switch_priv *priv = ds->priv;
1844 u64 mac = ether_addr_to_u64(mdb->addr);
1845 struct rtl838x_l2_entry e;
1846 int err = 0, idx;
1847 int vid = mdb->vid;
1848 u64 seed = priv->r->l2_hash_seed(mac, vid);
1849 u64 portmask;
1850
1851 pr_debug("In %s, port %d, mac %llx, vid: %d\n", __func__, port, mac, vid);
1852
1853 if (priv->is_lagmember[port]) {
1854 pr_info("%s: %d is lag slave. ignore\n", __func__, port);
1855 return 0;
1856 }
1857
1858 mutex_lock(&priv->reg_mutex);
1859
1860 idx = rtl83xx_find_l2_hash_entry(priv, seed, true, &e);
1861
1862 pr_debug("Found entry index %d, key %d and bucket %d\n", idx, idx >> 2, idx & 3);
1863 if (idx >= 0) {
1864 portmask = rtl83xx_mc_group_del_port(priv, e.mc_portmask_index, port);
1865 if (!portmask) {
1866 e.valid = false;
1867 // dump_l2_entry(&e);
1868 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1869 }
1870 goto out;
1871 }
1872
1873 /* Check CAM for spillover from hash buckets */
1874 rtl83xx_find_l2_cam_entry(priv, seed, true, &e);
1875
1876 if (idx >= 0) {
1877 portmask = rtl83xx_mc_group_del_port(priv, e.mc_portmask_index, port);
1878 if (!portmask) {
1879 e.valid = false;
1880 // dump_l2_entry(&e);
1881 priv->r->write_cam(idx, &e);
1882 }
1883 goto out;
1884 }
1885 // TODO: Re-enable with a newer kernel: err = -ENOENT;
1886 out:
1887 mutex_unlock(&priv->reg_mutex);
1888 return err;
1889 }
1890
1891 static int rtl83xx_port_mirror_add(struct dsa_switch *ds, int port,
1892 struct dsa_mall_mirror_tc_entry *mirror,
1893 bool ingress)
1894 {
1895 /* We support 4 mirror groups, one destination port per group */
1896 int group;
1897 struct rtl838x_switch_priv *priv = ds->priv;
1898 int ctrl_reg, dpm_reg, spm_reg;
1899
1900 pr_debug("In %s\n", __func__);
1901
1902 for (group = 0; group < 4; group++) {
1903 if (priv->mirror_group_ports[group] == mirror->to_local_port)
1904 break;
1905 }
1906 if (group >= 4) {
1907 for (group = 0; group < 4; group++) {
1908 if (priv->mirror_group_ports[group] < 0)
1909 break;
1910 }
1911 }
1912
1913 if (group >= 4)
1914 return -ENOSPC;
1915
1916 ctrl_reg = priv->r->mir_ctrl + group * 4;
1917 dpm_reg = priv->r->mir_dpm + group * 4 * priv->port_width;
1918 spm_reg = priv->r->mir_spm + group * 4 * priv->port_width;
1919
1920 pr_debug("Using group %d\n", group);
1921 mutex_lock(&priv->reg_mutex);
1922
1923 if (priv->family_id == RTL8380_FAMILY_ID) {
1924 /* Enable mirroring to port across VLANs (bit 11) */
1925 sw_w32(1 << 11 | (mirror->to_local_port << 4) | 1, ctrl_reg);
1926 } else {
1927 /* Enable mirroring to destination port */
1928 sw_w32((mirror->to_local_port << 4) | 1, ctrl_reg);
1929 }
1930
1931 if (ingress && (priv->r->get_port_reg_be(spm_reg) & (1ULL << port))) {
1932 mutex_unlock(&priv->reg_mutex);
1933 return -EEXIST;
1934 }
1935 if ((!ingress) && (priv->r->get_port_reg_be(dpm_reg) & (1ULL << port))) {
1936 mutex_unlock(&priv->reg_mutex);
1937 return -EEXIST;
1938 }
1939
1940 if (ingress)
1941 priv->r->mask_port_reg_be(0, 1ULL << port, spm_reg);
1942 else
1943 priv->r->mask_port_reg_be(0, 1ULL << port, dpm_reg);
1944
1945 priv->mirror_group_ports[group] = mirror->to_local_port;
1946 mutex_unlock(&priv->reg_mutex);
1947 return 0;
1948 }
1949
1950 static void rtl83xx_port_mirror_del(struct dsa_switch *ds, int port,
1951 struct dsa_mall_mirror_tc_entry *mirror)
1952 {
1953 int group = 0;
1954 struct rtl838x_switch_priv *priv = ds->priv;
1955 int ctrl_reg, dpm_reg, spm_reg;
1956
1957 pr_debug("In %s\n", __func__);
1958 for (group = 0; group < 4; group++) {
1959 if (priv->mirror_group_ports[group] == mirror->to_local_port)
1960 break;
1961 }
1962 if (group >= 4)
1963 return;
1964
1965 ctrl_reg = priv->r->mir_ctrl + group * 4;
1966 dpm_reg = priv->r->mir_dpm + group * 4 * priv->port_width;
1967 spm_reg = priv->r->mir_spm + group * 4 * priv->port_width;
1968
1969 mutex_lock(&priv->reg_mutex);
1970 if (mirror->ingress) {
1971 /* Ingress, clear source port matrix */
1972 priv->r->mask_port_reg_be(1ULL << port, 0, spm_reg);
1973 } else {
1974 /* Egress, clear destination port matrix */
1975 priv->r->mask_port_reg_be(1ULL << port, 0, dpm_reg);
1976 }
1977
1978 if (!(sw_r32(spm_reg) || sw_r32(dpm_reg))) {
1979 priv->mirror_group_ports[group] = -1;
1980 sw_w32(0, ctrl_reg);
1981 }
1982
1983 mutex_unlock(&priv->reg_mutex);
1984 }
1985
1986 static int rtl83xx_port_pre_bridge_flags(struct dsa_switch *ds, int port, unsigned long flags, struct netlink_ext_ack *extack)
1987 {
1988 struct rtl838x_switch_priv *priv = ds->priv;
1989 unsigned long features = 0;
1990 pr_debug("%s: %d %lX\n", __func__, port, flags);
1991 if (priv->r->enable_learning)
1992 features |= BR_LEARNING;
1993 if (priv->r->enable_flood)
1994 features |= BR_FLOOD;
1995 if (priv->r->enable_mcast_flood)
1996 features |= BR_MCAST_FLOOD;
1997 if (priv->r->enable_bcast_flood)
1998 features |= BR_BCAST_FLOOD;
1999 if (flags & ~(features))
2000 return -EINVAL;
2001
2002 return 0;
2003 }
2004
2005 static int rtl83xx_port_bridge_flags(struct dsa_switch *ds, int port, unsigned long flags, struct netlink_ext_ack *extack)
2006 {
2007 struct rtl838x_switch_priv *priv = ds->priv;
2008
2009 pr_debug("%s: %d %lX\n", __func__, port, flags);
2010 if (priv->r->enable_learning)
2011 priv->r->enable_learning(port, !!(flags & BR_LEARNING));
2012
2013 if (priv->r->enable_flood)
2014 priv->r->enable_flood(port, !!(flags & BR_FLOOD));
2015
2016 if (priv->r->enable_mcast_flood)
2017 priv->r->enable_mcast_flood(port, !!(flags & BR_MCAST_FLOOD));
2018
2019 if (priv->r->enable_bcast_flood)
2020 priv->r->enable_bcast_flood(port, !!(flags & BR_BCAST_FLOOD));
2021
2022 return 0;
2023 }
2024
2025 static bool rtl83xx_lag_can_offload(struct dsa_switch *ds,
2026 struct net_device *lag,
2027 struct netdev_lag_upper_info *info)
2028 {
2029 int id;
2030
2031 id = dsa_lag_id(ds->dst, lag);
2032 if (id < 0 || id >= ds->num_lag_ids)
2033 return false;
2034
2035 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
2036 return false;
2037 }
2038 if (info->hash_type != NETDEV_LAG_HASH_L2 && info->hash_type != NETDEV_LAG_HASH_L23)
2039 return false;
2040
2041 return true;
2042 }
2043
2044 static int rtl83xx_port_lag_change(struct dsa_switch *ds, int port)
2045 {
2046 struct rtl838x_switch_priv *priv = ds->priv;
2047
2048 pr_debug("%s: %d\n", __func__, port);
2049 // Nothing to be done...
2050
2051 return 0;
2052 }
2053
2054 static int rtl83xx_port_lag_join(struct dsa_switch *ds, int port,
2055 struct net_device *lag,
2056 struct netdev_lag_upper_info *info)
2057 {
2058 struct rtl838x_switch_priv *priv = ds->priv;
2059 int i, err = 0;
2060
2061 if (!rtl83xx_lag_can_offload(ds, lag, info))
2062 return -EOPNOTSUPP;
2063
2064 mutex_lock(&priv->reg_mutex);
2065
2066 for (i = 0; i < priv->n_lags; i++) {
2067 if ((!priv->lag_devs[i]) || (priv->lag_devs[i] == lag))
2068 break;
2069 }
2070 if (port >= priv->cpu_port) {
2071 err = -EINVAL;
2072 goto out;
2073 }
2074 pr_info("port_lag_join: group %d, port %d\n",i, port);
2075 if (!priv->lag_devs[i])
2076 priv->lag_devs[i] = lag;
2077
2078 if (priv->lag_primary[i]==-1) {
2079 priv->lag_primary[i]=port;
2080 } else
2081 priv->is_lagmember[port] = 1;
2082
2083 priv->lagmembers |= (1ULL << port);
2084
2085 pr_debug("lag_members = %llX\n", priv->lagmembers);
2086 err = rtl83xx_lag_add(priv->ds, i, port, info);
2087 if (err) {
2088 err = -EINVAL;
2089 goto out;
2090 }
2091
2092 out:
2093 mutex_unlock(&priv->reg_mutex);
2094 return err;
2095
2096 }
2097
2098 static int rtl83xx_port_lag_leave(struct dsa_switch *ds, int port,
2099 struct net_device *lag)
2100 {
2101 int i, group = -1, err;
2102 struct rtl838x_switch_priv *priv = ds->priv;
2103
2104 mutex_lock(&priv->reg_mutex);
2105 for (i=0;i<priv->n_lags;i++) {
2106 if (priv->lags_port_members[i] & BIT_ULL(port)) {
2107 group = i;
2108 break;
2109 }
2110 }
2111
2112 if (group == -1) {
2113 pr_info("port_lag_leave: port %d is not a member\n", port);
2114 err = -EINVAL;
2115 goto out;
2116 }
2117
2118 if (port >= priv->cpu_port) {
2119 err = -EINVAL;
2120 goto out;
2121 }
2122 pr_info("port_lag_del: group %d, port %d\n",group, port);
2123 priv->lagmembers &=~ (1ULL << port);
2124 priv->lag_primary[i] = -1;
2125 priv->is_lagmember[port] = 0;
2126 pr_debug("lag_members = %llX\n", priv->lagmembers);
2127 err = rtl83xx_lag_del(priv->ds, group, port);
2128 if (err) {
2129 err = -EINVAL;
2130 goto out;
2131 }
2132 if (!priv->lags_port_members[i])
2133 priv->lag_devs[i] = NULL;
2134
2135 out:
2136 mutex_unlock(&priv->reg_mutex);
2137 return 0;
2138 }
2139
2140 int dsa_phy_read(struct dsa_switch *ds, int phy_addr, int phy_reg)
2141 {
2142 u32 val;
2143 u32 offset = 0;
2144 struct rtl838x_switch_priv *priv = ds->priv;
2145
2146 if (phy_addr >= 24 && phy_addr <= 27
2147 && priv->ports[24].phy == PHY_RTL838X_SDS) {
2148 if (phy_addr == 26)
2149 offset = 0x100;
2150 val = sw_r32(RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2)) & 0xffff;
2151 return val;
2152 }
2153
2154 read_phy(phy_addr, 0, phy_reg, &val);
2155 return val;
2156 }
2157
2158 int dsa_phy_write(struct dsa_switch *ds, int phy_addr, int phy_reg, u16 val)
2159 {
2160 u32 offset = 0;
2161 struct rtl838x_switch_priv *priv = ds->priv;
2162
2163 if (phy_addr >= 24 && phy_addr <= 27
2164 && priv->ports[24].phy == PHY_RTL838X_SDS) {
2165 if (phy_addr == 26)
2166 offset = 0x100;
2167 sw_w32(val, RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2));
2168 return 0;
2169 }
2170 return write_phy(phy_addr, 0, phy_reg, val);
2171 }
2172
2173 const struct dsa_switch_ops rtl83xx_switch_ops = {
2174 .get_tag_protocol = rtl83xx_get_tag_protocol,
2175 .setup = rtl83xx_setup,
2176
2177 .phy_read = dsa_phy_read,
2178 .phy_write = dsa_phy_write,
2179
2180 .phylink_validate = rtl83xx_phylink_validate,
2181 .phylink_mac_link_state = rtl83xx_phylink_mac_link_state,
2182 .phylink_mac_config = rtl83xx_phylink_mac_config,
2183 .phylink_mac_link_down = rtl83xx_phylink_mac_link_down,
2184 .phylink_mac_link_up = rtl83xx_phylink_mac_link_up,
2185
2186 .get_strings = rtl83xx_get_strings,
2187 .get_ethtool_stats = rtl83xx_get_ethtool_stats,
2188 .get_sset_count = rtl83xx_get_sset_count,
2189
2190 .port_enable = rtl83xx_port_enable,
2191 .port_disable = rtl83xx_port_disable,
2192
2193 .get_mac_eee = rtl83xx_get_mac_eee,
2194 .set_mac_eee = rtl83xx_set_mac_eee,
2195
2196 .set_ageing_time = rtl83xx_set_ageing_time,
2197 .port_bridge_join = rtl83xx_port_bridge_join,
2198 .port_bridge_leave = rtl83xx_port_bridge_leave,
2199 .port_stp_state_set = rtl83xx_port_stp_state_set,
2200 .port_fast_age = rtl83xx_fast_age,
2201
2202 .port_vlan_filtering = rtl83xx_vlan_filtering,
2203 .port_vlan_prepare = rtl83xx_vlan_prepare,
2204 .port_vlan_add = rtl83xx_vlan_add,
2205 .port_vlan_del = rtl83xx_vlan_del,
2206
2207 .port_fdb_add = rtl83xx_port_fdb_add,
2208 .port_fdb_del = rtl83xx_port_fdb_del,
2209 .port_fdb_dump = rtl83xx_port_fdb_dump,
2210
2211 .port_mdb_prepare = rtl83xx_port_mdb_prepare,
2212 .port_mdb_add = rtl83xx_port_mdb_add,
2213 .port_mdb_del = rtl83xx_port_mdb_del,
2214
2215 .port_mirror_add = rtl83xx_port_mirror_add,
2216 .port_mirror_del = rtl83xx_port_mirror_del,
2217
2218 .port_lag_change = rtl83xx_port_lag_change,
2219 .port_lag_join = rtl83xx_port_lag_join,
2220 .port_lag_leave = rtl83xx_port_lag_leave,
2221
2222 .port_pre_bridge_flags = rtl83xx_port_pre_bridge_flags,
2223 .port_bridge_flags = rtl83xx_port_bridge_flags,
2224 };
2225
2226 const struct dsa_switch_ops rtl930x_switch_ops = {
2227 .get_tag_protocol = rtl83xx_get_tag_protocol,
2228 .setup = rtl93xx_setup,
2229
2230 .phy_read = dsa_phy_read,
2231 .phy_write = dsa_phy_write,
2232
2233 .phylink_validate = rtl93xx_phylink_validate,
2234 .phylink_mac_link_state = rtl93xx_phylink_mac_link_state,
2235 .phylink_mac_config = rtl93xx_phylink_mac_config,
2236 .phylink_mac_link_down = rtl93xx_phylink_mac_link_down,
2237 .phylink_mac_link_up = rtl93xx_phylink_mac_link_up,
2238
2239 .get_strings = rtl83xx_get_strings,
2240 .get_ethtool_stats = rtl83xx_get_ethtool_stats,
2241 .get_sset_count = rtl83xx_get_sset_count,
2242
2243 .port_enable = rtl83xx_port_enable,
2244 .port_disable = rtl83xx_port_disable,
2245
2246 .get_mac_eee = rtl93xx_get_mac_eee,
2247 .set_mac_eee = rtl83xx_set_mac_eee,
2248
2249 .set_ageing_time = rtl83xx_set_ageing_time,
2250 .port_bridge_join = rtl83xx_port_bridge_join,
2251 .port_bridge_leave = rtl83xx_port_bridge_leave,
2252 .port_stp_state_set = rtl83xx_port_stp_state_set,
2253 .port_fast_age = rtl930x_fast_age,
2254
2255 .port_vlan_filtering = rtl83xx_vlan_filtering,
2256 .port_vlan_prepare = rtl83xx_vlan_prepare,
2257 .port_vlan_add = rtl83xx_vlan_add,
2258 .port_vlan_del = rtl83xx_vlan_del,
2259
2260 .port_fdb_add = rtl83xx_port_fdb_add,
2261 .port_fdb_del = rtl83xx_port_fdb_del,
2262 .port_fdb_dump = rtl83xx_port_fdb_dump,
2263
2264 .port_mdb_prepare = rtl83xx_port_mdb_prepare,
2265 .port_mdb_add = rtl83xx_port_mdb_add,
2266 .port_mdb_del = rtl83xx_port_mdb_del,
2267
2268 .port_lag_change = rtl83xx_port_lag_change,
2269 .port_lag_join = rtl83xx_port_lag_join,
2270 .port_lag_leave = rtl83xx_port_lag_leave,
2271
2272 .port_pre_bridge_flags = rtl83xx_port_pre_bridge_flags,
2273 .port_bridge_flags = rtl83xx_port_bridge_flags,
2274 };
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