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92426be1f3adf9e6a71877667aeee076fba00206
[openwrt/staging/wigyori.git] / target / linux / realtek / files-5.10 / drivers / net / dsa / rtl83xx / rtl930x.c
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <asm/mach-rtl838x/mach-rtl83xx.h>
4 #include <linux/inetdevice.h>
5
6 #include "rtl83xx.h"
7
8 extern struct mutex smi_lock;
9 extern struct rtl83xx_soc_info soc_info;
10
11 /* Definition of the RTL930X-specific template field IDs as used in the PIE */
12 enum template_field_id {
13 TEMPLATE_FIELD_SPM0 = 0, // Source portmask ports 0-15
14 TEMPLATE_FIELD_SPM1 = 1, // Source portmask ports 16-31
15 TEMPLATE_FIELD_DMAC0 = 2, // Destination MAC [15:0]
16 TEMPLATE_FIELD_DMAC1 = 3, // Destination MAC [31:16]
17 TEMPLATE_FIELD_DMAC2 = 4, // Destination MAC [47:32]
18 TEMPLATE_FIELD_SMAC0 = 5, // Source MAC [15:0]
19 TEMPLATE_FIELD_SMAC1 = 6, // Source MAC [31:16]
20 TEMPLATE_FIELD_SMAC2 = 7, // Source MAC [47:32]
21 TEMPLATE_FIELD_ETHERTYPE = 8, // Ethernet frame type field
22 TEMPLATE_FIELD_OTAG = 9,
23 TEMPLATE_FIELD_ITAG = 10,
24 TEMPLATE_FIELD_SIP0 = 11,
25 TEMPLATE_FIELD_SIP1 = 12,
26 TEMPLATE_FIELD_DIP0 = 13,
27 TEMPLATE_FIELD_DIP1 = 14,
28 TEMPLATE_FIELD_IP_TOS_PROTO = 15,
29 TEMPLATE_FIELD_L4_SPORT = 16,
30 TEMPLATE_FIELD_L4_DPORT = 17,
31 TEMPLATE_FIELD_L34_HEADER = 18,
32 TEMPLATE_FIELD_TCP_INFO = 19,
33 TEMPLATE_FIELD_FIELD_SELECTOR_VALID = 20,
34 TEMPLATE_FIELD_FIELD_SELECTOR_0 = 21,
35 TEMPLATE_FIELD_FIELD_SELECTOR_1 = 22,
36 TEMPLATE_FIELD_FIELD_SELECTOR_2 = 23,
37 TEMPLATE_FIELD_FIELD_SELECTOR_3 = 24,
38 TEMPLATE_FIELD_FIELD_SELECTOR_4 = 25,
39 TEMPLATE_FIELD_FIELD_SELECTOR_5 = 26,
40 TEMPLATE_FIELD_SIP2 = 27,
41 TEMPLATE_FIELD_SIP3 = 28,
42 TEMPLATE_FIELD_SIP4 = 29,
43 TEMPLATE_FIELD_SIP5 = 30,
44 TEMPLATE_FIELD_SIP6 = 31,
45 TEMPLATE_FIELD_SIP7 = 32,
46 TEMPLATE_FIELD_DIP2 = 33,
47 TEMPLATE_FIELD_DIP3 = 34,
48 TEMPLATE_FIELD_DIP4 = 35,
49 TEMPLATE_FIELD_DIP5 = 36,
50 TEMPLATE_FIELD_DIP6 = 37,
51 TEMPLATE_FIELD_DIP7 = 38,
52 TEMPLATE_FIELD_PKT_INFO = 39,
53 TEMPLATE_FIELD_FLOW_LABEL = 40,
54 TEMPLATE_FIELD_DSAP_SSAP = 41,
55 TEMPLATE_FIELD_SNAP_OUI = 42,
56 TEMPLATE_FIELD_FWD_VID = 43,
57 TEMPLATE_FIELD_RANGE_CHK = 44,
58 TEMPLATE_FIELD_VLAN_GMSK = 45, // VLAN Group Mask/IP range check
59 TEMPLATE_FIELD_DLP = 46,
60 TEMPLATE_FIELD_META_DATA = 47,
61 TEMPLATE_FIELD_SRC_FWD_VID = 48,
62 TEMPLATE_FIELD_SLP = 49,
63 };
64
65 /* The meaning of TEMPLATE_FIELD_VLAN depends on phase and the configuration in
66 * RTL930X_PIE_CTRL. We use always the same definition and map to the inner VLAN tag:
67 */
68 #define TEMPLATE_FIELD_VLAN TEMPLATE_FIELD_ITAG
69
70 // Number of fixed templates predefined in the RTL9300 SoC
71 #define N_FIXED_TEMPLATES 5
72 // RTL9300 specific predefined templates
73 static enum template_field_id fixed_templates[N_FIXED_TEMPLATES][N_FIXED_FIELDS] =
74 {
75 {
76 TEMPLATE_FIELD_DMAC0, TEMPLATE_FIELD_DMAC1, TEMPLATE_FIELD_DMAC2,
77 TEMPLATE_FIELD_SMAC0, TEMPLATE_FIELD_SMAC1, TEMPLATE_FIELD_SMAC2,
78 TEMPLATE_FIELD_VLAN, TEMPLATE_FIELD_IP_TOS_PROTO, TEMPLATE_FIELD_DSAP_SSAP,
79 TEMPLATE_FIELD_ETHERTYPE, TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1
80 }, {
81 TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_DIP0,
82 TEMPLATE_FIELD_DIP1, TEMPLATE_FIELD_IP_TOS_PROTO, TEMPLATE_FIELD_TCP_INFO,
83 TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_L4_DPORT, TEMPLATE_FIELD_VLAN,
84 TEMPLATE_FIELD_RANGE_CHK, TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1
85 }, {
86 TEMPLATE_FIELD_DMAC0, TEMPLATE_FIELD_DMAC1, TEMPLATE_FIELD_DMAC2,
87 TEMPLATE_FIELD_VLAN, TEMPLATE_FIELD_ETHERTYPE, TEMPLATE_FIELD_IP_TOS_PROTO,
88 TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_DIP0,
89 TEMPLATE_FIELD_DIP1, TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_L4_DPORT
90 }, {
91 TEMPLATE_FIELD_DIP0, TEMPLATE_FIELD_DIP1, TEMPLATE_FIELD_DIP2,
92 TEMPLATE_FIELD_DIP3, TEMPLATE_FIELD_DIP4, TEMPLATE_FIELD_DIP5,
93 TEMPLATE_FIELD_DIP6, TEMPLATE_FIELD_DIP7, TEMPLATE_FIELD_IP_TOS_PROTO,
94 TEMPLATE_FIELD_TCP_INFO, TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_L4_DPORT
95 }, {
96 TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_SIP2,
97 TEMPLATE_FIELD_SIP3, TEMPLATE_FIELD_SIP4, TEMPLATE_FIELD_SIP5,
98 TEMPLATE_FIELD_SIP6, TEMPLATE_FIELD_SIP7, TEMPLATE_FIELD_VLAN,
99 TEMPLATE_FIELD_RANGE_CHK, TEMPLATE_FIELD_SPM1, TEMPLATE_FIELD_SPM1
100 },
101 };
102
103 void rtl930x_print_matrix(void)
104 {
105 int i;
106 struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 6);
107
108 for (i = 0; i < 29; i++) {
109 rtl_table_read(r, i);
110 pr_debug("> %08x\n", sw_r32(rtl_table_data(r, 0)));
111 }
112 rtl_table_release(r);
113 }
114
115 inline void rtl930x_exec_tbl0_cmd(u32 cmd)
116 {
117 sw_w32(cmd, RTL930X_TBL_ACCESS_CTRL_0);
118 do { } while (sw_r32(RTL930X_TBL_ACCESS_CTRL_0) & (1 << 17));
119 }
120
121 inline void rtl930x_exec_tbl1_cmd(u32 cmd)
122 {
123 sw_w32(cmd, RTL930X_TBL_ACCESS_CTRL_1);
124 do { } while (sw_r32(RTL930X_TBL_ACCESS_CTRL_1) & (1 << 17));
125 }
126
127 inline int rtl930x_tbl_access_data_0(int i)
128 {
129 return RTL930X_TBL_ACCESS_DATA_0(i);
130 }
131
132 static inline int rtl930x_l2_port_new_salrn(int p)
133 {
134 return RTL930X_L2_PORT_SALRN(p);
135 }
136
137 static inline int rtl930x_l2_port_new_sa_fwd(int p)
138 {
139 // TODO: The definition of the fields changed, because of the master-cpu in a stack
140 return RTL930X_L2_PORT_NEW_SA_FWD(p);
141 }
142
143 inline static int rtl930x_trk_mbr_ctr(int group)
144 {
145 return RTL930X_TRK_MBR_CTRL + (group << 2);
146 }
147
148 static void rtl930x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info)
149 {
150 u32 v, w;
151 // Read VLAN table (1) via register 0
152 struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 1);
153
154 rtl_table_read(r, vlan);
155 v = sw_r32(rtl_table_data(r, 0));
156 w = sw_r32(rtl_table_data(r, 1));
157 pr_debug("VLAN_READ %d: %08x %08x\n", vlan, v, w);
158 rtl_table_release(r);
159
160 info->tagged_ports = v >> 3;
161 info->profile_id = (w >> 24) & 7;
162 info->hash_mc_fid = !!(w & BIT(27));
163 info->hash_uc_fid = !!(w & BIT(28));
164 info->fid = ((v & 0x7) << 3) | ((w >> 29) & 0x7);
165
166 // Read UNTAG table via table register 2
167 r = rtl_table_get(RTL9300_TBL_2, 0);
168 rtl_table_read(r, vlan);
169 v = sw_r32(rtl_table_data(r, 0));
170 rtl_table_release(r);
171
172 info->untagged_ports = v >> 3;
173 }
174
175 static void rtl930x_vlan_set_tagged(u32 vlan, struct rtl838x_vlan_info *info)
176 {
177 u32 v, w;
178 // Access VLAN table (1) via register 0
179 struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 1);
180
181 v = info->tagged_ports << 3;
182 v |= ((u32)info->fid) >> 3;
183
184 w = ((u32)info->fid) << 29;
185 w |= info->hash_mc_fid ? BIT(27) : 0;
186 w |= info->hash_uc_fid ? BIT(28) : 0;
187 w |= info->profile_id << 24;
188
189 sw_w32(v, rtl_table_data(r, 0));
190 sw_w32(w, rtl_table_data(r, 1));
191
192 rtl_table_write(r, vlan);
193 rtl_table_release(r);
194 }
195
196 void rtl930x_vlan_profile_dump(int profile)
197 {
198 u32 p[5];
199
200 if (profile < 0 || profile > 7)
201 return;
202
203 p[0] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile));
204 p[1] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile) + 4);
205 p[2] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile) + 8) & 0x1FFFFFFF;
206 p[3] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile) + 12) & 0x1FFFFFFF;
207 p[4] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile) + 16) & 0x1FFFFFFF;
208
209 pr_info("VLAN %d: L2 learn: %d; Unknown MC PMasks: L2 %0x, IPv4 %0x, IPv6: %0x",
210 profile, p[0] & (3 << 21), p[2], p[3], p[4]);
211 pr_info(" Routing enabled: IPv4 UC %c, IPv6 UC %c, IPv4 MC %c, IPv6 MC %c\n",
212 p[0] & BIT(17) ? 'y' : 'n', p[0] & BIT(16) ? 'y' : 'n',
213 p[0] & BIT(13) ? 'y' : 'n', p[0] & BIT(12) ? 'y' : 'n');
214 pr_info(" Bridge enabled: IPv4 MC %c, IPv6 MC %c,\n",
215 p[0] & BIT(15) ? 'y' : 'n', p[0] & BIT(14) ? 'y' : 'n');
216 pr_info("VLAN profile %d: raw %08x %08x %08x %08x %08x\n",
217 profile, p[0], p[1], p[2], p[3], p[4]);
218 }
219
220 static void rtl930x_vlan_set_untagged(u32 vlan, u64 portmask)
221 {
222 struct table_reg *r = rtl_table_get(RTL9300_TBL_2, 0);
223
224 sw_w32(portmask << 3, rtl_table_data(r, 0));
225 rtl_table_write(r, vlan);
226 rtl_table_release(r);
227 }
228
229 /* Sets the L2 forwarding to be based on either the inner VLAN tag or the outer
230 */
231 static void rtl930x_vlan_fwd_on_inner(int port, bool is_set)
232 {
233 // Always set all tag modes to fwd based on either inner or outer tag
234 if (is_set)
235 sw_w32_mask(0, 0xf, RTL930X_VLAN_PORT_FWD + (port << 2));
236 else
237 sw_w32_mask(0xf, 0, RTL930X_VLAN_PORT_FWD + (port << 2));
238 }
239
240 static void rtl930x_vlan_profile_setup(int profile)
241 {
242 u32 p[5];
243
244 pr_info("In %s\n", __func__);
245 p[0] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile));
246 p[1] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile) + 4);
247
248 // Enable routing of Ipv4/6 Unicast and IPv4/6 Multicast traffic
249 p[0] |= BIT(17) | BIT(16) | BIT(13) | BIT(12);
250 p[2] = 0x1fffffff; // L2 unknown MC flooding portmask all ports, including the CPU-port
251 p[3] = 0x1fffffff; // IPv4 unknown MC flooding portmask
252 p[4] = 0x1fffffff; // IPv6 unknown MC flooding portmask
253
254 sw_w32(p[0], RTL930X_VLAN_PROFILE_SET(profile));
255 sw_w32(p[1], RTL930X_VLAN_PROFILE_SET(profile) + 4);
256 sw_w32(p[2], RTL930X_VLAN_PROFILE_SET(profile) + 8);
257 sw_w32(p[3], RTL930X_VLAN_PROFILE_SET(profile) + 12);
258 sw_w32(p[4], RTL930X_VLAN_PROFILE_SET(profile) + 16);
259 }
260
261 static void rtl930x_l2_learning_setup(void)
262 {
263 // Portmask for flooding broadcast traffic
264 sw_w32(0x1fffffff, RTL930X_L2_BC_FLD_PMSK);
265
266 // Portmask for flooding unicast traffic with unknown destination
267 sw_w32(0x1fffffff, RTL930X_L2_UNKN_UC_FLD_PMSK);
268
269 // Limit learning to maximum: 32k entries, after that just flood (bits 0-1)
270 sw_w32((0x7fff << 2) | 0, RTL930X_L2_LRN_CONSTRT_CTRL);
271 }
272
273 static void rtl930x_stp_get(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])
274 {
275 int i;
276 u32 cmd = 1 << 17 /* Execute cmd */
277 | 0 << 16 /* Read */
278 | 4 << 12 /* Table type 0b10 */
279 | (msti & 0xfff);
280 priv->r->exec_tbl0_cmd(cmd);
281
282 for (i = 0; i < 2; i++)
283 port_state[i] = sw_r32(RTL930X_TBL_ACCESS_DATA_0(i));
284 pr_debug("MSTI: %d STATE: %08x, %08x\n", msti, port_state[0], port_state[1]);
285 }
286
287 static void rtl930x_stp_set(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])
288 {
289 int i;
290 u32 cmd = 1 << 17 /* Execute cmd */
291 | 1 << 16 /* Write */
292 | 4 << 12 /* Table type 4 */
293 | (msti & 0xfff);
294
295 for (i = 0; i < 2; i++)
296 sw_w32(port_state[i], RTL930X_TBL_ACCESS_DATA_0(i));
297 priv->r->exec_tbl0_cmd(cmd);
298 }
299
300 static inline int rtl930x_mac_force_mode_ctrl(int p)
301 {
302 return RTL930X_MAC_FORCE_MODE_CTRL + (p << 2);
303 }
304
305 static inline int rtl930x_mac_port_ctrl(int p)
306 {
307 return RTL930X_MAC_L2_PORT_CTRL(p);
308 }
309
310 static inline int rtl930x_mac_link_spd_sts(int p)
311 {
312 return RTL930X_MAC_LINK_SPD_STS(p);
313 }
314
315 static u64 rtl930x_l2_hash_seed(u64 mac, u32 vid)
316 {
317 u64 v = vid;
318
319 v <<= 48;
320 v |= mac;
321
322 return v;
323 }
324
325 /*
326 * Calculate both the block 0 and the block 1 hash by applyingthe same hash
327 * algorithm as the one used currently by the ASIC to the seed, and return
328 * both hashes in the lower and higher word of the return value since only 12 bit of
329 * the hash are significant
330 */
331 static u32 rtl930x_l2_hash_key(struct rtl838x_switch_priv *priv, u64 seed)
332 {
333 u32 k0, k1, h1, h2, h;
334
335 k0 = (u32) (((seed >> 55) & 0x1f) ^ ((seed >> 44) & 0x7ff)
336 ^ ((seed >> 33) & 0x7ff) ^ ((seed >> 22) & 0x7ff)
337 ^ ((seed >> 11) & 0x7ff) ^ (seed & 0x7ff));
338
339 h1 = (seed >> 11) & 0x7ff;
340 h1 = ((h1 & 0x1f) << 6) | ((h1 >> 5) & 0x3f);
341
342 h2 = (seed >> 33) & 0x7ff;
343 h2 = ((h2 & 0x3f) << 5)| ((h2 >> 6) & 0x3f);
344
345 k1 = (u32) (((seed << 55) & 0x1f) ^ ((seed >> 44) & 0x7ff) ^ h2
346 ^ ((seed >> 22) & 0x7ff) ^ h1
347 ^ (seed & 0x7ff));
348
349 // Algorithm choice for block 0
350 if (sw_r32(RTL930X_L2_CTRL) & BIT(0))
351 h = k1;
352 else
353 h = k0;
354
355 /* Algorithm choice for block 1
356 * Since k0 and k1 are < 2048, adding 2048 will offset the hash into the second
357 * half of hash-space
358 * 2048 is in fact the hash-table size 16384 divided by 4 hashes per bucket
359 * divided by 2 to divide the hash space in 2
360 */
361 if (sw_r32(RTL930X_L2_CTRL) & BIT(1))
362 h |= (k1 + 2048) << 16;
363 else
364 h |= (k0 + 2048) << 16;
365
366 return h;
367 }
368
369 /*
370 * Fills an L2 entry structure from the SoC registers
371 */
372 static void rtl930x_fill_l2_entry(u32 r[], struct rtl838x_l2_entry *e)
373 {
374 pr_debug("In %s valid?\n", __func__);
375 e->valid = !!(r[2] & BIT(31));
376 if (!e->valid)
377 return;
378
379 pr_debug("In %s is valid\n", __func__);
380 e->is_ip_mc = false;
381 e->is_ipv6_mc = false;
382
383 // TODO: Is there not a function to copy directly MAC memory?
384 e->mac[0] = (r[0] >> 24);
385 e->mac[1] = (r[0] >> 16);
386 e->mac[2] = (r[0] >> 8);
387 e->mac[3] = r[0];
388 e->mac[4] = (r[1] >> 24);
389 e->mac[5] = (r[1] >> 16);
390
391 e->next_hop = !!(r[2] & BIT(12));
392 e->rvid = r[1] & 0xfff;
393
394 /* Is it a unicast entry? check multicast bit */
395 if (!(e->mac[0] & 1)) {
396 e->type = L2_UNICAST;
397 e->is_static = !!(r[2] & BIT(14));
398 e->port = (r[2] >> 20) & 0x3ff;
399 // Check for trunk port
400 if (r[2] & BIT(30)) {
401 e->is_trunk = true;
402 e->stack_dev = (e->port >> 9) & 1;
403 e->trunk = e->port & 0x3f;
404 } else {
405 e->is_trunk = false;
406 e->stack_dev = (e->port >> 6) & 0xf;
407 e->port = e->port & 0x3f;
408 }
409
410 e->block_da = !!(r[2] & BIT(15));
411 e->block_sa = !!(r[2] & BIT(16));
412 e->suspended = !!(r[2] & BIT(13));
413 e->age = (r[2] >> 17) & 3;
414 e->valid = true;
415 // the UC_VID field in hardware is used for the VID or for the route id
416 if (e->next_hop) {
417 e->nh_route_id = r[2] & 0x7ff;
418 e->vid = 0;
419 } else {
420 e->vid = r[2] & 0xfff;
421 e->nh_route_id = 0;
422 }
423 } else {
424 e->valid = true;
425 e->type = L2_MULTICAST;
426 e->mc_portmask_index = (r[2] >> 16) & 0x3ff;
427 }
428 }
429
430 /*
431 * Fills the 3 SoC table registers r[] with the information of in the rtl838x_l2_entry
432 */
433 static void rtl930x_fill_l2_row(u32 r[], struct rtl838x_l2_entry *e)
434 {
435 u32 port;
436
437 if (!e->valid) {
438 r[0] = r[1] = r[2] = 0;
439 return;
440 }
441
442 r[2] = BIT(31); // Set valid bit
443
444 r[0] = ((u32)e->mac[0]) << 24 | ((u32)e->mac[1]) << 16
445 | ((u32)e->mac[2]) << 8 | ((u32)e->mac[3]);
446 r[1] = ((u32)e->mac[4]) << 24 | ((u32)e->mac[5]) << 16;
447
448 r[2] |= e->next_hop ? BIT(12) : 0;
449
450 if (e->type == L2_UNICAST) {
451 r[2] |= e->is_static ? BIT(14) : 0;
452 r[1] |= e->rvid & 0xfff;
453 r[2] |= (e->port & 0x3ff) << 20;
454 if (e->is_trunk) {
455 r[2] |= BIT(30);
456 port = e->stack_dev << 9 | (e->port & 0x3f);
457 } else {
458 port = (e->stack_dev & 0xf) << 6;
459 port |= e->port & 0x3f;
460 }
461 r[2] |= port << 20;
462 r[2] |= e->block_da ? BIT(15) : 0;
463 r[2] |= e->block_sa ? BIT(17) : 0;
464 r[2] |= e->suspended ? BIT(13) : 0;
465 r[2] |= (e->age & 0x3) << 17;
466 // the UC_VID field in hardware is used for the VID or for the route id
467 if (e->next_hop)
468 r[2] |= e->nh_route_id & 0x7ff;
469 else
470 r[2] |= e->vid & 0xfff;
471 } else { // L2_MULTICAST
472 r[2] |= (e->mc_portmask_index & 0x3ff) << 16;
473 r[2] |= e->mc_mac_index & 0x7ff;
474 }
475 }
476
477 /*
478 * Read an L2 UC or MC entry out of a hash bucket of the L2 forwarding table
479 * hash is the id of the bucket and pos is the position of the entry in that bucket
480 * The data read from the SoC is filled into rtl838x_l2_entry
481 */
482 static u64 rtl930x_read_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e)
483 {
484 u32 r[3];
485 struct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 0);
486 u32 idx;
487 int i;
488 u64 mac;
489 u64 seed;
490
491 pr_debug("%s: hash %08x, pos: %d\n", __func__, hash, pos);
492
493 /* On the RTL93xx, 2 different hash algorithms are used making it a total of
494 * 8 buckets that need to be searched, 4 for each hash-half
495 * Use second hash space when bucket is between 4 and 8 */
496 if (pos >= 4) {
497 pos -= 4;
498 hash >>= 16;
499 } else {
500 hash &= 0xffff;
501 }
502
503 idx = (0 << 14) | (hash << 2) | pos; // Search SRAM, with hash and at pos in bucket
504 pr_debug("%s: NOW hash %08x, pos: %d\n", __func__, hash, pos);
505
506 rtl_table_read(q, idx);
507 for (i = 0; i < 3; i++)
508 r[i] = sw_r32(rtl_table_data(q, i));
509
510 rtl_table_release(q);
511
512 rtl930x_fill_l2_entry(r, e);
513
514 pr_debug("%s: valid: %d, nh: %d\n", __func__, e->valid, e->next_hop);
515 if (!e->valid)
516 return 0;
517
518 mac = ((u64)e->mac[0]) << 40 | ((u64)e->mac[1]) << 32 | ((u64)e->mac[2]) << 24
519 | ((u64)e->mac[3]) << 16 | ((u64)e->mac[4]) << 8 | ((u64)e->mac[5]);
520
521 seed = rtl930x_l2_hash_seed(mac, e->rvid);
522 pr_debug("%s: mac %016llx, seed %016llx\n", __func__, mac, seed);
523 // return vid with concatenated mac as unique id
524 return seed;
525 }
526
527 static void rtl930x_write_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e)
528 {
529 u32 r[3];
530 struct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 0);
531 u32 idx = (0 << 14) | (hash << 2) | pos; // Access SRAM, with hash and at pos in bucket
532 int i;
533
534 pr_debug("%s: hash %d, pos %d\n", __func__, hash, pos);
535 pr_debug("%s: index %d -> mac %02x:%02x:%02x:%02x:%02x:%02x\n", __func__, idx,
536 e->mac[0], e->mac[1], e->mac[2], e->mac[3],e->mac[4],e->mac[5]);
537
538 rtl930x_fill_l2_row(r, e);
539
540 for (i= 0; i < 3; i++)
541 sw_w32(r[i], rtl_table_data(q, i));
542
543 rtl_table_write(q, idx);
544 rtl_table_release(q);
545 }
546
547 static u64 rtl930x_read_cam(int idx, struct rtl838x_l2_entry *e)
548 {
549 u32 r[3];
550 struct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 1);
551 int i;
552
553 rtl_table_read(q, idx);
554 for (i= 0; i < 3; i++)
555 r[i] = sw_r32(rtl_table_data(q, i));
556
557 rtl_table_release(q);
558
559 rtl930x_fill_l2_entry(r, e);
560 if (!e->valid)
561 return 0;
562
563 // return mac with concatenated vid as unique id
564 return ((u64)r[0] << 28) | ((r[1] & 0xffff0000) >> 4) | e->vid;
565 }
566
567 static void rtl930x_write_cam(int idx, struct rtl838x_l2_entry *e)
568 {
569 u32 r[3];
570 struct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 1); // Access L2 Table 1
571 int i;
572
573 rtl930x_fill_l2_row(r, e);
574
575 for (i= 0; i < 3; i++)
576 sw_w32(r[i], rtl_table_data(q, i));
577
578 rtl_table_write(q, idx);
579 rtl_table_release(q);
580 }
581
582 static void dump_l2_entry(struct rtl838x_l2_entry *e)
583 {
584 pr_info("MAC: %02x:%02x:%02x:%02x:%02x:%02x vid: %d, rvid: %d, port: %d, valid: %d\n",
585 e->mac[0], e->mac[1], e->mac[2], e->mac[3], e->mac[4], e->mac[5],
586 e->vid, e->rvid, e->port, e->valid);
587 pr_info("Type: %d, is_static: %d, is_ip_mc: %d, is_ipv6_mc: %d, block_da: %d\n",
588 e->type, e->is_static, e->is_ip_mc, e->is_ipv6_mc, e->block_da);
589 pr_info(" block_sa: %d, suspended: %d, next_hop: %d, age: %d, is_trunk: %d, trunk: %d\n",
590 e->block_sa, e->suspended, e->next_hop, e->age, e->is_trunk, e->trunk);
591 if (e->is_ip_mc || e->is_ipv6_mc)
592 pr_info(" mc_portmask_index: %d, mc_gip: %d, mc_sip: %d\n",
593 e->mc_portmask_index, e->mc_gip, e->mc_sip);
594 pr_info(" stac_dev: %d, nh_route_id: %d, port: %d, dev_id\n",
595 e->stack_dev, e->nh_route_id, e->port);
596 }
597
598 static u64 rtl930x_read_mcast_pmask(int idx)
599 {
600 u32 portmask;
601 // Read MC_PORTMASK (2) via register RTL9300_TBL_L2
602 struct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 2);
603
604 rtl_table_read(q, idx);
605 portmask = sw_r32(rtl_table_data(q, 0));
606 portmask >>= 3;
607 rtl_table_release(q);
608
609 pr_debug("%s: Index idx %d has portmask %08x\n", __func__, idx, portmask);
610 return portmask;
611 }
612
613 static void rtl930x_write_mcast_pmask(int idx, u64 portmask)
614 {
615 u32 pm = portmask;
616
617 // Access MC_PORTMASK (2) via register RTL9300_TBL_L2
618 struct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 2);
619
620 pr_debug("%s: Index idx %d has portmask %08x\n", __func__, idx, pm);
621 pm <<= 3;
622 sw_w32(pm, rtl_table_data(q, 0));
623 rtl_table_write(q, idx);
624 rtl_table_release(q);
625 }
626
627 u64 rtl930x_traffic_get(int source)
628 {
629 u32 v;
630 struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 6);
631
632 rtl_table_read(r, source);
633 v = sw_r32(rtl_table_data(r, 0));
634 rtl_table_release(r);
635 return v >> 3;
636 }
637
638 /*
639 * Enable traffic between a source port and a destination port matrix
640 */
641 void rtl930x_traffic_set(int source, u64 dest_matrix)
642 {
643 struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 6);
644
645 sw_w32((dest_matrix << 3), rtl_table_data(r, 0));
646 rtl_table_write(r, source);
647 rtl_table_release(r);
648 }
649
650 void rtl930x_traffic_enable(int source, int dest)
651 {
652 struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 6);
653 rtl_table_read(r, source);
654 sw_w32_mask(0, BIT(dest + 3), rtl_table_data(r, 0));
655 rtl_table_write(r, source);
656 rtl_table_release(r);
657 }
658
659 void rtl930x_traffic_disable(int source, int dest)
660 {
661 struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 6);
662 rtl_table_read(r, source);
663 sw_w32_mask(BIT(dest + 3), 0, rtl_table_data(r, 0));
664 rtl_table_write(r, source);
665 rtl_table_release(r);
666 }
667
668 void rtl9300_dump_debug(void)
669 {
670 int i;
671 u16 r = RTL930X_STAT_PRVTE_DROP_COUNTER0;
672
673 for (i = 0; i < 10; i ++) {
674 pr_info("# %d %08x %08x %08x %08x %08x %08x %08x %08x\n", i * 8,
675 sw_r32(r), sw_r32(r + 4), sw_r32(r + 8), sw_r32(r + 12),
676 sw_r32(r + 16), sw_r32(r + 20), sw_r32(r + 24), sw_r32(r + 28));
677 r += 32;
678 }
679 pr_info("# %08x %08x %08x %08x %08x\n",
680 sw_r32(r), sw_r32(r + 4), sw_r32(r + 8), sw_r32(r + 12), sw_r32(r + 16));
681 rtl930x_print_matrix();
682 pr_info("RTL930X_L2_PORT_SABLK_CTRL: %08x, RTL930X_L2_PORT_DABLK_CTRL %08x\n",
683 sw_r32(RTL930X_L2_PORT_SABLK_CTRL), sw_r32(RTL930X_L2_PORT_DABLK_CTRL)
684
685 );
686 }
687
688 irqreturn_t rtl930x_switch_irq(int irq, void *dev_id)
689 {
690 struct dsa_switch *ds = dev_id;
691 u32 status = sw_r32(RTL930X_ISR_GLB);
692 u32 ports = sw_r32(RTL930X_ISR_PORT_LINK_STS_CHG);
693 u32 link;
694 int i;
695
696 /* Clear status */
697 sw_w32(ports, RTL930X_ISR_PORT_LINK_STS_CHG);
698
699 for (i = 0; i < 28; i++) {
700 if (ports & BIT(i)) {
701 /* Read the register twice because of issues with latency at least
702 * with the external RTL8226 PHY on the XGS1210 */
703 link = sw_r32(RTL930X_MAC_LINK_STS);
704 link = sw_r32(RTL930X_MAC_LINK_STS);
705 if (link & BIT(i))
706 dsa_port_phylink_mac_change(ds, i, true);
707 else
708 dsa_port_phylink_mac_change(ds, i, false);
709 }
710 }
711
712 return IRQ_HANDLED;
713 }
714
715 int rtl930x_write_phy(u32 port, u32 page, u32 reg, u32 val)
716 {
717 u32 v;
718 int err = 0;
719
720 pr_debug("%s: port %d, page: %d, reg: %x, val: %x\n", __func__, port, page, reg, val);
721
722 if (port > 63 || page > 4095 || reg > 31)
723 return -ENOTSUPP;
724
725 val &= 0xffff;
726 mutex_lock(&smi_lock);
727
728 sw_w32(BIT(port), RTL930X_SMI_ACCESS_PHY_CTRL_0);
729 sw_w32_mask(0xffff << 16, val << 16, RTL930X_SMI_ACCESS_PHY_CTRL_2);
730 v = reg << 20 | page << 3 | 0x1f << 15 | BIT(2) | BIT(0);
731 sw_w32(v, RTL930X_SMI_ACCESS_PHY_CTRL_1);
732
733 do {
734 v = sw_r32(RTL930X_SMI_ACCESS_PHY_CTRL_1);
735 } while (v & 0x1);
736
737 if (v & 0x2)
738 err = -EIO;
739
740 mutex_unlock(&smi_lock);
741
742 return err;
743 }
744
745 int rtl930x_read_phy(u32 port, u32 page, u32 reg, u32 *val)
746 {
747 u32 v;
748 int err = 0;
749
750 if (port > 63 || page > 4095 || reg > 31)
751 return -ENOTSUPP;
752
753 mutex_lock(&smi_lock);
754
755 sw_w32_mask(0xffff << 16, port << 16, RTL930X_SMI_ACCESS_PHY_CTRL_2);
756 v = reg << 20 | page << 3 | 0x1f << 15 | 1;
757 sw_w32(v, RTL930X_SMI_ACCESS_PHY_CTRL_1);
758
759 do {
760 v = sw_r32(RTL930X_SMI_ACCESS_PHY_CTRL_1);
761 } while ( v & 0x1);
762
763 if (v & BIT(25)) {
764 pr_debug("Error reading phy %d, register %d\n", port, reg);
765 err = -EIO;
766 }
767 *val = (sw_r32(RTL930X_SMI_ACCESS_PHY_CTRL_2) & 0xffff);
768
769 pr_debug("%s: port %d, page: %d, reg: %x, val: %x\n", __func__, port, page, reg, *val);
770
771 mutex_unlock(&smi_lock);
772
773 return err;
774 }
775
776 /*
777 * Write to an mmd register of the PHY
778 */
779 int rtl930x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val)
780 {
781 int err = 0;
782 u32 v;
783
784 mutex_lock(&smi_lock);
785
786 // Set PHY to access
787 sw_w32(BIT(port), RTL930X_SMI_ACCESS_PHY_CTRL_0);
788
789 // Set data to write
790 sw_w32_mask(0xffff << 16, val << 16, RTL930X_SMI_ACCESS_PHY_CTRL_2);
791
792 // Set MMD device number and register to write to
793 sw_w32(devnum << 16 | (regnum & 0xffff), RTL930X_SMI_ACCESS_PHY_CTRL_3);
794
795 v = BIT(2) | BIT(1) | BIT(0); // WRITE | MMD-access | EXEC
796 sw_w32(v, RTL930X_SMI_ACCESS_PHY_CTRL_1);
797
798 do {
799 v = sw_r32(RTL930X_SMI_ACCESS_PHY_CTRL_1);
800 } while (v & BIT(0));
801
802 pr_debug("%s: port %d, regnum: %x, val: %x (err %d)\n", __func__, port, regnum, val, err);
803 mutex_unlock(&smi_lock);
804 return err;
805 }
806
807 /*
808 * Read an mmd register of the PHY
809 */
810 int rtl930x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val)
811 {
812 int err = 0;
813 u32 v;
814
815 mutex_lock(&smi_lock);
816
817 // Set PHY to access
818 sw_w32_mask(0xffff << 16, port << 16, RTL930X_SMI_ACCESS_PHY_CTRL_2);
819
820 // Set MMD device number and register to write to
821 sw_w32(devnum << 16 | (regnum & 0xffff), RTL930X_SMI_ACCESS_PHY_CTRL_3);
822
823 v = BIT(1) | BIT(0); // MMD-access | EXEC
824 sw_w32(v, RTL930X_SMI_ACCESS_PHY_CTRL_1);
825
826 do {
827 v = sw_r32(RTL930X_SMI_ACCESS_PHY_CTRL_1);
828 } while (v & BIT(0));
829 // There is no error-checking via BIT 25 of v, as it does not seem to be set correctly
830 *val = (sw_r32(RTL930X_SMI_ACCESS_PHY_CTRL_2) & 0xffff);
831 pr_debug("%s: port %d, regnum: %x, val: %x (err %d)\n", __func__, port, regnum, *val, err);
832
833 mutex_unlock(&smi_lock);
834
835 return err;
836 }
837
838 /*
839 * Calculate both the block 0 and the block 1 hash, and return in
840 * lower and higher word of the return value since only 12 bit of
841 * the hash are significant
842 */
843 u32 rtl930x_hash(struct rtl838x_switch_priv *priv, u64 seed)
844 {
845 u32 k0, k1, h1, h2, h;
846
847 k0 = (u32) (((seed >> 55) & 0x1f) ^ ((seed >> 44) & 0x7ff)
848 ^ ((seed >> 33) & 0x7ff) ^ ((seed >> 22) & 0x7ff)
849 ^ ((seed >> 11) & 0x7ff) ^ (seed & 0x7ff));
850
851 h1 = (seed >> 11) & 0x7ff;
852 h1 = ((h1 & 0x1f) << 6) | ((h1 >> 5) & 0x3f);
853
854 h2 = (seed >> 33) & 0x7ff;
855 h2 = ((h2 & 0x3f) << 5)| ((h2 >> 6) & 0x3f);
856
857 k1 = (u32) (((seed << 55) & 0x1f) ^ ((seed >> 44) & 0x7ff) ^ h2
858 ^ ((seed >> 22) & 0x7ff) ^ h1
859 ^ (seed & 0x7ff));
860
861 // Algorithm choice for block 0
862 if (sw_r32(RTL930X_L2_CTRL) & BIT(0))
863 h = k1;
864 else
865 h = k0;
866
867 /* Algorithm choice for block 1
868 * Since k0 and k1 are < 2048, adding 2048 will offset the hash into the second
869 * half of hash-space
870 * 2048 is in fact the hash-table size 16384 divided by 4 hashes per bucket
871 * divided by 2 to divide the hash space in 2
872 */
873 if (sw_r32(RTL930X_L2_CTRL) & BIT(1))
874 h |= (k1 + 2048) << 16;
875 else
876 h |= (k0 + 2048) << 16;
877
878 return h;
879 }
880
881 /*
882 * Enables or disables the EEE/EEEP capability of a port
883 */
884 void rtl930x_port_eee_set(struct rtl838x_switch_priv *priv, int port, bool enable)
885 {
886 u32 v;
887
888 // This works only for Ethernet ports, and on the RTL930X, ports from 26 are SFP
889 if (port >= 26)
890 return;
891
892 pr_debug("In %s: setting port %d to %d\n", __func__, port, enable);
893 v = enable ? 0x3f : 0x0;
894
895 // Set EEE/EEEP state for 100, 500, 1000MBit and 2.5, 5 and 10GBit
896 sw_w32_mask(0, v << 10, rtl930x_mac_force_mode_ctrl(port));
897
898 // Set TX/RX EEE state
899 v = enable ? 0x3 : 0x0;
900 sw_w32(v, RTL930X_EEE_CTRL(port));
901
902 priv->ports[port].eee_enabled = enable;
903 }
904
905 /*
906 * Get EEE own capabilities and negotiation result
907 */
908 int rtl930x_eee_port_ability(struct rtl838x_switch_priv *priv, struct ethtool_eee *e, int port)
909 {
910 u32 link, a;
911
912 if (port >= 26)
913 return -ENOTSUPP;
914
915 pr_info("In %s, port %d\n", __func__, port);
916 link = sw_r32(RTL930X_MAC_LINK_STS);
917 link = sw_r32(RTL930X_MAC_LINK_STS);
918 if (!(link & BIT(port)))
919 return 0;
920
921 pr_info("Setting advertised\n");
922 if (sw_r32(rtl930x_mac_force_mode_ctrl(port)) & BIT(10))
923 e->advertised |= ADVERTISED_100baseT_Full;
924
925 if (sw_r32(rtl930x_mac_force_mode_ctrl(port)) & BIT(12))
926 e->advertised |= ADVERTISED_1000baseT_Full;
927
928 if (priv->ports[port].is2G5 && sw_r32(rtl930x_mac_force_mode_ctrl(port)) & BIT(13)) {
929 pr_info("ADVERTISING 2.5G EEE\n");
930 e->advertised |= ADVERTISED_2500baseX_Full;
931 }
932
933 if (priv->ports[port].is10G && sw_r32(rtl930x_mac_force_mode_ctrl(port)) & BIT(15))
934 e->advertised |= ADVERTISED_10000baseT_Full;
935
936 a = sw_r32(RTL930X_MAC_EEE_ABLTY);
937 a = sw_r32(RTL930X_MAC_EEE_ABLTY);
938 pr_info("Link partner: %08x\n", a);
939 if (a & BIT(port)) {
940 e->lp_advertised = ADVERTISED_100baseT_Full;
941 e->lp_advertised |= ADVERTISED_1000baseT_Full;
942 if (priv->ports[port].is2G5)
943 e->lp_advertised |= ADVERTISED_2500baseX_Full;
944 if (priv->ports[port].is10G)
945 e->lp_advertised |= ADVERTISED_10000baseT_Full;
946 }
947
948 // Read 2x to clear latched state
949 a = sw_r32(RTL930X_EEEP_PORT_CTRL(port));
950 a = sw_r32(RTL930X_EEEP_PORT_CTRL(port));
951 pr_info("%s RTL930X_EEEP_PORT_CTRL: %08x\n", __func__, a);
952
953 return 0;
954 }
955
956 static void rtl930x_init_eee(struct rtl838x_switch_priv *priv, bool enable)
957 {
958 int i;
959
960 pr_info("Setting up EEE, state: %d\n", enable);
961
962 // Setup EEE on all ports
963 for (i = 0; i < priv->cpu_port; i++) {
964 if (priv->ports[i].phy)
965 rtl930x_port_eee_set(priv, i, enable);
966 }
967
968 priv->eee_enabled = enable;
969 }
970 #define HASH_PICK(val, lsb, len) ((val & (((1 << len) - 1) << lsb)) >> lsb)
971
972 static u32 rtl930x_l3_hash4(u32 ip, int algorithm, bool move_dip)
973 {
974 u32 rows[4];
975 u32 hash;
976 u32 s0, s1, pH;
977
978 memset(rows, 0, sizeof(rows));
979
980 rows[0] = HASH_PICK(ip, 27, 5);
981 rows[1] = HASH_PICK(ip, 18, 9);
982 rows[2] = HASH_PICK(ip, 9, 9);
983
984 if (!move_dip)
985 rows[3] = HASH_PICK(ip, 0, 9);
986
987 if (!algorithm) {
988 hash = rows[0] ^ rows[1] ^ rows[2] ^ rows[3];
989 } else {
990 s0 = rows[0] + rows[1] + rows[2];
991 s1 = (s0 & 0x1ff) + ((s0 & (0x1ff << 9)) >> 9);
992 pH = (s1 & 0x1ff) + ((s1 & (0x1ff << 9)) >> 9);
993 hash = pH ^ rows[3];
994 }
995 return hash;
996 }
997
998 static u32 rtl930x_l3_hash6(struct in6_addr *ip6, int algorithm, bool move_dip)
999 {
1000 u32 rows[16];
1001 u32 hash;
1002 u32 s0, s1, pH;
1003
1004 rows[0] = (HASH_PICK(ip6->s6_addr[0], 6, 2) << 0);
1005 rows[1] = (HASH_PICK(ip6->s6_addr[0], 0, 6) << 3) | HASH_PICK(ip6->s6_addr[1], 5, 3);
1006 rows[2] = (HASH_PICK(ip6->s6_addr[1], 0, 5) << 4) | HASH_PICK(ip6->s6_addr[2], 4, 4);
1007 rows[3] = (HASH_PICK(ip6->s6_addr[2], 0, 4) << 5) | HASH_PICK(ip6->s6_addr[3], 3, 5);
1008 rows[4] = (HASH_PICK(ip6->s6_addr[3], 0, 3) << 6) | HASH_PICK(ip6->s6_addr[4], 2, 6);
1009 rows[5] = (HASH_PICK(ip6->s6_addr[4], 0, 2) << 7) | HASH_PICK(ip6->s6_addr[5], 1, 7);
1010 rows[6] = (HASH_PICK(ip6->s6_addr[5], 0, 1) << 8) | HASH_PICK(ip6->s6_addr[6], 0, 8);
1011 rows[7] = (HASH_PICK(ip6->s6_addr[7], 0, 8) << 1) | HASH_PICK(ip6->s6_addr[8], 7, 1);
1012 rows[8] = (HASH_PICK(ip6->s6_addr[8], 0, 7) << 2) | HASH_PICK(ip6->s6_addr[9], 6, 2);
1013 rows[9] = (HASH_PICK(ip6->s6_addr[9], 0, 6) << 3) | HASH_PICK(ip6->s6_addr[10], 5, 3);
1014 rows[10] = (HASH_PICK(ip6->s6_addr[10], 0, 5) << 4) | HASH_PICK(ip6->s6_addr[11], 4, 4);
1015 if (!algorithm) {
1016 rows[11] = (HASH_PICK(ip6->s6_addr[11], 0, 4) << 5)
1017 | (HASH_PICK(ip6->s6_addr[12], 3, 5) << 0);
1018 rows[12] = (HASH_PICK(ip6->s6_addr[12], 0, 3) << 6)
1019 | (HASH_PICK(ip6->s6_addr[13], 2, 6) << 0);
1020 rows[13] = (HASH_PICK(ip6->s6_addr[13], 0, 2) << 7)
1021 | (HASH_PICK(ip6->s6_addr[14], 1, 7) << 0);
1022 if (!move_dip) {
1023 rows[14] = (HASH_PICK(ip6->s6_addr[14], 0, 1) << 8)
1024 | (HASH_PICK(ip6->s6_addr[15], 0, 8) << 0);
1025 }
1026 hash = rows[0] ^ rows[1] ^ rows[2] ^ rows[3] ^ rows[4] ^ rows[5] ^ rows[6]
1027 ^ rows[7] ^ rows[8] ^ rows[9] ^ rows[10] ^ rows[11] ^ rows[12]
1028 ^ rows[13] ^ rows[14];
1029 } else {
1030 rows[11] = (HASH_PICK(ip6->s6_addr[11], 0, 4) << 5);
1031 rows[12] = (HASH_PICK(ip6->s6_addr[12], 3, 5) << 0);
1032 rows[13] = (HASH_PICK(ip6->s6_addr[12], 0, 3) << 6)
1033 | HASH_PICK(ip6->s6_addr[13], 2, 6);
1034 rows[14] = (HASH_PICK(ip6->s6_addr[13], 0, 2) << 7)
1035 | HASH_PICK(ip6->s6_addr[14], 1, 7);
1036 if (!move_dip) {
1037 rows[15] = (HASH_PICK(ip6->s6_addr[14], 0, 1) << 8)
1038 | (HASH_PICK(ip6->s6_addr[15], 0, 8) << 0);
1039 }
1040 s0 = rows[12] + rows[13] + rows[14];
1041 s1 = (s0 & 0x1ff) + ((s0 & (0x1ff << 9)) >> 9);
1042 pH = (s1 & 0x1ff) + ((s1 & (0x1ff << 9)) >> 9);
1043 hash = rows[0] ^ rows[1] ^ rows[2] ^ rows[3] ^ rows[4] ^ rows[5] ^ rows[6]
1044 ^ rows[7] ^ rows[8] ^ rows[9] ^ rows[10] ^ rows[11] ^ pH ^ rows[15];
1045 }
1046 return hash;
1047 }
1048
1049 /*
1050 * Read a prefix route entry from the L3_PREFIX_ROUTE_IPUC table
1051 * We currently only support IPv4 and IPv6 unicast route
1052 */
1053 static void rtl930x_route_read(int idx, struct rtl83xx_route *rt)
1054 {
1055 u32 v, ip4_m;
1056 bool host_route, default_route;
1057 struct in6_addr ip6_m;
1058
1059 // Read L3_PREFIX_ROUTE_IPUC table (2) via register RTL9300_TBL_1
1060 struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 2);
1061
1062 rtl_table_read(r, idx);
1063 // The table has a size of 11 registers
1064 rt->attr.valid = !!(sw_r32(rtl_table_data(r, 0)) & BIT(31));
1065 if (!rt->attr.valid)
1066 goto out;
1067
1068 rt->attr.type = (sw_r32(rtl_table_data(r, 0)) >> 29) & 0x3;
1069
1070 v = sw_r32(rtl_table_data(r, 10));
1071 host_route = !!(v & BIT(21));
1072 default_route = !!(v & BIT(20));
1073 rt->prefix_len = -1;
1074 pr_info("%s: host route %d, default_route %d\n", __func__, host_route, default_route);
1075
1076 switch (rt->attr.type) {
1077 case 0: // IPv4 Unicast route
1078 rt->dst_ip = sw_r32(rtl_table_data(r, 4));
1079 ip4_m = sw_r32(rtl_table_data(r, 9));
1080 pr_info("%s: Read ip4 mask: %08x\n", __func__, ip4_m);
1081 rt->prefix_len = host_route ? 32 : -1;
1082 rt->prefix_len = (rt->prefix_len < 0 && default_route) ? 0 : -1;
1083 if (rt->prefix_len < 0)
1084 rt->prefix_len = inet_mask_len(ip4_m);
1085 break;
1086 case 2: // IPv6 Unicast route
1087 ipv6_addr_set(&rt->dst_ip6,
1088 sw_r32(rtl_table_data(r, 1)), sw_r32(rtl_table_data(r, 2)),
1089 sw_r32(rtl_table_data(r, 3)), sw_r32(rtl_table_data(r, 4)));
1090 ipv6_addr_set(&ip6_m,
1091 sw_r32(rtl_table_data(r, 6)), sw_r32(rtl_table_data(r, 7)),
1092 sw_r32(rtl_table_data(r, 8)), sw_r32(rtl_table_data(r, 9)));
1093 rt->prefix_len = host_route ? 128 : 0;
1094 rt->prefix_len = (rt->prefix_len < 0 && default_route) ? 0 : -1;
1095 if (rt->prefix_len < 0)
1096 rt->prefix_len = find_last_bit((unsigned long int *)&ip6_m.s6_addr32,
1097 128);
1098 break;
1099 case 1: // IPv4 Multicast route
1100 case 3: // IPv6 Multicast route
1101 pr_warn("%s: route type not supported\n", __func__);
1102 goto out;
1103 }
1104
1105 rt->attr.hit = !!(v & BIT(22));
1106 rt->attr.action = (v >> 18) & 3;
1107 rt->nh.id = (v >> 7) & 0x7ff;
1108 rt->attr.ttl_dec = !!(v & BIT(6));
1109 rt->attr.ttl_check = !!(v & BIT(5));
1110 rt->attr.dst_null = !!(v & BIT(4));
1111 rt->attr.qos_as = !!(v & BIT(3));
1112 rt->attr.qos_prio = v & 0x7;
1113 pr_info("%s: index %d is valid: %d\n", __func__, idx, rt->attr.valid);
1114 pr_info("%s: next_hop: %d, hit: %d, action :%d, ttl_dec %d, ttl_check %d, dst_null %d\n",
1115 __func__, rt->nh.id, rt->attr.hit, rt->attr.action,
1116 rt->attr.ttl_dec, rt->attr.ttl_check, rt->attr.dst_null);
1117 pr_info("%s: GW: %pI4, prefix_len: %d\n", __func__, &rt->dst_ip, rt->prefix_len);
1118 out:
1119 rtl_table_release(r);
1120 }
1121
1122 static void rtl930x_net6_mask(int prefix_len, struct in6_addr *ip6_m)
1123 {
1124 int o, b;
1125 // Define network mask
1126 o = prefix_len >> 3;
1127 b = prefix_len & 0x7;
1128 memset(ip6_m->s6_addr, 0xff, o);
1129 ip6_m->s6_addr[o] |= b ? 0xff00 >> b : 0x00;
1130 }
1131
1132 /*
1133 * Read a host route entry from the table using its index
1134 * We currently only support IPv4 and IPv6 unicast route
1135 */
1136 static void rtl930x_host_route_read(int idx, struct rtl83xx_route *rt)
1137 {
1138 u32 v;
1139 // Read L3_HOST_ROUTE_IPUC table (1) via register RTL9300_TBL_1
1140 struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 1);
1141
1142 idx = ((idx / 6) * 8) + (idx % 6);
1143
1144 pr_debug("In %s, physical index %d\n", __func__, idx);
1145 rtl_table_read(r, idx);
1146 // The table has a size of 5 (for UC, 11 for MC) registers
1147 v = sw_r32(rtl_table_data(r, 0));
1148 rt->attr.valid = !!(v & BIT(31));
1149 if (!rt->attr.valid)
1150 goto out;
1151 rt->attr.type = (v >> 29) & 0x3;
1152 switch (rt->attr.type) {
1153 case 0: // IPv4 Unicast route
1154 rt->dst_ip = sw_r32(rtl_table_data(r, 4));
1155 break;
1156 case 2: // IPv6 Unicast route
1157 ipv6_addr_set(&rt->dst_ip6,
1158 sw_r32(rtl_table_data(r, 3)), sw_r32(rtl_table_data(r, 2)),
1159 sw_r32(rtl_table_data(r, 1)), sw_r32(rtl_table_data(r, 0)));
1160 break;
1161 case 1: // IPv4 Multicast route
1162 case 3: // IPv6 Multicast route
1163 pr_warn("%s: route type not supported\n", __func__);
1164 goto out;
1165 }
1166
1167 rt->attr.hit = !!(v & BIT(20));
1168 rt->attr.dst_null = !!(v & BIT(19));
1169 rt->attr.action = (v >> 17) & 3;
1170 rt->nh.id = (v >> 6) & 0x7ff;
1171 rt->attr.ttl_dec = !!(v & BIT(5));
1172 rt->attr.ttl_check = !!(v & BIT(4));
1173 rt->attr.qos_as = !!(v & BIT(3));
1174 rt->attr.qos_prio = v & 0x7;
1175 pr_debug("%s: index %d is valid: %d\n", __func__, idx, rt->attr.valid);
1176 pr_debug("%s: next_hop: %d, hit: %d, action :%d, ttl_dec %d, ttl_check %d, dst_null %d\n",
1177 __func__, rt->nh.id, rt->attr.hit, rt->attr.action, rt->attr.ttl_dec, rt->attr.ttl_check,
1178 rt->attr.dst_null);
1179 pr_debug("%s: Destination: %pI4\n", __func__, &rt->dst_ip);
1180
1181 out:
1182 rtl_table_release(r);
1183 }
1184
1185 /*
1186 * Write a host route entry from the table using its index
1187 * We currently only support IPv4 and IPv6 unicast route
1188 */
1189 static void rtl930x_host_route_write(int idx, struct rtl83xx_route *rt)
1190 {
1191 u32 v;
1192 // Access L3_HOST_ROUTE_IPUC table (1) via register RTL9300_TBL_1
1193 struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 1);
1194 // The table has a size of 5 (for UC, 11 for MC) registers
1195
1196 idx = ((idx / 6) * 8) + (idx % 6);
1197
1198 pr_debug("%s: index %d is valid: %d\n", __func__, idx, rt->attr.valid);
1199 pr_debug("%s: next_hop: %d, hit: %d, action :%d, ttl_dec %d, ttl_check %d, dst_null %d\n",
1200 __func__, rt->nh.id, rt->attr.hit, rt->attr.action, rt->attr.ttl_dec, rt->attr.ttl_check,
1201 rt->attr.dst_null);
1202 pr_debug("%s: GW: %pI4, prefix_len: %d\n", __func__, &rt->dst_ip, rt->prefix_len);
1203
1204 v = BIT(31); // Entry is valid
1205 v |= (rt->attr.type & 0x3) << 29;
1206 v |= rt->attr.hit ? BIT(20) : 0;
1207 v |= rt->attr.dst_null ? BIT(19) : 0;
1208 v |= (rt->attr.action & 0x3) << 17;
1209 v |= (rt->nh.id & 0x7ff) << 6;
1210 v |= rt->attr.ttl_dec ? BIT(5) : 0;
1211 v |= rt->attr.ttl_check ? BIT(4) : 0;
1212 v |= rt->attr.qos_as ? BIT(3) : 0;
1213 v |= rt->attr.qos_prio & 0x7;
1214
1215 sw_w32(v, rtl_table_data(r, 0));
1216 switch (rt->attr.type) {
1217 case 0: // IPv4 Unicast route
1218 sw_w32(0, rtl_table_data(r, 1));
1219 sw_w32(0, rtl_table_data(r, 2));
1220 sw_w32(0, rtl_table_data(r, 3));
1221 sw_w32(rt->dst_ip, rtl_table_data(r, 4));
1222 break;
1223 case 2: // IPv6 Unicast route
1224 sw_w32(rt->dst_ip6.s6_addr32[0], rtl_table_data(r, 1));
1225 sw_w32(rt->dst_ip6.s6_addr32[1], rtl_table_data(r, 2));
1226 sw_w32(rt->dst_ip6.s6_addr32[2], rtl_table_data(r, 3));
1227 sw_w32(rt->dst_ip6.s6_addr32[3], rtl_table_data(r, 4));
1228 break;
1229 case 1: // IPv4 Multicast route
1230 case 3: // IPv6 Multicast route
1231 pr_warn("%s: route type not supported\n", __func__);
1232 goto out;
1233 }
1234
1235 rtl_table_write(r, idx);
1236
1237 out:
1238 rtl_table_release(r);
1239 }
1240
1241 /*
1242 * Look up the index of a prefix route in the routing table CAM for unicast IPv4/6 routes
1243 * using hardware offload.
1244 */
1245 static int rtl930x_route_lookup_hw(struct rtl83xx_route *rt)
1246 {
1247 u32 ip4_m, v;
1248 struct in6_addr ip6_m;
1249 int i;
1250
1251 if (rt->attr.type == 1 || rt->attr.type == 3) // Hardware only supports UC routes
1252 return -1;
1253
1254 sw_w32_mask(0x3 << 19, rt->attr.type, RTL930X_L3_HW_LU_KEY_CTRL);
1255 if (rt->attr.type) { // IPv6
1256 rtl930x_net6_mask(rt->prefix_len, &ip6_m);
1257 for (i = 0; i < 4; i++)
1258 sw_w32(rt->dst_ip6.s6_addr32[0] & ip6_m.s6_addr32[0],
1259 RTL930X_L3_HW_LU_KEY_IP_CTRL + (i << 2));
1260 } else { // IPv4
1261 ip4_m = inet_make_mask(rt->prefix_len);
1262 sw_w32(0, RTL930X_L3_HW_LU_KEY_IP_CTRL);
1263 sw_w32(0, RTL930X_L3_HW_LU_KEY_IP_CTRL + 4);
1264 sw_w32(0, RTL930X_L3_HW_LU_KEY_IP_CTRL + 8);
1265 v = rt->dst_ip & ip4_m;
1266 pr_info("%s: searching for %pI4\n", __func__, &v);
1267 sw_w32(v, RTL930X_L3_HW_LU_KEY_IP_CTRL + 12);
1268 }
1269
1270 // Execute CAM lookup in SoC
1271 sw_w32(BIT(15), RTL930X_L3_HW_LU_CTRL);
1272
1273 // Wait until execute bit clears and result is ready
1274 do {
1275 v = sw_r32(RTL930X_L3_HW_LU_CTRL);
1276 } while (v & BIT(15));
1277
1278 pr_info("%s: found: %d, index: %d\n", __func__, !!(v & BIT(14)), v & 0x1ff);
1279
1280 // Test if search successful (BIT 14 set)
1281 if (v & BIT(14))
1282 return v & 0x1ff;
1283
1284 return -1;
1285 }
1286
1287 static int rtl930x_find_l3_slot(struct rtl83xx_route *rt, bool must_exist)
1288 {
1289 int t, s, slot_width, algorithm, addr, idx;
1290 u32 hash;
1291 struct rtl83xx_route route_entry;
1292
1293 // IPv6 entries take up 3 slots
1294 slot_width = (rt->attr.type == 0) || (rt->attr.type == 2) ? 1 : 3;
1295
1296 for (t = 0; t < 2; t++) {
1297 algorithm = (sw_r32(RTL930X_L3_HOST_TBL_CTRL) >> (2 + t)) & 0x1;
1298 hash = rtl930x_l3_hash4(rt->dst_ip, algorithm, false);
1299
1300 pr_debug("%s: table %d, algorithm %d, hash %04x\n", __func__, t, algorithm, hash);
1301
1302 for (s = 0; s < 6; s += slot_width) {
1303 addr = (t << 12) | ((hash & 0x1ff) << 3) | s;
1304 pr_debug("%s physical address %d\n", __func__, addr);
1305 idx = ((addr / 8) * 6) + (addr % 8);
1306 pr_debug("%s logical address %d\n", __func__, idx);
1307
1308 rtl930x_host_route_read(idx, &route_entry);
1309 pr_debug("%s route valid %d, route dest: %pI4, hit %d\n", __func__,
1310 rt->attr.valid, &rt->dst_ip, rt->attr.hit);
1311 if (!must_exist && rt->attr.valid)
1312 return idx;
1313 if (must_exist && route_entry.dst_ip == rt->dst_ip)
1314 return idx;
1315 }
1316 }
1317
1318 return -1;
1319 }
1320
1321 /*
1322 * Write a prefix route into the routing table CAM at position idx
1323 * Currently only IPv4 and IPv6 unicast routes are supported
1324 */
1325 static void rtl930x_route_write(int idx, struct rtl83xx_route *rt)
1326 {
1327 u32 v, ip4_m;
1328 struct in6_addr ip6_m;
1329 // Access L3_PREFIX_ROUTE_IPUC table (2) via register RTL9300_TBL_1
1330 // The table has a size of 11 registers (20 for MC)
1331 struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 2);
1332
1333 pr_debug("%s: index %d is valid: %d\n", __func__, idx, rt->attr.valid);
1334 pr_debug("%s: nexthop: %d, hit: %d, action :%d, ttl_dec %d, ttl_check %d, dst_null %d\n",
1335 __func__, rt->nh.id, rt->attr.hit, rt->attr.action,
1336 rt->attr.ttl_dec, rt->attr.ttl_check, rt->attr.dst_null);
1337 pr_debug("%s: GW: %pI4, prefix_len: %d\n", __func__, &rt->dst_ip, rt->prefix_len);
1338
1339 v = rt->attr.valid ? BIT(31) : 0;
1340 v |= (rt->attr.type & 0x3) << 29;
1341 sw_w32(v, rtl_table_data(r, 0));
1342
1343 v = rt->attr.hit ? BIT(22) : 0;
1344 v |= (rt->attr.action & 0x3) << 18;
1345 v |= (rt->nh.id & 0x7ff) << 7;
1346 v |= rt->attr.ttl_dec ? BIT(6) : 0;
1347 v |= rt->attr.ttl_check ? BIT(5) : 0;
1348 v |= rt->attr.dst_null ? BIT(6) : 0;
1349 v |= rt->attr.qos_as ? BIT(6) : 0;
1350 v |= rt->attr.qos_prio & 0x7;
1351 v |= rt->prefix_len == 0 ? BIT(20) : 0; // set default route bit
1352
1353 // set bit mask for entry type always to 0x3
1354 sw_w32(0x3 << 29, rtl_table_data(r, 5));
1355
1356 switch (rt->attr.type) {
1357 case 0: // IPv4 Unicast route
1358 sw_w32(0, rtl_table_data(r, 1));
1359 sw_w32(0, rtl_table_data(r, 2));
1360 sw_w32(0, rtl_table_data(r, 3));
1361 sw_w32(rt->dst_ip, rtl_table_data(r, 4));
1362
1363 v |= rt->prefix_len == 32 ? BIT(21) : 0; // set host-route bit
1364 ip4_m = inet_make_mask(rt->prefix_len);
1365 sw_w32(0, rtl_table_data(r, 6));
1366 sw_w32(0, rtl_table_data(r, 7));
1367 sw_w32(0, rtl_table_data(r, 8));
1368 sw_w32(ip4_m, rtl_table_data(r, 9));
1369 break;
1370 case 2: // IPv6 Unicast route
1371 sw_w32(rt->dst_ip6.s6_addr32[0], rtl_table_data(r, 1));
1372 sw_w32(rt->dst_ip6.s6_addr32[1], rtl_table_data(r, 2));
1373 sw_w32(rt->dst_ip6.s6_addr32[2], rtl_table_data(r, 3));
1374 sw_w32(rt->dst_ip6.s6_addr32[3], rtl_table_data(r, 4));
1375
1376 v |= rt->prefix_len == 128 ? BIT(21) : 0; // set host-route bit
1377
1378 rtl930x_net6_mask(rt->prefix_len, &ip6_m);
1379
1380 sw_w32(ip6_m.s6_addr32[0], rtl_table_data(r, 6));
1381 sw_w32(ip6_m.s6_addr32[1], rtl_table_data(r, 7));
1382 sw_w32(ip6_m.s6_addr32[2], rtl_table_data(r, 8));
1383 sw_w32(ip6_m.s6_addr32[3], rtl_table_data(r, 9));
1384 break;
1385 case 1: // IPv4 Multicast route
1386 case 3: // IPv6 Multicast route
1387 pr_warn("%s: route type not supported\n", __func__);
1388 rtl_table_release(r);
1389 return;
1390 }
1391 sw_w32(v, rtl_table_data(r, 10));
1392
1393 pr_debug("%s: %08x %08x %08x %08x %08x %08x %08x %08x %08x %08x %08x\n", __func__,
1394 sw_r32(rtl_table_data(r, 0)), sw_r32(rtl_table_data(r, 1)), sw_r32(rtl_table_data(r, 2)),
1395 sw_r32(rtl_table_data(r, 3)), sw_r32(rtl_table_data(r, 4)), sw_r32(rtl_table_data(r, 5)),
1396 sw_r32(rtl_table_data(r, 6)), sw_r32(rtl_table_data(r, 7)), sw_r32(rtl_table_data(r, 8)),
1397 sw_r32(rtl_table_data(r, 9)), sw_r32(rtl_table_data(r, 10)));
1398
1399 rtl_table_write(r, idx);
1400 rtl_table_release(r);
1401 }
1402
1403
1404 /*
1405 * Get the destination MAC and L3 egress interface ID of a nexthop entry from
1406 * the SoC's L3_NEXTHOP table
1407 */
1408 static void rtl930x_get_l3_nexthop(int idx, u16 *dmac_id, u16 *interface)
1409 {
1410 u32 v;
1411 // Read L3_NEXTHOP table (3) via register RTL9300_TBL_1
1412 struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 3);
1413
1414 rtl_table_read(r, idx);
1415 // The table has a size of 1 register
1416 v = sw_r32(rtl_table_data(r, 0));
1417 rtl_table_release(r);
1418
1419 *dmac_id = (v >> 7) & 0x7fff;
1420 *interface = v & 0x7f;
1421 }
1422
1423 static int rtl930x_l3_mtu_del(struct rtl838x_switch_priv *priv, int mtu)
1424 {
1425 int i;
1426
1427 for (i = 0; i < MAX_INTF_MTUS; i++) {
1428 if (mtu == priv->intf_mtus[i])
1429 break;
1430 }
1431 if (i >= MAX_INTF_MTUS || !priv->intf_mtu_count[i]) {
1432 pr_err("%s: No MTU slot found for MTU: %d\n", __func__, mtu);
1433 return -EINVAL;
1434 }
1435
1436 priv->intf_mtu_count[i]--;
1437 }
1438
1439 static int rtl930x_l3_mtu_add(struct rtl838x_switch_priv *priv, int mtu)
1440 {
1441 int i, free_mtu;
1442 int mtu_id;
1443
1444 // Try to find an existing mtu-value or a free slot
1445 free_mtu = MAX_INTF_MTUS;
1446 for (i = 0; i < MAX_INTF_MTUS && priv->intf_mtus[i] != mtu; i++) {
1447 if ((!priv->intf_mtu_count[i]) && (free_mtu == MAX_INTF_MTUS))
1448 free_mtu = i;
1449 }
1450 i = (i < MAX_INTF_MTUS) ? i : free_mtu;
1451 if (i < MAX_INTF_MTUS) {
1452 mtu_id = i;
1453 } else {
1454 pr_err("%s: No free MTU slot available!\n", __func__);
1455 return -EINVAL;
1456 }
1457
1458 priv->intf_mtus[i] = mtu;
1459 pr_info("Writing MTU %d to slot %d\n", priv->intf_mtus[i], i);
1460 // Set MTU-value of the slot TODO: distinguish between IPv4/IPv6 routes / slots
1461 sw_w32_mask(0xffff << ((i % 2) * 16), priv->intf_mtus[i] << ((i % 2) * 16),
1462 RTL930X_L3_IP_MTU_CTRL(i));
1463 sw_w32_mask(0xffff << ((i % 2) * 16), priv->intf_mtus[i] << ((i % 2) * 16),
1464 RTL930X_L3_IP6_MTU_CTRL(i));
1465
1466 priv->intf_mtu_count[i]++;
1467
1468 return mtu_id;
1469 }
1470
1471 /*
1472 * Creates an interface for a route by setting up the HW tables in the SoC
1473 */
1474 static int rtl930x_l3_intf_add(struct rtl838x_switch_priv *priv, struct rtl838x_l3_intf *intf)
1475 {
1476 int i, intf_id, mtu_id;
1477 // number of MTU-values < 16384
1478
1479 // Use the same IPv6 mtu as the ip4 mtu for this route if unset
1480 intf->ip6_mtu = intf->ip6_mtu ? intf->ip6_mtu : intf->ip4_mtu;
1481
1482 mtu_id = rtl930x_l3_mtu_add(priv, intf->ip4_mtu);
1483 pr_info("%s: added mtu %d with mtu-id %d\n", __func__, intf->ip4_mtu, mtu_id);
1484 if (mtu_id < 0)
1485 return -ENOSPC;
1486 intf->ip4_mtu_id = mtu_id;
1487 intf->ip6_mtu_id = mtu_id;
1488
1489 for (i = 0; i < MAX_INTERFACES; i++) {
1490 if (!priv->interfaces[i])
1491 break;
1492 }
1493 if (i >= MAX_INTERFACES) {
1494 pr_err("%s: cannot find free interface entry\n", __func__);
1495 return -EINVAL;
1496 }
1497 intf_id = i;
1498 priv->interfaces[i] = kzalloc(sizeof(struct rtl838x_l3_intf), GFP_KERNEL);
1499 if (!priv->interfaces[i]) {
1500 pr_err("%s: no memory to allocate new interface\n", __func__);
1501 return -ENOMEM;
1502 }
1503 }
1504
1505 /*
1506 * Set the destination MAC and L3 egress interface ID for a nexthop entry in the SoC's
1507 * L3_NEXTHOP table. The nexthop entry is identified by idx.
1508 * dmac_id is the reference to the L2 entry in the L2 forwarding table, special values are
1509 * 0x7ffe: TRAP2CPU
1510 * 0x7ffd: TRAP2MASTERCPU
1511 * 0x7fff: DMAC_ID_DROP
1512 */
1513 static void rtl930x_set_l3_nexthop(int idx, u16 dmac_id, u16 interface)
1514 {
1515 // Access L3_NEXTHOP table (3) via register RTL9300_TBL_1
1516 struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 3);
1517
1518 pr_info("%s: Writing to L3_NEXTHOP table, index %d, dmac_id %d, interface %d\n",
1519 __func__, idx, dmac_id, interface);
1520 sw_w32(((dmac_id & 0x7fff) << 7) | (interface & 0x7f), rtl_table_data(r, 0));
1521
1522 pr_info("%s: %08x\n", __func__, sw_r32(rtl_table_data(r,0)));
1523 rtl_table_write(r, idx);
1524 rtl_table_release(r);
1525 }
1526
1527 static void rtl930x_pie_lookup_enable(struct rtl838x_switch_priv *priv, int index)
1528 {
1529 int block = index / PIE_BLOCK_SIZE;
1530
1531 sw_w32_mask(0, BIT(block), RTL930X_PIE_BLK_LOOKUP_CTRL);
1532 }
1533
1534 /*
1535 * Reads the intermediate representation of the templated match-fields of the
1536 * PIE rule in the pie_rule structure and fills in the raw data fields in the
1537 * raw register space r[].
1538 * The register space configuration size is identical for the RTL8380/90 and RTL9300,
1539 * however the RTL9310 has 2 more registers / fields and the physical field-ids are different
1540 * on all SoCs
1541 * On the RTL9300 the mask fields are not word-aligend!
1542 */
1543 static void rtl930x_write_pie_templated(u32 r[], struct pie_rule *pr, enum template_field_id t[])
1544 {
1545 int i;
1546 enum template_field_id field_type;
1547 u16 data, data_m;
1548
1549 for (i = 0; i < N_FIXED_FIELDS; i++) {
1550 field_type = t[i];
1551 data = data_m = 0;
1552
1553 switch (field_type) {
1554 case TEMPLATE_FIELD_SPM0:
1555 data = pr->spm;
1556 data_m = pr->spm_m;
1557 break;
1558 case TEMPLATE_FIELD_SPM1:
1559 data = pr->spm >> 16;
1560 data_m = pr->spm_m >> 16;
1561 break;
1562 case TEMPLATE_FIELD_OTAG:
1563 data = pr->otag;
1564 data_m = pr->otag_m;
1565 break;
1566 case TEMPLATE_FIELD_SMAC0:
1567 data = pr->smac[4];
1568 data = (data << 8) | pr->smac[5];
1569 data_m = pr->smac_m[4];
1570 data_m = (data_m << 8) | pr->smac_m[5];
1571 break;
1572 case TEMPLATE_FIELD_SMAC1:
1573 data = pr->smac[2];
1574 data = (data << 8) | pr->smac[3];
1575 data_m = pr->smac_m[2];
1576 data_m = (data_m << 8) | pr->smac_m[3];
1577 break;
1578 case TEMPLATE_FIELD_SMAC2:
1579 data = pr->smac[0];
1580 data = (data << 8) | pr->smac[1];
1581 data_m = pr->smac_m[0];
1582 data_m = (data_m << 8) | pr->smac_m[1];
1583 break;
1584 case TEMPLATE_FIELD_DMAC0:
1585 data = pr->dmac[4];
1586 data = (data << 8) | pr->dmac[5];
1587 data_m = pr->dmac_m[4];
1588 data_m = (data_m << 8) | pr->dmac_m[5];
1589 break;
1590 case TEMPLATE_FIELD_DMAC1:
1591 data = pr->dmac[2];
1592 data = (data << 8) | pr->dmac[3];
1593 data_m = pr->dmac_m[2];
1594 data_m = (data_m << 8) | pr->dmac_m[3];
1595 break;
1596 case TEMPLATE_FIELD_DMAC2:
1597 data = pr->dmac[0];
1598 data = (data << 8) | pr->dmac[1];
1599 data_m = pr->dmac_m[0];
1600 data_m = (data_m << 8) | pr->dmac_m[1];
1601 break;
1602 case TEMPLATE_FIELD_ETHERTYPE:
1603 data = pr->ethertype;
1604 data_m = pr->ethertype_m;
1605 break;
1606 case TEMPLATE_FIELD_ITAG:
1607 data = pr->itag;
1608 data_m = pr->itag_m;
1609 break;
1610 case TEMPLATE_FIELD_SIP0:
1611 if (pr->is_ipv6) {
1612 data = pr->sip6.s6_addr16[7];
1613 data_m = pr->sip6_m.s6_addr16[7];
1614 } else {
1615 data = pr->sip;
1616 data_m = pr->sip_m;
1617 }
1618 break;
1619 case TEMPLATE_FIELD_SIP1:
1620 if (pr->is_ipv6) {
1621 data = pr->sip6.s6_addr16[6];
1622 data_m = pr->sip6_m.s6_addr16[6];
1623 } else {
1624 data = pr->sip >> 16;
1625 data_m = pr->sip_m >> 16;
1626 }
1627 break;
1628
1629 case TEMPLATE_FIELD_SIP2:
1630 case TEMPLATE_FIELD_SIP3:
1631 case TEMPLATE_FIELD_SIP4:
1632 case TEMPLATE_FIELD_SIP5:
1633 case TEMPLATE_FIELD_SIP6:
1634 case TEMPLATE_FIELD_SIP7:
1635 data = pr->sip6.s6_addr16[5 - (field_type - TEMPLATE_FIELD_SIP2)];
1636 data_m = pr->sip6_m.s6_addr16[5 - (field_type - TEMPLATE_FIELD_SIP2)];
1637 break;
1638
1639 case TEMPLATE_FIELD_DIP0:
1640 if (pr->is_ipv6) {
1641 data = pr->dip6.s6_addr16[7];
1642 data_m = pr->dip6_m.s6_addr16[7];
1643 } else {
1644 data = pr->dip;
1645 data_m = pr->dip_m;
1646 }
1647 break;
1648
1649 case TEMPLATE_FIELD_DIP1:
1650 if (pr->is_ipv6) {
1651 data = pr->dip6.s6_addr16[6];
1652 data_m = pr->dip6_m.s6_addr16[6];
1653 } else {
1654 data = pr->dip >> 16;
1655 data_m = pr->dip_m >> 16;
1656 }
1657 break;
1658
1659 case TEMPLATE_FIELD_DIP2:
1660 case TEMPLATE_FIELD_DIP3:
1661 case TEMPLATE_FIELD_DIP4:
1662 case TEMPLATE_FIELD_DIP5:
1663 case TEMPLATE_FIELD_DIP6:
1664 case TEMPLATE_FIELD_DIP7:
1665 data = pr->dip6.s6_addr16[5 - (field_type - TEMPLATE_FIELD_DIP2)];
1666 data_m = pr->dip6_m.s6_addr16[5 - (field_type - TEMPLATE_FIELD_DIP2)];
1667 break;
1668
1669 case TEMPLATE_FIELD_IP_TOS_PROTO:
1670 data = pr->tos_proto;
1671 data_m = pr->tos_proto_m;
1672 break;
1673 case TEMPLATE_FIELD_L4_SPORT:
1674 data = pr->sport;
1675 data_m = pr->sport_m;
1676 break;
1677 case TEMPLATE_FIELD_L4_DPORT:
1678 data = pr->dport;
1679 data_m = pr->dport_m;
1680 break;
1681 case TEMPLATE_FIELD_DSAP_SSAP:
1682 data = pr->dsap_ssap;
1683 data_m = pr->dsap_ssap_m;
1684 break;
1685 case TEMPLATE_FIELD_TCP_INFO:
1686 data = pr->tcp_info;
1687 data_m = pr->tcp_info_m;
1688 break;
1689 case TEMPLATE_FIELD_RANGE_CHK:
1690 pr_warn("Warning: TEMPLATE_FIELD_RANGE_CHK: not configured\n");
1691 break;
1692 default:
1693 pr_info("%s: unknown field %d\n", __func__, field_type);
1694 }
1695
1696 // On the RTL9300, the mask fields are not word aligned!
1697 if (!(i % 2)) {
1698 r[5 - i / 2] = data;
1699 r[12 - i / 2] |= ((u32)data_m << 8);
1700 } else {
1701 r[5 - i / 2] |= ((u32)data) << 16;
1702 r[12 - i / 2] |= ((u32)data_m) << 24;
1703 r[11 - i / 2] |= ((u32)data_m) >> 8;
1704 }
1705 }
1706 }
1707
1708 static void rtl930x_read_pie_fixed_fields(u32 r[], struct pie_rule *pr)
1709 {
1710 pr->stacking_port = r[6] & BIT(31);
1711 pr->spn = (r[6] >> 24) & 0x7f;
1712 pr->mgnt_vlan = r[6] & BIT(23);
1713 if (pr->phase == PHASE_IACL)
1714 pr->dmac_hit_sw = r[6] & BIT(22);
1715 else
1716 pr->content_too_deep = r[6] & BIT(22);
1717 pr->not_first_frag = r[6] & BIT(21);
1718 pr->frame_type_l4 = (r[6] >> 18) & 7;
1719 pr->frame_type = (r[6] >> 16) & 3;
1720 pr->otag_fmt = (r[6] >> 15) & 1;
1721 pr->itag_fmt = (r[6] >> 14) & 1;
1722 pr->otag_exist = (r[6] >> 13) & 1;
1723 pr->itag_exist = (r[6] >> 12) & 1;
1724 pr->frame_type_l2 = (r[6] >> 10) & 3;
1725 pr->igr_normal_port = (r[6] >> 9) & 1;
1726 pr->tid = (r[6] >> 8) & 1;
1727
1728 pr->stacking_port_m = r[12] & BIT(7);
1729 pr->spn_m = r[12] & 0x7f;
1730 pr->mgnt_vlan_m = r[13] & BIT(31);
1731 if (pr->phase == PHASE_IACL)
1732 pr->dmac_hit_sw_m = r[13] & BIT(30);
1733 else
1734 pr->content_too_deep_m = r[13] & BIT(30);
1735 pr->not_first_frag_m = r[13] & BIT(29);
1736 pr->frame_type_l4_m = (r[13] >> 26) & 7;
1737 pr->frame_type_m = (r[13] >> 24) & 3;
1738 pr->otag_fmt_m = r[13] & BIT(23);
1739 pr->itag_fmt_m = r[13] & BIT(22);
1740 pr->otag_exist_m = r[13] & BIT(21);
1741 pr->itag_exist_m = r[13] & BIT (20);
1742 pr->frame_type_l2_m = (r[13] >> 18) & 3;
1743 pr->igr_normal_port_m = r[13] & BIT(17);
1744 pr->tid_m = (r[13] >> 16) & 1;
1745
1746 pr->valid = r[13] & BIT(15);
1747 pr->cond_not = r[13] & BIT(14);
1748 pr->cond_and1 = r[13] & BIT(13);
1749 pr->cond_and2 = r[13] & BIT(12);
1750 }
1751
1752 static void rtl930x_write_pie_fixed_fields(u32 r[], struct pie_rule *pr)
1753 {
1754 r[6] = pr->stacking_port ? BIT(31) : 0;
1755 r[6] |= ((u32) (pr->spn & 0x7f)) << 24;
1756 r[6] |= pr->mgnt_vlan ? BIT(23) : 0;
1757 if (pr->phase == PHASE_IACL)
1758 r[6] |= pr->dmac_hit_sw ? BIT(22) : 0;
1759 else
1760 r[6] |= pr->content_too_deep ? BIT(22) : 0;
1761 r[6] |= pr->not_first_frag ? BIT(21) : 0;
1762 r[6] |= ((u32) (pr->frame_type_l4 & 0x7)) << 18;
1763 r[6] |= ((u32) (pr->frame_type & 0x3)) << 16;
1764 r[6] |= pr->otag_fmt ? BIT(15) : 0;
1765 r[6] |= pr->itag_fmt ? BIT(14) : 0;
1766 r[6] |= pr->otag_exist ? BIT(13) : 0;
1767 r[6] |= pr->itag_exist ? BIT(12) : 0;
1768 r[6] |= ((u32) (pr->frame_type_l2 & 0x3)) << 10;
1769 r[6] |= pr->igr_normal_port ? BIT(9) : 0;
1770 r[6] |= ((u32) (pr->tid & 0x1)) << 8;
1771
1772 r[12] |= pr->stacking_port_m ? BIT(7) : 0;
1773 r[12] |= (u32) (pr->spn_m & 0x7f);
1774 r[13] |= pr->mgnt_vlan_m ? BIT(31) : 0;
1775 if (pr->phase == PHASE_IACL)
1776 r[13] |= pr->dmac_hit_sw_m ? BIT(30) : 0;
1777 else
1778 r[13] |= pr->content_too_deep_m ? BIT(30) : 0;
1779 r[13] |= pr->not_first_frag_m ? BIT(29) : 0;
1780 r[13] |= ((u32) (pr->frame_type_l4_m & 0x7)) << 26;
1781 r[13] |= ((u32) (pr->frame_type_m & 0x3)) << 24;
1782 r[13] |= pr->otag_fmt_m ? BIT(23) : 0;
1783 r[13] |= pr->itag_fmt_m ? BIT(22) : 0;
1784 r[13] |= pr->otag_exist_m ? BIT(21) : 0;
1785 r[13] |= pr->itag_exist_m ? BIT(20) : 0;
1786 r[13] |= ((u32) (pr->frame_type_l2_m & 0x3)) << 18;
1787 r[13] |= pr->igr_normal_port_m ? BIT(17) : 0;
1788 r[13] |= ((u32) (pr->tid_m & 0x1)) << 16;
1789
1790 r[13] |= pr->valid ? BIT(15) : 0;
1791 r[13] |= pr->cond_not ? BIT(14) : 0;
1792 r[13] |= pr->cond_and1 ? BIT(13) : 0;
1793 r[13] |= pr->cond_and2 ? BIT(12) : 0;
1794 }
1795
1796 static void rtl930x_write_pie_action(u32 r[], struct pie_rule *pr)
1797 {
1798 // Either drop or forward
1799 if (pr->drop) {
1800 r[14] |= BIT(24) | BIT(25) | BIT(26); // Do Green, Yellow and Red drops
1801 // Actually DROP, not PERMIT in Green / Yellow / Red
1802 r[14] |= BIT(23) | BIT(22) | BIT(20);
1803 } else {
1804 r[14] |= pr->fwd_sel ? BIT(27) : 0;
1805 r[14] |= pr->fwd_act << 18;
1806 r[14] |= BIT(14); // We overwrite any drop
1807 }
1808 if (pr->phase == PHASE_VACL)
1809 r[14] |= pr->fwd_sa_lrn ? BIT(15) : 0;
1810 r[13] |= pr->bypass_sel ? BIT(5) : 0;
1811 r[13] |= pr->nopri_sel ? BIT(4) : 0;
1812 r[13] |= pr->tagst_sel ? BIT(3) : 0;
1813 r[13] |= pr->ovid_sel ? BIT(1) : 0;
1814 r[14] |= pr->ivid_sel ? BIT(31) : 0;
1815 r[14] |= pr->meter_sel ? BIT(30) : 0;
1816 r[14] |= pr->mir_sel ? BIT(29) : 0;
1817 r[14] |= pr->log_sel ? BIT(28) : 0;
1818
1819 r[14] |= ((u32)(pr->fwd_data & 0x3fff)) << 3;
1820 r[15] |= pr->log_octets ? BIT(31) : 0;
1821 r[15] |= (u32)(pr->meter_data) << 23;
1822
1823 r[15] |= ((u32)(pr->ivid_act) << 21) & 0x3;
1824 r[15] |= ((u32)(pr->ivid_data) << 9) & 0xfff;
1825 r[16] |= ((u32)(pr->ovid_act) << 30) & 0x3;
1826 r[16] |= ((u32)(pr->ovid_data) & 0xfff) << 16;
1827 r[16] |= (pr->mir_data & 0x3) << 6;
1828 r[17] |= ((u32)(pr->tagst_data) & 0xf) << 28;
1829 r[17] |= ((u32)(pr->nopri_data) & 0x7) << 25;
1830 r[17] |= pr->bypass_ibc_sc ? BIT(16) : 0;
1831 }
1832
1833 void rtl930x_pie_rule_dump_raw(u32 r[])
1834 {
1835 pr_info("Raw IACL table entry:\n");
1836 pr_info("r 0 - 7: %08x %08x %08x %08x %08x %08x %08x %08x\n",
1837 r[0], r[1], r[2], r[3], r[4], r[5], r[6], r[7]);
1838 pr_info("r 8 - 15: %08x %08x %08x %08x %08x %08x %08x %08x\n",
1839 r[8], r[9], r[10], r[11], r[12], r[13], r[14], r[15]);
1840 pr_info("r 16 - 18: %08x %08x %08x\n", r[16], r[17], r[18]);
1841 pr_info("Match : %08x %08x %08x %08x %08x %08x\n", r[0], r[1], r[2], r[3], r[4], r[5]);
1842 pr_info("Fixed : %06x\n", r[6] >> 8);
1843 pr_info("Match M: %08x %08x %08x %08x %08x %08x\n",
1844 (r[6] << 24) | (r[7] >> 8), (r[7] << 24) | (r[8] >> 8), (r[8] << 24) | (r[9] >> 8),
1845 (r[9] << 24) | (r[10] >> 8), (r[10] << 24) | (r[11] >> 8),
1846 (r[11] << 24) | (r[12] >> 8));
1847 pr_info("R[13]: %08x\n", r[13]);
1848 pr_info("Fixed M: %06x\n", ((r[12] << 16) | (r[13] >> 16)) & 0xffffff);
1849 pr_info("Valid / not / and1 / and2 : %1x\n", (r[13] >> 12) & 0xf);
1850 pr_info("r 13-16: %08x %08x %08x %08x\n", r[13], r[14], r[15], r[16]);
1851 }
1852
1853 static int rtl930x_pie_rule_write(struct rtl838x_switch_priv *priv, int idx, struct pie_rule *pr)
1854 {
1855 // Access IACL table (2) via register 0
1856 struct table_reg *q = rtl_table_get(RTL9300_TBL_0, 2);
1857 u32 r[19];
1858 int i;
1859 int block = idx / PIE_BLOCK_SIZE;
1860 u32 t_select = sw_r32(RTL930X_PIE_BLK_TMPLTE_CTRL(block));
1861
1862 pr_debug("%s: %d, t_select: %08x\n", __func__, idx, t_select);
1863
1864 for (i = 0; i < 19; i++)
1865 r[i] = 0;
1866
1867 if (!pr->valid) {
1868 rtl_table_write(q, idx);
1869 rtl_table_release(q);
1870 return 0;
1871 }
1872 rtl930x_write_pie_fixed_fields(r, pr);
1873
1874 pr_debug("%s: template %d\n", __func__, (t_select >> (pr->tid * 4)) & 0xf);
1875 rtl930x_write_pie_templated(r, pr, fixed_templates[(t_select >> (pr->tid * 4)) & 0xf]);
1876
1877 rtl930x_write_pie_action(r, pr);
1878
1879 // rtl930x_pie_rule_dump_raw(r);
1880
1881 for (i = 0; i < 19; i++)
1882 sw_w32(r[i], rtl_table_data(q, i));
1883
1884 rtl_table_write(q, idx);
1885 rtl_table_release(q);
1886
1887 return 0;
1888 }
1889
1890 static bool rtl930x_pie_templ_has(int t, enum template_field_id field_type)
1891 {
1892 int i;
1893 enum template_field_id ft;
1894
1895 for (i = 0; i < N_FIXED_FIELDS; i++) {
1896 ft = fixed_templates[t][i];
1897 if (field_type == ft)
1898 return true;
1899 }
1900
1901 return false;
1902 }
1903
1904 /*
1905 * Verify that the rule pr is compatible with a given template t in block block
1906 * Note that this function is SoC specific since the values of e.g. TEMPLATE_FIELD_SIP0
1907 * depend on the SoC
1908 */
1909 static int rtl930x_pie_verify_template(struct rtl838x_switch_priv *priv,
1910 struct pie_rule *pr, int t, int block)
1911 {
1912 int i;
1913
1914 if (!pr->is_ipv6 && pr->sip_m && !rtl930x_pie_templ_has(t, TEMPLATE_FIELD_SIP0))
1915 return -1;
1916
1917 if (!pr->is_ipv6 && pr->dip_m && !rtl930x_pie_templ_has(t, TEMPLATE_FIELD_DIP0))
1918 return -1;
1919
1920 if (pr->is_ipv6) {
1921 if ((pr->sip6_m.s6_addr32[0] || pr->sip6_m.s6_addr32[1]
1922 || pr->sip6_m.s6_addr32[2] || pr->sip6_m.s6_addr32[3])
1923 && !rtl930x_pie_templ_has(t, TEMPLATE_FIELD_SIP2))
1924 return -1;
1925 if ((pr->dip6_m.s6_addr32[0] || pr->dip6_m.s6_addr32[1]
1926 || pr->dip6_m.s6_addr32[2] || pr->dip6_m.s6_addr32[3])
1927 && !rtl930x_pie_templ_has(t, TEMPLATE_FIELD_DIP2))
1928 return -1;
1929 }
1930
1931 if (ether_addr_to_u64(pr->smac) && !rtl930x_pie_templ_has(t, TEMPLATE_FIELD_SMAC0))
1932 return -1;
1933
1934 if (ether_addr_to_u64(pr->dmac) && !rtl930x_pie_templ_has(t, TEMPLATE_FIELD_DMAC0))
1935 return -1;
1936
1937 // TODO: Check more
1938
1939 i = find_first_zero_bit(&priv->pie_use_bm[block * 4], PIE_BLOCK_SIZE);
1940
1941 if (i >= PIE_BLOCK_SIZE)
1942 return -1;
1943
1944 return i + PIE_BLOCK_SIZE * block;
1945 }
1946
1947 static int rtl930x_pie_rule_add(struct rtl838x_switch_priv *priv, struct pie_rule *pr)
1948 {
1949 int idx, block, j, t;
1950 int min_block = 0;
1951 int max_block = priv->n_pie_blocks / 2;
1952
1953 if (pr->is_egress) {
1954 min_block = max_block;
1955 max_block = priv->n_pie_blocks;
1956 }
1957 pr_debug("In %s\n", __func__);
1958
1959 mutex_lock(&priv->pie_mutex);
1960
1961 for (block = min_block; block < max_block; block++) {
1962 for (j = 0; j < 2; j++) {
1963 t = (sw_r32(RTL930X_PIE_BLK_TMPLTE_CTRL(block)) >> (j * 4)) & 0xf;
1964 pr_debug("Testing block %d, template %d, template id %d\n", block, j, t);
1965 pr_debug("%s: %08x\n",
1966 __func__, sw_r32(RTL930X_PIE_BLK_TMPLTE_CTRL(block)));
1967 idx = rtl930x_pie_verify_template(priv, pr, t, block);
1968 if (idx >= 0)
1969 break;
1970 }
1971 if (j < 2)
1972 break;
1973 }
1974
1975 if (block >= priv->n_pie_blocks) {
1976 mutex_unlock(&priv->pie_mutex);
1977 return -EOPNOTSUPP;
1978 }
1979
1980 pr_debug("Using block: %d, index %d, template-id %d\n", block, idx, j);
1981 set_bit(idx, priv->pie_use_bm);
1982
1983 pr->valid = true;
1984 pr->tid = j; // Mapped to template number
1985 pr->tid_m = 0x1;
1986 pr->id = idx;
1987
1988 rtl930x_pie_lookup_enable(priv, idx);
1989 rtl930x_pie_rule_write(priv, idx, pr);
1990
1991 mutex_unlock(&priv->pie_mutex);
1992 return 0;
1993 }
1994
1995 /*
1996 * Delete a range of Packet Inspection Engine rules
1997 */
1998 static int rtl930x_pie_rule_del(struct rtl838x_switch_priv *priv, int index_from, int index_to)
1999 {
2000 u32 v = (index_from << 1)| (index_to << 12 ) | BIT(0);
2001
2002 pr_debug("%s: from %d to %d\n", __func__, index_from, index_to);
2003 mutex_lock(&priv->reg_mutex);
2004
2005 // Write from-to and execute bit into control register
2006 sw_w32(v, RTL930X_PIE_CLR_CTRL);
2007
2008 // Wait until command has completed
2009 do {
2010 } while (sw_r32(RTL930X_PIE_CLR_CTRL) & BIT(0));
2011
2012 mutex_unlock(&priv->reg_mutex);
2013 return 0;
2014 }
2015
2016 static void rtl930x_pie_rule_rm(struct rtl838x_switch_priv *priv, struct pie_rule *pr)
2017 {
2018 int idx = pr->id;
2019
2020 rtl930x_pie_rule_del(priv, idx, idx);
2021 clear_bit(idx, priv->pie_use_bm);
2022 }
2023
2024 static void rtl930x_pie_init(struct rtl838x_switch_priv *priv)
2025 {
2026 int i;
2027 u32 template_selectors;
2028
2029 mutex_init(&priv->pie_mutex);
2030
2031 pr_info("%s\n", __func__);
2032 // Enable ACL lookup on all ports, including CPU_PORT
2033 for (i = 0; i <= priv->cpu_port; i++)
2034 sw_w32(1, RTL930X_ACL_PORT_LOOKUP_CTRL(i));
2035
2036 // Include IPG in metering
2037 sw_w32_mask(0, 1, RTL930X_METER_GLB_CTRL);
2038
2039 // Delete all present rules, block size is 128 on all SoC families
2040 rtl930x_pie_rule_del(priv, 0, priv->n_pie_blocks * 128 - 1);
2041
2042 // Assign blocks 0-7 to VACL phase (bit = 0), blocks 8-15 to IACL (bit = 1)
2043 sw_w32(0xff00, RTL930X_PIE_BLK_PHASE_CTRL);
2044
2045 // Enable predefined templates 0, 1 for first quarter of all blocks
2046 template_selectors = 0 | (1 << 4);
2047 for (i = 0; i < priv->n_pie_blocks / 4; i++)
2048 sw_w32(template_selectors, RTL930X_PIE_BLK_TMPLTE_CTRL(i));
2049
2050 // Enable predefined templates 2, 3 for second quarter of all blocks
2051 template_selectors = 2 | (3 << 4);
2052 for (i = priv->n_pie_blocks / 4; i < priv->n_pie_blocks / 2; i++)
2053 sw_w32(template_selectors, RTL930X_PIE_BLK_TMPLTE_CTRL(i));
2054
2055 // Enable predefined templates 0, 1 for third half of all blocks
2056 template_selectors = 0 | (1 << 4);
2057 for (i = priv->n_pie_blocks / 2; i < priv->n_pie_blocks * 3 / 4; i++)
2058 sw_w32(template_selectors, RTL930X_PIE_BLK_TMPLTE_CTRL(i));
2059
2060 // Enable predefined templates 2, 3 for fourth quater of all blocks
2061 template_selectors = 2 | (3 << 4);
2062 for (i = priv->n_pie_blocks * 3 / 4; i < priv->n_pie_blocks; i++)
2063 sw_w32(template_selectors, RTL930X_PIE_BLK_TMPLTE_CTRL(i));
2064
2065 }
2066
2067 /*
2068 * Sets up an egress interface for L3 actions
2069 * Actions for ip4/6_icmp_redirect, ip4/6_pbr_icmp_redirect are:
2070 * 0: FORWARD, 1: DROP, 2: TRAP2CPU, 3: COPY2CPU, 4: TRAP2MASTERCPU 5: COPY2MASTERCPU
2071 * 6: HARDDROP
2072 * idx is the index in the HW interface table: idx < 0x80
2073 */
2074 static void rtl930x_set_l3_egress_intf(int idx, struct rtl838x_l3_intf *intf)
2075 {
2076 u32 u, v;
2077 // Read L3_EGR_INTF table (4) via register RTL9300_TBL_1
2078 struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 4);
2079
2080 // The table has 2 registers
2081 u = (intf->vid & 0xfff) << 9;
2082 u |= (intf->smac_idx & 0x3f) << 3;
2083 u |= (intf->ip4_mtu_id & 0x7);
2084
2085 v = (intf->ip6_mtu_id & 0x7) << 28;
2086 v |= (intf->ttl_scope & 0xff) << 20;
2087 v |= (intf->hl_scope & 0xff) << 12;
2088 v |= (intf->ip4_icmp_redirect & 0x7) << 9;
2089 v |= (intf->ip6_icmp_redirect & 0x7)<< 6;
2090 v |= (intf->ip4_pbr_icmp_redirect & 0x7) << 3;
2091 v |= (intf->ip6_pbr_icmp_redirect & 0x7);
2092
2093 sw_w32(u, rtl_table_data(r, 0));
2094 sw_w32(v, rtl_table_data(r, 1));
2095
2096 pr_info("%s writing to index %d: %08x %08x\n", __func__, idx, u, v);
2097 rtl_table_write(r, idx & 0x7f);
2098 rtl_table_release(r);
2099 }
2100
2101 /*
2102 * Reads a MAC entry for L3 termination as entry point for routing
2103 * from the hardware table
2104 * idx is the index into the L3_ROUTER_MAC table
2105 */
2106 static void rtl930x_get_l3_router_mac(u32 idx, struct rtl93xx_rt_mac *m)
2107 {
2108 u32 v, w;
2109 // Read L3_ROUTER_MAC table (0) via register RTL9300_TBL_1
2110 struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 0);
2111
2112 rtl_table_read(r, idx);
2113 // The table has a size of 7 registers, 64 entries
2114 v = sw_r32(rtl_table_data(r, 0));
2115 w = sw_r32(rtl_table_data(r, 3));
2116 m->valid = !!(v & BIT(20));
2117 if (!m->valid)
2118 goto out;
2119
2120 m->p_type = !!(v & BIT(19));
2121 m->p_id = (v >> 13) & 0x3f; // trunk id of port
2122 m->vid = v & 0xfff;
2123 m->vid_mask = w & 0xfff;
2124 m->action = sw_r32(rtl_table_data(r, 6)) & 0x7;
2125 m->mac_mask = ((((u64)sw_r32(rtl_table_data(r, 5))) << 32) & 0xffffffffffffULL)
2126 | (sw_r32(rtl_table_data(r, 4)));
2127 m->mac = ((((u64)sw_r32(rtl_table_data(r, 1))) << 32) & 0xffffffffffffULL)
2128 | (sw_r32(rtl_table_data(r, 2)));
2129 // Bits L3_INTF and BMSK_L3_INTF are 0
2130
2131 out:
2132 rtl_table_release(r);
2133 }
2134
2135 /*
2136 * Writes a MAC entry for L3 termination as entry point for routing
2137 * into the hardware table
2138 * idx is the index into the L3_ROUTER_MAC table
2139 */
2140 static void rtl930x_set_l3_router_mac(u32 idx, struct rtl93xx_rt_mac *m)
2141 {
2142 u32 v, w;
2143 // Read L3_ROUTER_MAC table (0) via register RTL9300_TBL_1
2144 struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 0);
2145
2146 // The table has a size of 7 registers, 64 entries
2147 v = BIT(20); // mac entry valid, port type is 0: individual
2148 v |= (m->p_id & 0x3f) << 13;
2149 v |= (m->vid & 0xfff); // Set the interface_id to the vlan id
2150
2151 w = m->vid_mask;
2152 w |= (m->p_id_mask & 0x3f) << 13;
2153
2154 sw_w32(v, rtl_table_data(r, 0));
2155 sw_w32(w, rtl_table_data(r, 3));
2156
2157 // Set MAC address, L3_INTF (bit 12 in register 1) needs to be 0
2158 sw_w32((u32)(m->mac), rtl_table_data(r, 2));
2159 sw_w32(m->mac >> 32, rtl_table_data(r, 1));
2160
2161 // Set MAC address mask, BMSK_L3_INTF (bit 12 in register 5) needs to be 0
2162 sw_w32((u32)(m->mac_mask >> 32), rtl_table_data(r, 4));
2163 sw_w32((u32)m->mac_mask, rtl_table_data(r, 5));
2164
2165 sw_w32(m->action & 0x7, rtl_table_data(r, 6));
2166
2167 pr_debug("%s writing index %d: %08x %08x %08x %08x %08x %08x %08x\n", __func__, idx,
2168 sw_r32(rtl_table_data(r, 0)), sw_r32(rtl_table_data(r, 1)), sw_r32(rtl_table_data(r, 2)),
2169 sw_r32(rtl_table_data(r, 3)), sw_r32(rtl_table_data(r, 4)), sw_r32(rtl_table_data(r, 5)),
2170 sw_r32(rtl_table_data(r, 6))
2171 );
2172 rtl_table_write(r, idx);
2173 rtl_table_release(r);
2174 }
2175
2176 /*
2177 * Get the Destination-MAC of an L3 egress interface or the Source MAC for routed packets
2178 * from the SoC's L3_EGR_INTF_MAC table
2179 * Indexes 0-2047 are DMACs, 2048+ are SMACs
2180 */
2181 static u64 rtl930x_get_l3_egress_mac(u32 idx)
2182 {
2183 u64 mac;
2184 // Read L3_EGR_INTF_MAC table (2) via register RTL9300_TBL_2
2185 struct table_reg *r = rtl_table_get(RTL9300_TBL_2, 2);
2186
2187 rtl_table_read(r, idx);
2188 // The table has a size of 2 registers
2189 mac = sw_r32(rtl_table_data(r, 0));
2190 mac <<= 32;
2191 mac |= sw_r32(rtl_table_data(r, 1));
2192 rtl_table_release(r);
2193
2194 return mac;
2195 }
2196 /*
2197 * Set the Destination-MAC of a route or the Source MAC of an L3 egress interface
2198 * in the SoC's L3_EGR_INTF_MAC table
2199 * Indexes 0-2047 are DMACs, 2048+ are SMACs
2200 */
2201 static void rtl930x_set_l3_egress_mac(u32 idx, u64 mac)
2202 {
2203 // Access L3_EGR_INTF_MAC table (2) via register RTL9300_TBL_2
2204 struct table_reg *r = rtl_table_get(RTL9300_TBL_2, 2);
2205
2206 // The table has a size of 2 registers
2207 sw_w32(mac >> 32, rtl_table_data(r, 0));
2208 sw_w32(mac, rtl_table_data(r, 1));
2209
2210 pr_debug("%s: setting index %d to %016llx\n", __func__, idx, mac);
2211 rtl_table_write(r, idx);
2212 rtl_table_release(r);
2213 }
2214
2215 /*
2216 * Configure L3 routing settings of the device:
2217 * - MTUs
2218 * - Egress interface
2219 * - The router's MAC address on which routed packets are expected
2220 * - MAC addresses used as source macs of routed packets
2221 */
2222 int rtl930x_l3_setup(struct rtl838x_switch_priv *priv)
2223 {
2224 int i;
2225
2226 // Setup MTU with id 0 for default interface
2227 for (i = 0; i < MAX_INTF_MTUS; i++)
2228 priv->intf_mtu_count[i] = priv->intf_mtus[i] = 0;
2229
2230 priv->intf_mtu_count[0] = 0; // Needs to stay forever
2231 priv->intf_mtus[0] = DEFAULT_MTU;
2232 sw_w32_mask(0xffff, DEFAULT_MTU, RTL930X_L3_IP_MTU_CTRL(0));
2233 sw_w32_mask(0xffff, DEFAULT_MTU, RTL930X_L3_IP6_MTU_CTRL(0));
2234 priv->intf_mtus[1] = DEFAULT_MTU;
2235 sw_w32_mask(0xffff0000, DEFAULT_MTU << 16, RTL930X_L3_IP_MTU_CTRL(0));
2236 sw_w32_mask(0xffff0000, DEFAULT_MTU << 16, RTL930X_L3_IP6_MTU_CTRL(0));
2237
2238 sw_w32_mask(0xffff, DEFAULT_MTU, RTL930X_L3_IP_MTU_CTRL(1));
2239 sw_w32_mask(0xffff, DEFAULT_MTU, RTL930X_L3_IP6_MTU_CTRL(1));
2240 sw_w32_mask(0xffff0000, DEFAULT_MTU << 16, RTL930X_L3_IP_MTU_CTRL(1));
2241 sw_w32_mask(0xffff0000, DEFAULT_MTU << 16, RTL930X_L3_IP6_MTU_CTRL(1));
2242
2243 // Clear all source port MACs
2244 for (i = 0; i < MAX_SMACS; i++)
2245 rtl930x_set_l3_egress_mac(L3_EGRESS_DMACS + i, 0ULL);
2246
2247 // Configure the default L3 hash algorithm
2248 sw_w32_mask(BIT(2), 0, RTL930X_L3_HOST_TBL_CTRL); // Algorithm selection 0 = 0
2249 sw_w32_mask(0, BIT(3), RTL930X_L3_HOST_TBL_CTRL); // Algorithm selection 1 = 1
2250
2251 pr_info("L3_IPUC_ROUTE_CTRL %08x, IPMC_ROUTE %08x, IP6UC_ROUTE %08x, IP6MC_ROUTE %08x\n",
2252 sw_r32(RTL930X_L3_IPUC_ROUTE_CTRL), sw_r32(RTL930X_L3_IPMC_ROUTE_CTRL),
2253 sw_r32(RTL930X_L3_IP6UC_ROUTE_CTRL), sw_r32(RTL930X_L3_IP6MC_ROUTE_CTRL));
2254 sw_w32_mask(0, 1, RTL930X_L3_IPUC_ROUTE_CTRL);
2255 sw_w32_mask(0, 1, RTL930X_L3_IP6UC_ROUTE_CTRL);
2256 sw_w32_mask(0, 1, RTL930X_L3_IPMC_ROUTE_CTRL);
2257 sw_w32_mask(0, 1, RTL930X_L3_IP6MC_ROUTE_CTRL);
2258
2259 sw_w32(0x00002001, RTL930X_L3_IPUC_ROUTE_CTRL);
2260 sw_w32(0x00014581, RTL930X_L3_IP6UC_ROUTE_CTRL);
2261 sw_w32(0x00000501, RTL930X_L3_IPMC_ROUTE_CTRL);
2262 sw_w32(0x00012881, RTL930X_L3_IP6MC_ROUTE_CTRL);
2263
2264 pr_info("L3_IPUC_ROUTE_CTRL %08x, IPMC_ROUTE %08x, IP6UC_ROUTE %08x, IP6MC_ROUTE %08x\n",
2265 sw_r32(RTL930X_L3_IPUC_ROUTE_CTRL), sw_r32(RTL930X_L3_IPMC_ROUTE_CTRL),
2266 sw_r32(RTL930X_L3_IP6UC_ROUTE_CTRL), sw_r32(RTL930X_L3_IP6MC_ROUTE_CTRL));
2267
2268 // Trap non-ip traffic to the CPU-port (e.g. ARP so we stay reachable)
2269 sw_w32_mask(0x3 << 8, 0x1 << 8, RTL930X_L3_IP_ROUTE_CTRL);
2270 pr_info("L3_IP_ROUTE_CTRL %08x\n", sw_r32(RTL930X_L3_IP_ROUTE_CTRL));
2271
2272 // PORT_ISO_RESTRICT_ROUTE_CTRL ?
2273
2274 // Do not use prefix route 0 because of HW limitations
2275 set_bit(0, priv->route_use_bm);
2276
2277 return 0;
2278 }
2279
2280 static u32 rtl930x_packet_cntr_read(int counter)
2281 {
2282 u32 v;
2283
2284 // Read LOG table (3) via register RTL9300_TBL_0
2285 struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 3);
2286
2287 pr_debug("In %s, id %d\n", __func__, counter);
2288 rtl_table_read(r, counter / 2);
2289
2290 pr_debug("Registers: %08x %08x\n",
2291 sw_r32(rtl_table_data(r, 0)), sw_r32(rtl_table_data(r, 1)));
2292 // The table has a size of 2 registers
2293 if (counter % 2)
2294 v = sw_r32(rtl_table_data(r, 0));
2295 else
2296 v = sw_r32(rtl_table_data(r, 1));
2297
2298 rtl_table_release(r);
2299
2300 return v;
2301 }
2302
2303 static void rtl930x_packet_cntr_clear(int counter)
2304 {
2305 // Access LOG table (3) via register RTL9300_TBL_0
2306 struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 3);
2307
2308 pr_info("In %s, id %d\n", __func__, counter);
2309 // The table has a size of 2 registers
2310 if (counter % 2)
2311 sw_w32(0, rtl_table_data(r, 0));
2312 else
2313 sw_w32(0, rtl_table_data(r, 1));
2314
2315 rtl_table_write(r, counter / 2);
2316
2317 rtl_table_release(r);
2318 }
2319
2320 const struct rtl838x_reg rtl930x_reg = {
2321 .mask_port_reg_be = rtl838x_mask_port_reg,
2322 .set_port_reg_be = rtl838x_set_port_reg,
2323 .get_port_reg_be = rtl838x_get_port_reg,
2324 .mask_port_reg_le = rtl838x_mask_port_reg,
2325 .set_port_reg_le = rtl838x_set_port_reg,
2326 .get_port_reg_le = rtl838x_get_port_reg,
2327 .stat_port_rst = RTL930X_STAT_PORT_RST,
2328 .stat_rst = RTL930X_STAT_RST,
2329 .stat_port_std_mib = RTL930X_STAT_PORT_MIB_CNTR,
2330 .traffic_enable = rtl930x_traffic_enable,
2331 .traffic_disable = rtl930x_traffic_disable,
2332 .traffic_get = rtl930x_traffic_get,
2333 .traffic_set = rtl930x_traffic_set,
2334 .l2_ctrl_0 = RTL930X_L2_CTRL,
2335 .l2_ctrl_1 = RTL930X_L2_AGE_CTRL,
2336 .l2_port_aging_out = RTL930X_L2_PORT_AGE_CTRL,
2337 .smi_poll_ctrl = RTL930X_SMI_POLL_CTRL, // TODO: Difference to RTL9300_SMI_PRVTE_POLLING_CTRL
2338 .l2_tbl_flush_ctrl = RTL930X_L2_TBL_FLUSH_CTRL,
2339 .exec_tbl0_cmd = rtl930x_exec_tbl0_cmd,
2340 .exec_tbl1_cmd = rtl930x_exec_tbl1_cmd,
2341 .tbl_access_data_0 = rtl930x_tbl_access_data_0,
2342 .isr_glb_src = RTL930X_ISR_GLB,
2343 .isr_port_link_sts_chg = RTL930X_ISR_PORT_LINK_STS_CHG,
2344 .imr_port_link_sts_chg = RTL930X_IMR_PORT_LINK_STS_CHG,
2345 .imr_glb = RTL930X_IMR_GLB,
2346 .vlan_tables_read = rtl930x_vlan_tables_read,
2347 .vlan_set_tagged = rtl930x_vlan_set_tagged,
2348 .vlan_set_untagged = rtl930x_vlan_set_untagged,
2349 .vlan_profile_dump = rtl930x_vlan_profile_dump,
2350 .vlan_profile_setup = rtl930x_vlan_profile_setup,
2351 .vlan_fwd_on_inner = rtl930x_vlan_fwd_on_inner,
2352 .stp_get = rtl930x_stp_get,
2353 .stp_set = rtl930x_stp_set,
2354 .mac_force_mode_ctrl = rtl930x_mac_force_mode_ctrl,
2355 .mac_port_ctrl = rtl930x_mac_port_ctrl,
2356 .l2_port_new_salrn = rtl930x_l2_port_new_salrn,
2357 .l2_port_new_sa_fwd = rtl930x_l2_port_new_sa_fwd,
2358 .mir_ctrl = RTL930X_MIR_CTRL,
2359 .mir_dpm = RTL930X_MIR_DPM_CTRL,
2360 .mir_spm = RTL930X_MIR_SPM_CTRL,
2361 .mac_link_sts = RTL930X_MAC_LINK_STS,
2362 .mac_link_dup_sts = RTL930X_MAC_LINK_DUP_STS,
2363 .mac_link_spd_sts = rtl930x_mac_link_spd_sts,
2364 .mac_rx_pause_sts = RTL930X_MAC_RX_PAUSE_STS,
2365 .mac_tx_pause_sts = RTL930X_MAC_TX_PAUSE_STS,
2366 .read_l2_entry_using_hash = rtl930x_read_l2_entry_using_hash,
2367 .write_l2_entry_using_hash = rtl930x_write_l2_entry_using_hash,
2368 .read_cam = rtl930x_read_cam,
2369 .write_cam = rtl930x_write_cam,
2370 .vlan_port_egr_filter = RTL930X_VLAN_PORT_EGR_FLTR,
2371 .vlan_port_igr_filter = RTL930X_VLAN_PORT_IGR_FLTR,
2372 .vlan_port_pb = RTL930X_VLAN_PORT_PB_VLAN,
2373 .vlan_port_tag_sts_ctrl = RTL930X_VLAN_PORT_TAG_STS_CTRL,
2374 .trk_mbr_ctr = rtl930x_trk_mbr_ctr,
2375 .rma_bpdu_fld_pmask = RTL930X_RMA_BPDU_FLD_PMSK,
2376 .init_eee = rtl930x_init_eee,
2377 .port_eee_set = rtl930x_port_eee_set,
2378 .eee_port_ability = rtl930x_eee_port_ability,
2379 .l2_hash_seed = rtl930x_l2_hash_seed,
2380 .l2_hash_key = rtl930x_l2_hash_key,
2381 .read_mcast_pmask = rtl930x_read_mcast_pmask,
2382 .write_mcast_pmask = rtl930x_write_mcast_pmask,
2383 .pie_init = rtl930x_pie_init,
2384 .pie_rule_write = rtl930x_pie_rule_write,
2385 .pie_rule_add = rtl930x_pie_rule_add,
2386 .pie_rule_rm = rtl930x_pie_rule_rm,
2387 .l2_learning_setup = rtl930x_l2_learning_setup,
2388 .packet_cntr_read = rtl930x_packet_cntr_read,
2389 .packet_cntr_clear = rtl930x_packet_cntr_clear,
2390 .route_read = rtl930x_route_read,
2391 .route_write = rtl930x_route_write,
2392 .host_route_write = rtl930x_host_route_write,
2393 .l3_setup = rtl930x_l3_setup,
2394 .set_l3_nexthop = rtl930x_set_l3_nexthop,
2395 .get_l3_nexthop = rtl930x_get_l3_nexthop,
2396 .get_l3_egress_mac = rtl930x_get_l3_egress_mac,
2397 .set_l3_egress_mac = rtl930x_set_l3_egress_mac,
2398 .find_l3_slot = rtl930x_find_l3_slot,
2399 .route_lookup_hw = rtl930x_route_lookup_hw,
2400 .get_l3_router_mac = rtl930x_get_l3_router_mac,
2401 .set_l3_router_mac = rtl930x_set_l3_router_mac,
2402 .set_l3_egress_intf = rtl930x_set_l3_egress_intf,
2403 };
Staging tree of Zoltan Herpai