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realtek: reduce excessive logging for FDB operations
[openwrt/staging/ldir.git] / target / linux / realtek / files-5.10 / drivers / net / dsa / rtl83xx / rtl930x.c
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <asm/mach-rtl838x/mach-rtl83xx.h>
4 #include <linux/inetdevice.h>
5
6 #include "rtl83xx.h"
7
8 extern struct mutex smi_lock;
9 extern struct rtl83xx_soc_info soc_info;
10
11 /* Definition of the RTL930X-specific template field IDs as used in the PIE */
12 enum template_field_id {
13 TEMPLATE_FIELD_SPM0 = 0, // Source portmask ports 0-15
14 TEMPLATE_FIELD_SPM1 = 1, // Source portmask ports 16-31
15 TEMPLATE_FIELD_DMAC0 = 2, // Destination MAC [15:0]
16 TEMPLATE_FIELD_DMAC1 = 3, // Destination MAC [31:16]
17 TEMPLATE_FIELD_DMAC2 = 4, // Destination MAC [47:32]
18 TEMPLATE_FIELD_SMAC0 = 5, // Source MAC [15:0]
19 TEMPLATE_FIELD_SMAC1 = 6, // Source MAC [31:16]
20 TEMPLATE_FIELD_SMAC2 = 7, // Source MAC [47:32]
21 TEMPLATE_FIELD_ETHERTYPE = 8, // Ethernet frame type field
22 TEMPLATE_FIELD_OTAG = 9,
23 TEMPLATE_FIELD_ITAG = 10,
24 TEMPLATE_FIELD_SIP0 = 11,
25 TEMPLATE_FIELD_SIP1 = 12,
26 TEMPLATE_FIELD_DIP0 = 13,
27 TEMPLATE_FIELD_DIP1 = 14,
28 TEMPLATE_FIELD_IP_TOS_PROTO = 15,
29 TEMPLATE_FIELD_L4_SPORT = 16,
30 TEMPLATE_FIELD_L4_DPORT = 17,
31 TEMPLATE_FIELD_L34_HEADER = 18,
32 TEMPLATE_FIELD_TCP_INFO = 19,
33 TEMPLATE_FIELD_FIELD_SELECTOR_VALID = 20,
34 TEMPLATE_FIELD_FIELD_SELECTOR_0 = 21,
35 TEMPLATE_FIELD_FIELD_SELECTOR_1 = 22,
36 TEMPLATE_FIELD_FIELD_SELECTOR_2 = 23,
37 TEMPLATE_FIELD_FIELD_SELECTOR_3 = 24,
38 TEMPLATE_FIELD_FIELD_SELECTOR_4 = 25,
39 TEMPLATE_FIELD_FIELD_SELECTOR_5 = 26,
40 TEMPLATE_FIELD_SIP2 = 27,
41 TEMPLATE_FIELD_SIP3 = 28,
42 TEMPLATE_FIELD_SIP4 = 29,
43 TEMPLATE_FIELD_SIP5 = 30,
44 TEMPLATE_FIELD_SIP6 = 31,
45 TEMPLATE_FIELD_SIP7 = 32,
46 TEMPLATE_FIELD_DIP2 = 33,
47 TEMPLATE_FIELD_DIP3 = 34,
48 TEMPLATE_FIELD_DIP4 = 35,
49 TEMPLATE_FIELD_DIP5 = 36,
50 TEMPLATE_FIELD_DIP6 = 37,
51 TEMPLATE_FIELD_DIP7 = 38,
52 TEMPLATE_FIELD_PKT_INFO = 39,
53 TEMPLATE_FIELD_FLOW_LABEL = 40,
54 TEMPLATE_FIELD_DSAP_SSAP = 41,
55 TEMPLATE_FIELD_SNAP_OUI = 42,
56 TEMPLATE_FIELD_FWD_VID = 43,
57 TEMPLATE_FIELD_RANGE_CHK = 44,
58 TEMPLATE_FIELD_VLAN_GMSK = 45, // VLAN Group Mask/IP range check
59 TEMPLATE_FIELD_DLP = 46,
60 TEMPLATE_FIELD_META_DATA = 47,
61 TEMPLATE_FIELD_SRC_FWD_VID = 48,
62 TEMPLATE_FIELD_SLP = 49,
63 };
64
65 /* The meaning of TEMPLATE_FIELD_VLAN depends on phase and the configuration in
66 * RTL930X_PIE_CTRL. We use always the same definition and map to the inner VLAN tag:
67 */
68 #define TEMPLATE_FIELD_VLAN TEMPLATE_FIELD_ITAG
69
70 // Number of fixed templates predefined in the RTL9300 SoC
71 #define N_FIXED_TEMPLATES 5
72 // RTL9300 specific predefined templates
73 static enum template_field_id fixed_templates[N_FIXED_TEMPLATES][N_FIXED_FIELDS] =
74 {
75 {
76 TEMPLATE_FIELD_DMAC0, TEMPLATE_FIELD_DMAC1, TEMPLATE_FIELD_DMAC2,
77 TEMPLATE_FIELD_SMAC0, TEMPLATE_FIELD_SMAC1, TEMPLATE_FIELD_SMAC2,
78 TEMPLATE_FIELD_VLAN, TEMPLATE_FIELD_IP_TOS_PROTO, TEMPLATE_FIELD_DSAP_SSAP,
79 TEMPLATE_FIELD_ETHERTYPE, TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1
80 }, {
81 TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_DIP0,
82 TEMPLATE_FIELD_DIP1, TEMPLATE_FIELD_IP_TOS_PROTO, TEMPLATE_FIELD_TCP_INFO,
83 TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_L4_DPORT, TEMPLATE_FIELD_VLAN,
84 TEMPLATE_FIELD_RANGE_CHK, TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1
85 }, {
86 TEMPLATE_FIELD_DMAC0, TEMPLATE_FIELD_DMAC1, TEMPLATE_FIELD_DMAC2,
87 TEMPLATE_FIELD_VLAN, TEMPLATE_FIELD_ETHERTYPE, TEMPLATE_FIELD_IP_TOS_PROTO,
88 TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_DIP0,
89 TEMPLATE_FIELD_DIP1, TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_L4_DPORT
90 }, {
91 TEMPLATE_FIELD_DIP0, TEMPLATE_FIELD_DIP1, TEMPLATE_FIELD_DIP2,
92 TEMPLATE_FIELD_DIP3, TEMPLATE_FIELD_DIP4, TEMPLATE_FIELD_DIP5,
93 TEMPLATE_FIELD_DIP6, TEMPLATE_FIELD_DIP7, TEMPLATE_FIELD_IP_TOS_PROTO,
94 TEMPLATE_FIELD_TCP_INFO, TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_L4_DPORT
95 }, {
96 TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_SIP2,
97 TEMPLATE_FIELD_SIP3, TEMPLATE_FIELD_SIP4, TEMPLATE_FIELD_SIP5,
98 TEMPLATE_FIELD_SIP6, TEMPLATE_FIELD_SIP7, TEMPLATE_FIELD_VLAN,
99 TEMPLATE_FIELD_RANGE_CHK, TEMPLATE_FIELD_SPM1, TEMPLATE_FIELD_SPM1
100 },
101 };
102
103 void rtl930x_print_matrix(void)
104 {
105 int i;
106 struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 6);
107
108 for (i = 0; i < 29; i++) {
109 rtl_table_read(r, i);
110 pr_debug("> %08x\n", sw_r32(rtl_table_data(r, 0)));
111 }
112 rtl_table_release(r);
113 }
114
115 inline void rtl930x_exec_tbl0_cmd(u32 cmd)
116 {
117 sw_w32(cmd, RTL930X_TBL_ACCESS_CTRL_0);
118 do { } while (sw_r32(RTL930X_TBL_ACCESS_CTRL_0) & (1 << 17));
119 }
120
121 inline void rtl930x_exec_tbl1_cmd(u32 cmd)
122 {
123 sw_w32(cmd, RTL930X_TBL_ACCESS_CTRL_1);
124 do { } while (sw_r32(RTL930X_TBL_ACCESS_CTRL_1) & (1 << 17));
125 }
126
127 inline int rtl930x_tbl_access_data_0(int i)
128 {
129 return RTL930X_TBL_ACCESS_DATA_0(i);
130 }
131
132 static inline int rtl930x_l2_port_new_salrn(int p)
133 {
134 return RTL930X_L2_PORT_SALRN(p);
135 }
136
137 static inline int rtl930x_l2_port_new_sa_fwd(int p)
138 {
139 // TODO: The definition of the fields changed, because of the master-cpu in a stack
140 return RTL930X_L2_PORT_NEW_SA_FWD(p);
141 }
142
143 inline static int rtl930x_trk_mbr_ctr(int group)
144 {
145 return RTL930X_TRK_MBR_CTRL + (group << 2);
146 }
147
148 static void rtl930x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info)
149 {
150 u32 v, w;
151 // Read VLAN table (1) via register 0
152 struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 1);
153
154 rtl_table_read(r, vlan);
155 v = sw_r32(rtl_table_data(r, 0));
156 w = sw_r32(rtl_table_data(r, 1));
157 pr_debug("VLAN_READ %d: %08x %08x\n", vlan, v, w);
158 rtl_table_release(r);
159
160 info->tagged_ports = v >> 3;
161 info->profile_id = (w >> 24) & 7;
162 info->hash_mc_fid = !!(w & BIT(27));
163 info->hash_uc_fid = !!(w & BIT(28));
164 info->fid = ((v & 0x7) << 3) | ((w >> 29) & 0x7);
165
166 // Read UNTAG table via table register 2
167 r = rtl_table_get(RTL9300_TBL_2, 0);
168 rtl_table_read(r, vlan);
169 v = sw_r32(rtl_table_data(r, 0));
170 rtl_table_release(r);
171
172 info->untagged_ports = v >> 3;
173 }
174
175 static void rtl930x_vlan_set_tagged(u32 vlan, struct rtl838x_vlan_info *info)
176 {
177 u32 v, w;
178 // Access VLAN table (1) via register 0
179 struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 1);
180
181 v = info->tagged_ports << 3;
182 v |= ((u32)info->fid) >> 3;
183
184 w = ((u32)info->fid) << 29;
185 w |= info->hash_mc_fid ? BIT(27) : 0;
186 w |= info->hash_uc_fid ? BIT(28) : 0;
187 w |= info->profile_id << 24;
188
189 sw_w32(v, rtl_table_data(r, 0));
190 sw_w32(w, rtl_table_data(r, 1));
191
192 rtl_table_write(r, vlan);
193 rtl_table_release(r);
194 }
195
196 void rtl930x_vlan_profile_dump(int profile)
197 {
198 u32 p[5];
199
200 if (profile < 0 || profile > 7)
201 return;
202
203 p[0] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile));
204 p[1] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile) + 4);
205 p[2] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile) + 8) & 0x1FFFFFFF;
206 p[3] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile) + 12) & 0x1FFFFFFF;
207 p[4] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile) + 16) & 0x1FFFFFFF;
208
209 pr_info("VLAN %d: L2 learn: %d; Unknown MC PMasks: L2 %0x, IPv4 %0x, IPv6: %0x",
210 profile, p[0] & (3 << 21), p[2], p[3], p[4]);
211 pr_info(" Routing enabled: IPv4 UC %c, IPv6 UC %c, IPv4 MC %c, IPv6 MC %c\n",
212 p[0] & BIT(17) ? 'y' : 'n', p[0] & BIT(16) ? 'y' : 'n',
213 p[0] & BIT(13) ? 'y' : 'n', p[0] & BIT(12) ? 'y' : 'n');
214 pr_info(" Bridge enabled: IPv4 MC %c, IPv6 MC %c,\n",
215 p[0] & BIT(15) ? 'y' : 'n', p[0] & BIT(14) ? 'y' : 'n');
216 pr_info("VLAN profile %d: raw %08x %08x %08x %08x %08x\n",
217 profile, p[0], p[1], p[2], p[3], p[4]);
218 }
219
220 static void rtl930x_vlan_set_untagged(u32 vlan, u64 portmask)
221 {
222 struct table_reg *r = rtl_table_get(RTL9300_TBL_2, 0);
223
224 sw_w32(portmask << 3, rtl_table_data(r, 0));
225 rtl_table_write(r, vlan);
226 rtl_table_release(r);
227 }
228
229 /* Sets the L2 forwarding to be based on either the inner VLAN tag or the outer
230 */
231 static void rtl930x_vlan_fwd_on_inner(int port, bool is_set)
232 {
233 // Always set all tag modes to fwd based on either inner or outer tag
234 if (is_set)
235 sw_w32_mask(0, 0xf, RTL930X_VLAN_PORT_FWD + (port << 2));
236 else
237 sw_w32_mask(0xf, 0, RTL930X_VLAN_PORT_FWD + (port << 2));
238 }
239
240 static void rtl930x_vlan_profile_setup(int profile)
241 {
242 u32 p[5];
243
244 pr_info("In %s\n", __func__);
245 p[0] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile));
246 p[1] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile) + 4);
247
248 // Enable routing of Ipv4/6 Unicast and IPv4/6 Multicast traffic
249 p[0] |= BIT(17) | BIT(16) | BIT(13) | BIT(12);
250 p[2] = 0x1fffffff; // L2 unknown MC flooding portmask all ports, including the CPU-port
251 p[3] = 0x1fffffff; // IPv4 unknown MC flooding portmask
252 p[4] = 0x1fffffff; // IPv6 unknown MC flooding portmask
253
254 sw_w32(p[0], RTL930X_VLAN_PROFILE_SET(profile));
255 sw_w32(p[1], RTL930X_VLAN_PROFILE_SET(profile) + 4);
256 sw_w32(p[2], RTL930X_VLAN_PROFILE_SET(profile) + 8);
257 sw_w32(p[3], RTL930X_VLAN_PROFILE_SET(profile) + 12);
258 sw_w32(p[4], RTL930X_VLAN_PROFILE_SET(profile) + 16);
259 }
260
261 static void rtl930x_l2_learning_setup(void)
262 {
263 // Portmask for flooding broadcast traffic
264 sw_w32(0x1fffffff, RTL930X_L2_BC_FLD_PMSK);
265
266 // Portmask for flooding unicast traffic with unknown destination
267 sw_w32(0x1fffffff, RTL930X_L2_UNKN_UC_FLD_PMSK);
268
269 // Limit learning to maximum: 32k entries, after that just flood (bits 0-1)
270 sw_w32((0x7fff << 2) | 0, RTL930X_L2_LRN_CONSTRT_CTRL);
271 }
272
273 static void rtl930x_stp_get(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])
274 {
275 int i;
276 u32 cmd = 1 << 17 /* Execute cmd */
277 | 0 << 16 /* Read */
278 | 4 << 12 /* Table type 0b10 */
279 | (msti & 0xfff);
280 priv->r->exec_tbl0_cmd(cmd);
281
282 for (i = 0; i < 2; i++)
283 port_state[i] = sw_r32(RTL930X_TBL_ACCESS_DATA_0(i));
284 pr_debug("MSTI: %d STATE: %08x, %08x\n", msti, port_state[0], port_state[1]);
285 }
286
287 static void rtl930x_stp_set(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])
288 {
289 int i;
290 u32 cmd = 1 << 17 /* Execute cmd */
291 | 1 << 16 /* Write */
292 | 4 << 12 /* Table type 4 */
293 | (msti & 0xfff);
294
295 for (i = 0; i < 2; i++)
296 sw_w32(port_state[i], RTL930X_TBL_ACCESS_DATA_0(i));
297 priv->r->exec_tbl0_cmd(cmd);
298 }
299
300 static inline int rtl930x_mac_force_mode_ctrl(int p)
301 {
302 return RTL930X_MAC_FORCE_MODE_CTRL + (p << 2);
303 }
304
305 static inline int rtl930x_mac_port_ctrl(int p)
306 {
307 return RTL930X_MAC_L2_PORT_CTRL(p);
308 }
309
310 static inline int rtl930x_mac_link_spd_sts(int p)
311 {
312 return RTL930X_MAC_LINK_SPD_STS(p);
313 }
314
315 static u64 rtl930x_l2_hash_seed(u64 mac, u32 vid)
316 {
317 u64 v = vid;
318
319 v <<= 48;
320 v |= mac;
321
322 return v;
323 }
324
325 /*
326 * Calculate both the block 0 and the block 1 hash by applyingthe same hash
327 * algorithm as the one used currently by the ASIC to the seed, and return
328 * both hashes in the lower and higher word of the return value since only 12 bit of
329 * the hash are significant
330 */
331 static u32 rtl930x_l2_hash_key(struct rtl838x_switch_priv *priv, u64 seed)
332 {
333 u32 k0, k1, h1, h2, h;
334
335 k0 = (u32) (((seed >> 55) & 0x1f) ^ ((seed >> 44) & 0x7ff)
336 ^ ((seed >> 33) & 0x7ff) ^ ((seed >> 22) & 0x7ff)
337 ^ ((seed >> 11) & 0x7ff) ^ (seed & 0x7ff));
338
339 h1 = (seed >> 11) & 0x7ff;
340 h1 = ((h1 & 0x1f) << 6) | ((h1 >> 5) & 0x3f);
341
342 h2 = (seed >> 33) & 0x7ff;
343 h2 = ((h2 & 0x3f) << 5)| ((h2 >> 6) & 0x3f);
344
345 k1 = (u32) (((seed << 55) & 0x1f) ^ ((seed >> 44) & 0x7ff) ^ h2
346 ^ ((seed >> 22) & 0x7ff) ^ h1
347 ^ (seed & 0x7ff));
348
349 // Algorithm choice for block 0
350 if (sw_r32(RTL930X_L2_CTRL) & BIT(0))
351 h = k1;
352 else
353 h = k0;
354
355 /* Algorithm choice for block 1
356 * Since k0 and k1 are < 2048, adding 2048 will offset the hash into the second
357 * half of hash-space
358 * 2048 is in fact the hash-table size 16384 divided by 4 hashes per bucket
359 * divided by 2 to divide the hash space in 2
360 */
361 if (sw_r32(RTL930X_L2_CTRL) & BIT(1))
362 h |= (k1 + 2048) << 16;
363 else
364 h |= (k0 + 2048) << 16;
365
366 return h;
367 }
368
369 /*
370 * Fills an L2 entry structure from the SoC registers
371 */
372 static void rtl930x_fill_l2_entry(u32 r[], struct rtl838x_l2_entry *e)
373 {
374 pr_debug("In %s valid?\n", __func__);
375 e->valid = !!(r[2] & BIT(31));
376 if (!e->valid)
377 return;
378
379 pr_debug("In %s is valid\n", __func__);
380 e->is_ip_mc = false;
381 e->is_ipv6_mc = false;
382
383 // TODO: Is there not a function to copy directly MAC memory?
384 e->mac[0] = (r[0] >> 24);
385 e->mac[1] = (r[0] >> 16);
386 e->mac[2] = (r[0] >> 8);
387 e->mac[3] = r[0];
388 e->mac[4] = (r[1] >> 24);
389 e->mac[5] = (r[1] >> 16);
390
391 e->next_hop = !!(r[2] & BIT(12));
392 e->rvid = r[1] & 0xfff;
393
394 /* Is it a unicast entry? check multicast bit */
395 if (!(e->mac[0] & 1)) {
396 e->type = L2_UNICAST;
397 e->is_static = !!(r[2] & BIT(14));
398 e->port = (r[2] >> 20) & 0x3ff;
399 // Check for trunk port
400 if (r[2] & BIT(30)) {
401 e->is_trunk = true;
402 e->stack_dev = (e->port >> 9) & 1;
403 e->trunk = e->port & 0x3f;
404 } else {
405 e->is_trunk = false;
406 e->stack_dev = (e->port >> 6) & 0xf;
407 e->port = e->port & 0x3f;
408 }
409
410 e->block_da = !!(r[2] & BIT(15));
411 e->block_sa = !!(r[2] & BIT(16));
412 e->suspended = !!(r[2] & BIT(13));
413 e->age = (r[2] >> 17) & 3;
414 e->valid = true;
415 // the UC_VID field in hardware is used for the VID or for the route id
416 if (e->next_hop) {
417 e->nh_route_id = r[2] & 0x7ff;
418 e->vid = 0;
419 } else {
420 e->vid = r[2] & 0xfff;
421 e->nh_route_id = 0;
422 }
423 } else {
424 e->valid = true;
425 e->type = L2_MULTICAST;
426 e->mc_portmask_index = (r[2] >> 16) & 0x3ff;
427 }
428 }
429
430 /*
431 * Fills the 3 SoC table registers r[] with the information of in the rtl838x_l2_entry
432 */
433 static void rtl930x_fill_l2_row(u32 r[], struct rtl838x_l2_entry *e)
434 {
435 u32 port;
436
437 if (!e->valid) {
438 r[0] = r[1] = r[2] = 0;
439 return;
440 }
441
442 r[2] = BIT(31); // Set valid bit
443
444 r[0] = ((u32)e->mac[0]) << 24 | ((u32)e->mac[1]) << 16
445 | ((u32)e->mac[2]) << 8 | ((u32)e->mac[3]);
446 r[1] = ((u32)e->mac[4]) << 24 | ((u32)e->mac[5]) << 16;
447
448 r[2] |= e->next_hop ? BIT(12) : 0;
449
450 if (e->type == L2_UNICAST) {
451 r[2] |= e->is_static ? BIT(14) : 0;
452 r[1] |= e->rvid & 0xfff;
453 r[2] |= (e->port & 0x3ff) << 20;
454 if (e->is_trunk) {
455 r[2] |= BIT(30);
456 port = e->stack_dev << 9 | (e->port & 0x3f);
457 } else {
458 port = (e->stack_dev & 0xf) << 6;
459 port |= e->port & 0x3f;
460 }
461 r[2] |= port << 20;
462 r[2] |= e->block_da ? BIT(15) : 0;
463 r[2] |= e->block_sa ? BIT(17) : 0;
464 r[2] |= e->suspended ? BIT(13) : 0;
465 r[2] |= (e->age & 0x3) << 17;
466 // the UC_VID field in hardware is used for the VID or for the route id
467 if (e->next_hop)
468 r[2] |= e->nh_route_id & 0x7ff;
469 else
470 r[2] |= e->vid & 0xfff;
471 } else { // L2_MULTICAST
472 r[2] |= (e->mc_portmask_index & 0x3ff) << 16;
473 r[2] |= e->mc_mac_index & 0x7ff;
474 }
475 }
476
477 /*
478 * Read an L2 UC or MC entry out of a hash bucket of the L2 forwarding table
479 * hash is the id of the bucket and pos is the position of the entry in that bucket
480 * The data read from the SoC is filled into rtl838x_l2_entry
481 */
482 static u64 rtl930x_read_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e)
483 {
484 u32 r[3];
485 struct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 0);
486 u32 idx;
487 int i;
488 u64 mac;
489 u64 seed;
490
491 pr_debug("%s: hash %08x, pos: %d\n", __func__, hash, pos);
492
493 /* On the RTL93xx, 2 different hash algorithms are used making it a total of
494 * 8 buckets that need to be searched, 4 for each hash-half
495 * Use second hash space when bucket is between 4 and 8 */
496 if (pos >= 4) {
497 pos -= 4;
498 hash >>= 16;
499 } else {
500 hash &= 0xffff;
501 }
502
503 idx = (0 << 14) | (hash << 2) | pos; // Search SRAM, with hash and at pos in bucket
504 pr_debug("%s: NOW hash %08x, pos: %d\n", __func__, hash, pos);
505
506 rtl_table_read(q, idx);
507 for (i = 0; i < 3; i++)
508 r[i] = sw_r32(rtl_table_data(q, i));
509
510 rtl_table_release(q);
511
512 rtl930x_fill_l2_entry(r, e);
513
514 pr_debug("%s: valid: %d, nh: %d\n", __func__, e->valid, e->next_hop);
515 if (!e->valid)
516 return 0;
517
518 mac = ((u64)e->mac[0]) << 40 | ((u64)e->mac[1]) << 32 | ((u64)e->mac[2]) << 24
519 | ((u64)e->mac[3]) << 16 | ((u64)e->mac[4]) << 8 | ((u64)e->mac[5]);
520
521 seed = rtl930x_l2_hash_seed(mac, e->rvid);
522 pr_debug("%s: mac %016llx, seed %016llx\n", __func__, mac, seed);
523 // return vid with concatenated mac as unique id
524 return seed;
525 }
526
527 static void rtl930x_write_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e)
528 {
529 u32 r[3];
530 struct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 0);
531 u32 idx = (0 << 14) | (hash << 2) | pos; // Access SRAM, with hash and at pos in bucket
532 int i;
533
534 pr_debug("%s: hash %d, pos %d\n", __func__, hash, pos);
535 pr_debug("%s: index %d -> mac %02x:%02x:%02x:%02x:%02x:%02x\n", __func__, idx,
536 e->mac[0], e->mac[1], e->mac[2], e->mac[3],e->mac[4],e->mac[5]);
537
538 rtl930x_fill_l2_row(r, e);
539
540 for (i= 0; i < 3; i++)
541 sw_w32(r[i], rtl_table_data(q, i));
542
543 rtl_table_write(q, idx);
544 rtl_table_release(q);
545 }
546
547 static u64 rtl930x_read_cam(int idx, struct rtl838x_l2_entry *e)
548 {
549 u32 r[3];
550 struct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 1);
551 int i;
552
553 rtl_table_read(q, idx);
554 for (i= 0; i < 3; i++)
555 r[i] = sw_r32(rtl_table_data(q, i));
556
557 rtl_table_release(q);
558
559 rtl930x_fill_l2_entry(r, e);
560 if (!e->valid)
561 return 0;
562
563 // return mac with concatenated vid as unique id
564 return ((u64)r[0] << 28) | ((r[1] & 0xffff0000) >> 4) | e->vid;
565 }
566
567 static void rtl930x_write_cam(int idx, struct rtl838x_l2_entry *e)
568 {
569 u32 r[3];
570 struct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 1); // Access L2 Table 1
571 int i;
572
573 rtl930x_fill_l2_row(r, e);
574
575 for (i= 0; i < 3; i++)
576 sw_w32(r[i], rtl_table_data(q, i));
577
578 rtl_table_write(q, idx);
579 rtl_table_release(q);
580 }
581
582 static u64 rtl930x_read_mcast_pmask(int idx)
583 {
584 u32 portmask;
585 // Read MC_PORTMASK (2) via register RTL9300_TBL_L2
586 struct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 2);
587
588 rtl_table_read(q, idx);
589 portmask = sw_r32(rtl_table_data(q, 0));
590 portmask >>= 3;
591 rtl_table_release(q);
592
593 pr_debug("%s: Index idx %d has portmask %08x\n", __func__, idx, portmask);
594 return portmask;
595 }
596
597 static void rtl930x_write_mcast_pmask(int idx, u64 portmask)
598 {
599 u32 pm = portmask;
600
601 // Access MC_PORTMASK (2) via register RTL9300_TBL_L2
602 struct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 2);
603
604 pr_debug("%s: Index idx %d has portmask %08x\n", __func__, idx, pm);
605 pm <<= 3;
606 sw_w32(pm, rtl_table_data(q, 0));
607 rtl_table_write(q, idx);
608 rtl_table_release(q);
609 }
610
611 u64 rtl930x_traffic_get(int source)
612 {
613 u32 v;
614 struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 6);
615
616 rtl_table_read(r, source);
617 v = sw_r32(rtl_table_data(r, 0));
618 rtl_table_release(r);
619 return v >> 3;
620 }
621
622 /*
623 * Enable traffic between a source port and a destination port matrix
624 */
625 void rtl930x_traffic_set(int source, u64 dest_matrix)
626 {
627 struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 6);
628
629 sw_w32((dest_matrix << 3), rtl_table_data(r, 0));
630 rtl_table_write(r, source);
631 rtl_table_release(r);
632 }
633
634 void rtl930x_traffic_enable(int source, int dest)
635 {
636 struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 6);
637 rtl_table_read(r, source);
638 sw_w32_mask(0, BIT(dest + 3), rtl_table_data(r, 0));
639 rtl_table_write(r, source);
640 rtl_table_release(r);
641 }
642
643 void rtl930x_traffic_disable(int source, int dest)
644 {
645 struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 6);
646 rtl_table_read(r, source);
647 sw_w32_mask(BIT(dest + 3), 0, rtl_table_data(r, 0));
648 rtl_table_write(r, source);
649 rtl_table_release(r);
650 }
651
652 void rtl9300_dump_debug(void)
653 {
654 int i;
655 u16 r = RTL930X_STAT_PRVTE_DROP_COUNTER0;
656
657 for (i = 0; i < 10; i ++) {
658 pr_info("# %d %08x %08x %08x %08x %08x %08x %08x %08x\n", i * 8,
659 sw_r32(r), sw_r32(r + 4), sw_r32(r + 8), sw_r32(r + 12),
660 sw_r32(r + 16), sw_r32(r + 20), sw_r32(r + 24), sw_r32(r + 28));
661 r += 32;
662 }
663 pr_info("# %08x %08x %08x %08x %08x\n",
664 sw_r32(r), sw_r32(r + 4), sw_r32(r + 8), sw_r32(r + 12), sw_r32(r + 16));
665 rtl930x_print_matrix();
666 pr_info("RTL930X_L2_PORT_SABLK_CTRL: %08x, RTL930X_L2_PORT_DABLK_CTRL %08x\n",
667 sw_r32(RTL930X_L2_PORT_SABLK_CTRL), sw_r32(RTL930X_L2_PORT_DABLK_CTRL)
668
669 );
670 }
671
672 irqreturn_t rtl930x_switch_irq(int irq, void *dev_id)
673 {
674 struct dsa_switch *ds = dev_id;
675 u32 ports = sw_r32(RTL930X_ISR_PORT_LINK_STS_CHG);
676 u32 link;
677 int i;
678
679 /* Clear status */
680 sw_w32(ports, RTL930X_ISR_PORT_LINK_STS_CHG);
681
682 for (i = 0; i < 28; i++) {
683 if (ports & BIT(i)) {
684 /* Read the register twice because of issues with latency at least
685 * with the external RTL8226 PHY on the XGS1210 */
686 link = sw_r32(RTL930X_MAC_LINK_STS);
687 link = sw_r32(RTL930X_MAC_LINK_STS);
688 if (link & BIT(i))
689 dsa_port_phylink_mac_change(ds, i, true);
690 else
691 dsa_port_phylink_mac_change(ds, i, false);
692 }
693 }
694
695 return IRQ_HANDLED;
696 }
697
698 int rtl930x_write_phy(u32 port, u32 page, u32 reg, u32 val)
699 {
700 u32 v;
701 int err = 0;
702
703 pr_debug("%s: port %d, page: %d, reg: %x, val: %x\n", __func__, port, page, reg, val);
704
705 if (port > 63 || page > 4095 || reg > 31)
706 return -ENOTSUPP;
707
708 val &= 0xffff;
709 mutex_lock(&smi_lock);
710
711 sw_w32(BIT(port), RTL930X_SMI_ACCESS_PHY_CTRL_0);
712 sw_w32_mask(0xffff << 16, val << 16, RTL930X_SMI_ACCESS_PHY_CTRL_2);
713 v = reg << 20 | page << 3 | 0x1f << 15 | BIT(2) | BIT(0);
714 sw_w32(v, RTL930X_SMI_ACCESS_PHY_CTRL_1);
715
716 do {
717 v = sw_r32(RTL930X_SMI_ACCESS_PHY_CTRL_1);
718 } while (v & 0x1);
719
720 if (v & 0x2)
721 err = -EIO;
722
723 mutex_unlock(&smi_lock);
724
725 return err;
726 }
727
728 int rtl930x_read_phy(u32 port, u32 page, u32 reg, u32 *val)
729 {
730 u32 v;
731 int err = 0;
732
733 if (port > 63 || page > 4095 || reg > 31)
734 return -ENOTSUPP;
735
736 mutex_lock(&smi_lock);
737
738 sw_w32_mask(0xffff << 16, port << 16, RTL930X_SMI_ACCESS_PHY_CTRL_2);
739 v = reg << 20 | page << 3 | 0x1f << 15 | 1;
740 sw_w32(v, RTL930X_SMI_ACCESS_PHY_CTRL_1);
741
742 do {
743 v = sw_r32(RTL930X_SMI_ACCESS_PHY_CTRL_1);
744 } while ( v & 0x1);
745
746 if (v & BIT(25)) {
747 pr_debug("Error reading phy %d, register %d\n", port, reg);
748 err = -EIO;
749 }
750 *val = (sw_r32(RTL930X_SMI_ACCESS_PHY_CTRL_2) & 0xffff);
751
752 pr_debug("%s: port %d, page: %d, reg: %x, val: %x\n", __func__, port, page, reg, *val);
753
754 mutex_unlock(&smi_lock);
755
756 return err;
757 }
758
759 /*
760 * Write to an mmd register of the PHY
761 */
762 int rtl930x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val)
763 {
764 int err = 0;
765 u32 v;
766
767 mutex_lock(&smi_lock);
768
769 // Set PHY to access
770 sw_w32(BIT(port), RTL930X_SMI_ACCESS_PHY_CTRL_0);
771
772 // Set data to write
773 sw_w32_mask(0xffff << 16, val << 16, RTL930X_SMI_ACCESS_PHY_CTRL_2);
774
775 // Set MMD device number and register to write to
776 sw_w32(devnum << 16 | (regnum & 0xffff), RTL930X_SMI_ACCESS_PHY_CTRL_3);
777
778 v = BIT(2) | BIT(1) | BIT(0); // WRITE | MMD-access | EXEC
779 sw_w32(v, RTL930X_SMI_ACCESS_PHY_CTRL_1);
780
781 do {
782 v = sw_r32(RTL930X_SMI_ACCESS_PHY_CTRL_1);
783 } while (v & BIT(0));
784
785 pr_debug("%s: port %d, regnum: %x, val: %x (err %d)\n", __func__, port, regnum, val, err);
786 mutex_unlock(&smi_lock);
787 return err;
788 }
789
790 /*
791 * Read an mmd register of the PHY
792 */
793 int rtl930x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val)
794 {
795 int err = 0;
796 u32 v;
797
798 mutex_lock(&smi_lock);
799
800 // Set PHY to access
801 sw_w32_mask(0xffff << 16, port << 16, RTL930X_SMI_ACCESS_PHY_CTRL_2);
802
803 // Set MMD device number and register to write to
804 sw_w32(devnum << 16 | (regnum & 0xffff), RTL930X_SMI_ACCESS_PHY_CTRL_3);
805
806 v = BIT(1) | BIT(0); // MMD-access | EXEC
807 sw_w32(v, RTL930X_SMI_ACCESS_PHY_CTRL_1);
808
809 do {
810 v = sw_r32(RTL930X_SMI_ACCESS_PHY_CTRL_1);
811 } while (v & BIT(0));
812 // There is no error-checking via BIT 25 of v, as it does not seem to be set correctly
813 *val = (sw_r32(RTL930X_SMI_ACCESS_PHY_CTRL_2) & 0xffff);
814 pr_debug("%s: port %d, regnum: %x, val: %x (err %d)\n", __func__, port, regnum, *val, err);
815
816 mutex_unlock(&smi_lock);
817
818 return err;
819 }
820
821 /*
822 * Calculate both the block 0 and the block 1 hash, and return in
823 * lower and higher word of the return value since only 12 bit of
824 * the hash are significant
825 */
826 u32 rtl930x_hash(struct rtl838x_switch_priv *priv, u64 seed)
827 {
828 u32 k0, k1, h1, h2, h;
829
830 k0 = (u32) (((seed >> 55) & 0x1f) ^ ((seed >> 44) & 0x7ff)
831 ^ ((seed >> 33) & 0x7ff) ^ ((seed >> 22) & 0x7ff)
832 ^ ((seed >> 11) & 0x7ff) ^ (seed & 0x7ff));
833
834 h1 = (seed >> 11) & 0x7ff;
835 h1 = ((h1 & 0x1f) << 6) | ((h1 >> 5) & 0x3f);
836
837 h2 = (seed >> 33) & 0x7ff;
838 h2 = ((h2 & 0x3f) << 5)| ((h2 >> 6) & 0x3f);
839
840 k1 = (u32) (((seed << 55) & 0x1f) ^ ((seed >> 44) & 0x7ff) ^ h2
841 ^ ((seed >> 22) & 0x7ff) ^ h1
842 ^ (seed & 0x7ff));
843
844 // Algorithm choice for block 0
845 if (sw_r32(RTL930X_L2_CTRL) & BIT(0))
846 h = k1;
847 else
848 h = k0;
849
850 /* Algorithm choice for block 1
851 * Since k0 and k1 are < 2048, adding 2048 will offset the hash into the second
852 * half of hash-space
853 * 2048 is in fact the hash-table size 16384 divided by 4 hashes per bucket
854 * divided by 2 to divide the hash space in 2
855 */
856 if (sw_r32(RTL930X_L2_CTRL) & BIT(1))
857 h |= (k1 + 2048) << 16;
858 else
859 h |= (k0 + 2048) << 16;
860
861 return h;
862 }
863
864 /*
865 * Enables or disables the EEE/EEEP capability of a port
866 */
867 void rtl930x_port_eee_set(struct rtl838x_switch_priv *priv, int port, bool enable)
868 {
869 u32 v;
870
871 // This works only for Ethernet ports, and on the RTL930X, ports from 26 are SFP
872 if (port >= 26)
873 return;
874
875 pr_debug("In %s: setting port %d to %d\n", __func__, port, enable);
876 v = enable ? 0x3f : 0x0;
877
878 // Set EEE/EEEP state for 100, 500, 1000MBit and 2.5, 5 and 10GBit
879 sw_w32_mask(0, v << 10, rtl930x_mac_force_mode_ctrl(port));
880
881 // Set TX/RX EEE state
882 v = enable ? 0x3 : 0x0;
883 sw_w32(v, RTL930X_EEE_CTRL(port));
884
885 priv->ports[port].eee_enabled = enable;
886 }
887
888 /*
889 * Get EEE own capabilities and negotiation result
890 */
891 int rtl930x_eee_port_ability(struct rtl838x_switch_priv *priv, struct ethtool_eee *e, int port)
892 {
893 u32 link, a;
894
895 if (port >= 26)
896 return -ENOTSUPP;
897
898 pr_info("In %s, port %d\n", __func__, port);
899 link = sw_r32(RTL930X_MAC_LINK_STS);
900 link = sw_r32(RTL930X_MAC_LINK_STS);
901 if (!(link & BIT(port)))
902 return 0;
903
904 pr_info("Setting advertised\n");
905 if (sw_r32(rtl930x_mac_force_mode_ctrl(port)) & BIT(10))
906 e->advertised |= ADVERTISED_100baseT_Full;
907
908 if (sw_r32(rtl930x_mac_force_mode_ctrl(port)) & BIT(12))
909 e->advertised |= ADVERTISED_1000baseT_Full;
910
911 if (priv->ports[port].is2G5 && sw_r32(rtl930x_mac_force_mode_ctrl(port)) & BIT(13)) {
912 pr_info("ADVERTISING 2.5G EEE\n");
913 e->advertised |= ADVERTISED_2500baseX_Full;
914 }
915
916 if (priv->ports[port].is10G && sw_r32(rtl930x_mac_force_mode_ctrl(port)) & BIT(15))
917 e->advertised |= ADVERTISED_10000baseT_Full;
918
919 a = sw_r32(RTL930X_MAC_EEE_ABLTY);
920 a = sw_r32(RTL930X_MAC_EEE_ABLTY);
921 pr_info("Link partner: %08x\n", a);
922 if (a & BIT(port)) {
923 e->lp_advertised = ADVERTISED_100baseT_Full;
924 e->lp_advertised |= ADVERTISED_1000baseT_Full;
925 if (priv->ports[port].is2G5)
926 e->lp_advertised |= ADVERTISED_2500baseX_Full;
927 if (priv->ports[port].is10G)
928 e->lp_advertised |= ADVERTISED_10000baseT_Full;
929 }
930
931 // Read 2x to clear latched state
932 a = sw_r32(RTL930X_EEEP_PORT_CTRL(port));
933 a = sw_r32(RTL930X_EEEP_PORT_CTRL(port));
934 pr_info("%s RTL930X_EEEP_PORT_CTRL: %08x\n", __func__, a);
935
936 return 0;
937 }
938
939 static void rtl930x_init_eee(struct rtl838x_switch_priv *priv, bool enable)
940 {
941 int i;
942
943 pr_info("Setting up EEE, state: %d\n", enable);
944
945 // Setup EEE on all ports
946 for (i = 0; i < priv->cpu_port; i++) {
947 if (priv->ports[i].phy)
948 rtl930x_port_eee_set(priv, i, enable);
949 }
950
951 priv->eee_enabled = enable;
952 }
953 #define HASH_PICK(val, lsb, len) ((val & (((1 << len) - 1) << lsb)) >> lsb)
954
955 static u32 rtl930x_l3_hash4(u32 ip, int algorithm, bool move_dip)
956 {
957 u32 rows[4];
958 u32 hash;
959 u32 s0, s1, pH;
960
961 memset(rows, 0, sizeof(rows));
962
963 rows[0] = HASH_PICK(ip, 27, 5);
964 rows[1] = HASH_PICK(ip, 18, 9);
965 rows[2] = HASH_PICK(ip, 9, 9);
966
967 if (!move_dip)
968 rows[3] = HASH_PICK(ip, 0, 9);
969
970 if (!algorithm) {
971 hash = rows[0] ^ rows[1] ^ rows[2] ^ rows[3];
972 } else {
973 s0 = rows[0] + rows[1] + rows[2];
974 s1 = (s0 & 0x1ff) + ((s0 & (0x1ff << 9)) >> 9);
975 pH = (s1 & 0x1ff) + ((s1 & (0x1ff << 9)) >> 9);
976 hash = pH ^ rows[3];
977 }
978 return hash;
979 }
980
981 static u32 rtl930x_l3_hash6(struct in6_addr *ip6, int algorithm, bool move_dip)
982 {
983 u32 rows[16];
984 u32 hash;
985 u32 s0, s1, pH;
986
987 rows[0] = (HASH_PICK(ip6->s6_addr[0], 6, 2) << 0);
988 rows[1] = (HASH_PICK(ip6->s6_addr[0], 0, 6) << 3) | HASH_PICK(ip6->s6_addr[1], 5, 3);
989 rows[2] = (HASH_PICK(ip6->s6_addr[1], 0, 5) << 4) | HASH_PICK(ip6->s6_addr[2], 4, 4);
990 rows[3] = (HASH_PICK(ip6->s6_addr[2], 0, 4) << 5) | HASH_PICK(ip6->s6_addr[3], 3, 5);
991 rows[4] = (HASH_PICK(ip6->s6_addr[3], 0, 3) << 6) | HASH_PICK(ip6->s6_addr[4], 2, 6);
992 rows[5] = (HASH_PICK(ip6->s6_addr[4], 0, 2) << 7) | HASH_PICK(ip6->s6_addr[5], 1, 7);
993 rows[6] = (HASH_PICK(ip6->s6_addr[5], 0, 1) << 8) | HASH_PICK(ip6->s6_addr[6], 0, 8);
994 rows[7] = (HASH_PICK(ip6->s6_addr[7], 0, 8) << 1) | HASH_PICK(ip6->s6_addr[8], 7, 1);
995 rows[8] = (HASH_PICK(ip6->s6_addr[8], 0, 7) << 2) | HASH_PICK(ip6->s6_addr[9], 6, 2);
996 rows[9] = (HASH_PICK(ip6->s6_addr[9], 0, 6) << 3) | HASH_PICK(ip6->s6_addr[10], 5, 3);
997 rows[10] = (HASH_PICK(ip6->s6_addr[10], 0, 5) << 4) | HASH_PICK(ip6->s6_addr[11], 4, 4);
998 if (!algorithm) {
999 rows[11] = (HASH_PICK(ip6->s6_addr[11], 0, 4) << 5)
1000 | (HASH_PICK(ip6->s6_addr[12], 3, 5) << 0);
1001 rows[12] = (HASH_PICK(ip6->s6_addr[12], 0, 3) << 6)
1002 | (HASH_PICK(ip6->s6_addr[13], 2, 6) << 0);
1003 rows[13] = (HASH_PICK(ip6->s6_addr[13], 0, 2) << 7)
1004 | (HASH_PICK(ip6->s6_addr[14], 1, 7) << 0);
1005 if (!move_dip) {
1006 rows[14] = (HASH_PICK(ip6->s6_addr[14], 0, 1) << 8)
1007 | (HASH_PICK(ip6->s6_addr[15], 0, 8) << 0);
1008 }
1009 hash = rows[0] ^ rows[1] ^ rows[2] ^ rows[3] ^ rows[4] ^ rows[5] ^ rows[6]
1010 ^ rows[7] ^ rows[8] ^ rows[9] ^ rows[10] ^ rows[11] ^ rows[12]
1011 ^ rows[13] ^ rows[14];
1012 } else {
1013 rows[11] = (HASH_PICK(ip6->s6_addr[11], 0, 4) << 5);
1014 rows[12] = (HASH_PICK(ip6->s6_addr[12], 3, 5) << 0);
1015 rows[13] = (HASH_PICK(ip6->s6_addr[12], 0, 3) << 6)
1016 | HASH_PICK(ip6->s6_addr[13], 2, 6);
1017 rows[14] = (HASH_PICK(ip6->s6_addr[13], 0, 2) << 7)
1018 | HASH_PICK(ip6->s6_addr[14], 1, 7);
1019 if (!move_dip) {
1020 rows[15] = (HASH_PICK(ip6->s6_addr[14], 0, 1) << 8)
1021 | (HASH_PICK(ip6->s6_addr[15], 0, 8) << 0);
1022 }
1023 s0 = rows[12] + rows[13] + rows[14];
1024 s1 = (s0 & 0x1ff) + ((s0 & (0x1ff << 9)) >> 9);
1025 pH = (s1 & 0x1ff) + ((s1 & (0x1ff << 9)) >> 9);
1026 hash = rows[0] ^ rows[1] ^ rows[2] ^ rows[3] ^ rows[4] ^ rows[5] ^ rows[6]
1027 ^ rows[7] ^ rows[8] ^ rows[9] ^ rows[10] ^ rows[11] ^ pH ^ rows[15];
1028 }
1029 return hash;
1030 }
1031
1032 /*
1033 * Read a prefix route entry from the L3_PREFIX_ROUTE_IPUC table
1034 * We currently only support IPv4 and IPv6 unicast route
1035 */
1036 static void rtl930x_route_read(int idx, struct rtl83xx_route *rt)
1037 {
1038 u32 v, ip4_m;
1039 bool host_route, default_route;
1040 struct in6_addr ip6_m;
1041
1042 // Read L3_PREFIX_ROUTE_IPUC table (2) via register RTL9300_TBL_1
1043 struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 2);
1044
1045 rtl_table_read(r, idx);
1046 // The table has a size of 11 registers
1047 rt->attr.valid = !!(sw_r32(rtl_table_data(r, 0)) & BIT(31));
1048 if (!rt->attr.valid)
1049 goto out;
1050
1051 rt->attr.type = (sw_r32(rtl_table_data(r, 0)) >> 29) & 0x3;
1052
1053 v = sw_r32(rtl_table_data(r, 10));
1054 host_route = !!(v & BIT(21));
1055 default_route = !!(v & BIT(20));
1056 rt->prefix_len = -1;
1057 pr_info("%s: host route %d, default_route %d\n", __func__, host_route, default_route);
1058
1059 switch (rt->attr.type) {
1060 case 0: // IPv4 Unicast route
1061 rt->dst_ip = sw_r32(rtl_table_data(r, 4));
1062 ip4_m = sw_r32(rtl_table_data(r, 9));
1063 pr_info("%s: Read ip4 mask: %08x\n", __func__, ip4_m);
1064 rt->prefix_len = host_route ? 32 : -1;
1065 rt->prefix_len = (rt->prefix_len < 0 && default_route) ? 0 : -1;
1066 if (rt->prefix_len < 0)
1067 rt->prefix_len = inet_mask_len(ip4_m);
1068 break;
1069 case 2: // IPv6 Unicast route
1070 ipv6_addr_set(&rt->dst_ip6,
1071 sw_r32(rtl_table_data(r, 1)), sw_r32(rtl_table_data(r, 2)),
1072 sw_r32(rtl_table_data(r, 3)), sw_r32(rtl_table_data(r, 4)));
1073 ipv6_addr_set(&ip6_m,
1074 sw_r32(rtl_table_data(r, 6)), sw_r32(rtl_table_data(r, 7)),
1075 sw_r32(rtl_table_data(r, 8)), sw_r32(rtl_table_data(r, 9)));
1076 rt->prefix_len = host_route ? 128 : 0;
1077 rt->prefix_len = (rt->prefix_len < 0 && default_route) ? 0 : -1;
1078 if (rt->prefix_len < 0)
1079 rt->prefix_len = find_last_bit((unsigned long int *)&ip6_m.s6_addr32,
1080 128);
1081 break;
1082 case 1: // IPv4 Multicast route
1083 case 3: // IPv6 Multicast route
1084 pr_warn("%s: route type not supported\n", __func__);
1085 goto out;
1086 }
1087
1088 rt->attr.hit = !!(v & BIT(22));
1089 rt->attr.action = (v >> 18) & 3;
1090 rt->nh.id = (v >> 7) & 0x7ff;
1091 rt->attr.ttl_dec = !!(v & BIT(6));
1092 rt->attr.ttl_check = !!(v & BIT(5));
1093 rt->attr.dst_null = !!(v & BIT(4));
1094 rt->attr.qos_as = !!(v & BIT(3));
1095 rt->attr.qos_prio = v & 0x7;
1096 pr_info("%s: index %d is valid: %d\n", __func__, idx, rt->attr.valid);
1097 pr_info("%s: next_hop: %d, hit: %d, action :%d, ttl_dec %d, ttl_check %d, dst_null %d\n",
1098 __func__, rt->nh.id, rt->attr.hit, rt->attr.action,
1099 rt->attr.ttl_dec, rt->attr.ttl_check, rt->attr.dst_null);
1100 pr_info("%s: GW: %pI4, prefix_len: %d\n", __func__, &rt->dst_ip, rt->prefix_len);
1101 out:
1102 rtl_table_release(r);
1103 }
1104
1105 static void rtl930x_net6_mask(int prefix_len, struct in6_addr *ip6_m)
1106 {
1107 int o, b;
1108 // Define network mask
1109 o = prefix_len >> 3;
1110 b = prefix_len & 0x7;
1111 memset(ip6_m->s6_addr, 0xff, o);
1112 ip6_m->s6_addr[o] |= b ? 0xff00 >> b : 0x00;
1113 }
1114
1115 /*
1116 * Read a host route entry from the table using its index
1117 * We currently only support IPv4 and IPv6 unicast route
1118 */
1119 static void rtl930x_host_route_read(int idx, struct rtl83xx_route *rt)
1120 {
1121 u32 v;
1122 // Read L3_HOST_ROUTE_IPUC table (1) via register RTL9300_TBL_1
1123 struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 1);
1124
1125 idx = ((idx / 6) * 8) + (idx % 6);
1126
1127 pr_debug("In %s, physical index %d\n", __func__, idx);
1128 rtl_table_read(r, idx);
1129 // The table has a size of 5 (for UC, 11 for MC) registers
1130 v = sw_r32(rtl_table_data(r, 0));
1131 rt->attr.valid = !!(v & BIT(31));
1132 if (!rt->attr.valid)
1133 goto out;
1134 rt->attr.type = (v >> 29) & 0x3;
1135 switch (rt->attr.type) {
1136 case 0: // IPv4 Unicast route
1137 rt->dst_ip = sw_r32(rtl_table_data(r, 4));
1138 break;
1139 case 2: // IPv6 Unicast route
1140 ipv6_addr_set(&rt->dst_ip6,
1141 sw_r32(rtl_table_data(r, 3)), sw_r32(rtl_table_data(r, 2)),
1142 sw_r32(rtl_table_data(r, 1)), sw_r32(rtl_table_data(r, 0)));
1143 break;
1144 case 1: // IPv4 Multicast route
1145 case 3: // IPv6 Multicast route
1146 pr_warn("%s: route type not supported\n", __func__);
1147 goto out;
1148 }
1149
1150 rt->attr.hit = !!(v & BIT(20));
1151 rt->attr.dst_null = !!(v & BIT(19));
1152 rt->attr.action = (v >> 17) & 3;
1153 rt->nh.id = (v >> 6) & 0x7ff;
1154 rt->attr.ttl_dec = !!(v & BIT(5));
1155 rt->attr.ttl_check = !!(v & BIT(4));
1156 rt->attr.qos_as = !!(v & BIT(3));
1157 rt->attr.qos_prio = v & 0x7;
1158 pr_debug("%s: index %d is valid: %d\n", __func__, idx, rt->attr.valid);
1159 pr_debug("%s: next_hop: %d, hit: %d, action :%d, ttl_dec %d, ttl_check %d, dst_null %d\n",
1160 __func__, rt->nh.id, rt->attr.hit, rt->attr.action, rt->attr.ttl_dec, rt->attr.ttl_check,
1161 rt->attr.dst_null);
1162 pr_debug("%s: Destination: %pI4\n", __func__, &rt->dst_ip);
1163
1164 out:
1165 rtl_table_release(r);
1166 }
1167
1168 /*
1169 * Write a host route entry from the table using its index
1170 * We currently only support IPv4 and IPv6 unicast route
1171 */
1172 static void rtl930x_host_route_write(int idx, struct rtl83xx_route *rt)
1173 {
1174 u32 v;
1175 // Access L3_HOST_ROUTE_IPUC table (1) via register RTL9300_TBL_1
1176 struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 1);
1177 // The table has a size of 5 (for UC, 11 for MC) registers
1178
1179 idx = ((idx / 6) * 8) + (idx % 6);
1180
1181 pr_debug("%s: index %d is valid: %d\n", __func__, idx, rt->attr.valid);
1182 pr_debug("%s: next_hop: %d, hit: %d, action :%d, ttl_dec %d, ttl_check %d, dst_null %d\n",
1183 __func__, rt->nh.id, rt->attr.hit, rt->attr.action, rt->attr.ttl_dec, rt->attr.ttl_check,
1184 rt->attr.dst_null);
1185 pr_debug("%s: GW: %pI4, prefix_len: %d\n", __func__, &rt->dst_ip, rt->prefix_len);
1186
1187 v = BIT(31); // Entry is valid
1188 v |= (rt->attr.type & 0x3) << 29;
1189 v |= rt->attr.hit ? BIT(20) : 0;
1190 v |= rt->attr.dst_null ? BIT(19) : 0;
1191 v |= (rt->attr.action & 0x3) << 17;
1192 v |= (rt->nh.id & 0x7ff) << 6;
1193 v |= rt->attr.ttl_dec ? BIT(5) : 0;
1194 v |= rt->attr.ttl_check ? BIT(4) : 0;
1195 v |= rt->attr.qos_as ? BIT(3) : 0;
1196 v |= rt->attr.qos_prio & 0x7;
1197
1198 sw_w32(v, rtl_table_data(r, 0));
1199 switch (rt->attr.type) {
1200 case 0: // IPv4 Unicast route
1201 sw_w32(0, rtl_table_data(r, 1));
1202 sw_w32(0, rtl_table_data(r, 2));
1203 sw_w32(0, rtl_table_data(r, 3));
1204 sw_w32(rt->dst_ip, rtl_table_data(r, 4));
1205 break;
1206 case 2: // IPv6 Unicast route
1207 sw_w32(rt->dst_ip6.s6_addr32[0], rtl_table_data(r, 1));
1208 sw_w32(rt->dst_ip6.s6_addr32[1], rtl_table_data(r, 2));
1209 sw_w32(rt->dst_ip6.s6_addr32[2], rtl_table_data(r, 3));
1210 sw_w32(rt->dst_ip6.s6_addr32[3], rtl_table_data(r, 4));
1211 break;
1212 case 1: // IPv4 Multicast route
1213 case 3: // IPv6 Multicast route
1214 pr_warn("%s: route type not supported\n", __func__);
1215 goto out;
1216 }
1217
1218 rtl_table_write(r, idx);
1219
1220 out:
1221 rtl_table_release(r);
1222 }
1223
1224 /*
1225 * Look up the index of a prefix route in the routing table CAM for unicast IPv4/6 routes
1226 * using hardware offload.
1227 */
1228 static int rtl930x_route_lookup_hw(struct rtl83xx_route *rt)
1229 {
1230 u32 ip4_m, v;
1231 struct in6_addr ip6_m;
1232 int i;
1233
1234 if (rt->attr.type == 1 || rt->attr.type == 3) // Hardware only supports UC routes
1235 return -1;
1236
1237 sw_w32_mask(0x3 << 19, rt->attr.type, RTL930X_L3_HW_LU_KEY_CTRL);
1238 if (rt->attr.type) { // IPv6
1239 rtl930x_net6_mask(rt->prefix_len, &ip6_m);
1240 for (i = 0; i < 4; i++)
1241 sw_w32(rt->dst_ip6.s6_addr32[0] & ip6_m.s6_addr32[0],
1242 RTL930X_L3_HW_LU_KEY_IP_CTRL + (i << 2));
1243 } else { // IPv4
1244 ip4_m = inet_make_mask(rt->prefix_len);
1245 sw_w32(0, RTL930X_L3_HW_LU_KEY_IP_CTRL);
1246 sw_w32(0, RTL930X_L3_HW_LU_KEY_IP_CTRL + 4);
1247 sw_w32(0, RTL930X_L3_HW_LU_KEY_IP_CTRL + 8);
1248 v = rt->dst_ip & ip4_m;
1249 pr_info("%s: searching for %pI4\n", __func__, &v);
1250 sw_w32(v, RTL930X_L3_HW_LU_KEY_IP_CTRL + 12);
1251 }
1252
1253 // Execute CAM lookup in SoC
1254 sw_w32(BIT(15), RTL930X_L3_HW_LU_CTRL);
1255
1256 // Wait until execute bit clears and result is ready
1257 do {
1258 v = sw_r32(RTL930X_L3_HW_LU_CTRL);
1259 } while (v & BIT(15));
1260
1261 pr_info("%s: found: %d, index: %d\n", __func__, !!(v & BIT(14)), v & 0x1ff);
1262
1263 // Test if search successful (BIT 14 set)
1264 if (v & BIT(14))
1265 return v & 0x1ff;
1266
1267 return -1;
1268 }
1269
1270 static int rtl930x_find_l3_slot(struct rtl83xx_route *rt, bool must_exist)
1271 {
1272 int t, s, slot_width, algorithm, addr, idx;
1273 u32 hash;
1274 struct rtl83xx_route route_entry;
1275
1276 // IPv6 entries take up 3 slots
1277 slot_width = (rt->attr.type == 0) || (rt->attr.type == 2) ? 1 : 3;
1278
1279 for (t = 0; t < 2; t++) {
1280 algorithm = (sw_r32(RTL930X_L3_HOST_TBL_CTRL) >> (2 + t)) & 0x1;
1281 hash = rtl930x_l3_hash4(rt->dst_ip, algorithm, false);
1282
1283 pr_debug("%s: table %d, algorithm %d, hash %04x\n", __func__, t, algorithm, hash);
1284
1285 for (s = 0; s < 6; s += slot_width) {
1286 addr = (t << 12) | ((hash & 0x1ff) << 3) | s;
1287 pr_debug("%s physical address %d\n", __func__, addr);
1288 idx = ((addr / 8) * 6) + (addr % 8);
1289 pr_debug("%s logical address %d\n", __func__, idx);
1290
1291 rtl930x_host_route_read(idx, &route_entry);
1292 pr_debug("%s route valid %d, route dest: %pI4, hit %d\n", __func__,
1293 rt->attr.valid, &rt->dst_ip, rt->attr.hit);
1294 if (!must_exist && rt->attr.valid)
1295 return idx;
1296 if (must_exist && route_entry.dst_ip == rt->dst_ip)
1297 return idx;
1298 }
1299 }
1300
1301 return -1;
1302 }
1303
1304 /*
1305 * Write a prefix route into the routing table CAM at position idx
1306 * Currently only IPv4 and IPv6 unicast routes are supported
1307 */
1308 static void rtl930x_route_write(int idx, struct rtl83xx_route *rt)
1309 {
1310 u32 v, ip4_m;
1311 struct in6_addr ip6_m;
1312 // Access L3_PREFIX_ROUTE_IPUC table (2) via register RTL9300_TBL_1
1313 // The table has a size of 11 registers (20 for MC)
1314 struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 2);
1315
1316 pr_debug("%s: index %d is valid: %d\n", __func__, idx, rt->attr.valid);
1317 pr_debug("%s: nexthop: %d, hit: %d, action :%d, ttl_dec %d, ttl_check %d, dst_null %d\n",
1318 __func__, rt->nh.id, rt->attr.hit, rt->attr.action,
1319 rt->attr.ttl_dec, rt->attr.ttl_check, rt->attr.dst_null);
1320 pr_debug("%s: GW: %pI4, prefix_len: %d\n", __func__, &rt->dst_ip, rt->prefix_len);
1321
1322 v = rt->attr.valid ? BIT(31) : 0;
1323 v |= (rt->attr.type & 0x3) << 29;
1324 sw_w32(v, rtl_table_data(r, 0));
1325
1326 v = rt->attr.hit ? BIT(22) : 0;
1327 v |= (rt->attr.action & 0x3) << 18;
1328 v |= (rt->nh.id & 0x7ff) << 7;
1329 v |= rt->attr.ttl_dec ? BIT(6) : 0;
1330 v |= rt->attr.ttl_check ? BIT(5) : 0;
1331 v |= rt->attr.dst_null ? BIT(6) : 0;
1332 v |= rt->attr.qos_as ? BIT(6) : 0;
1333 v |= rt->attr.qos_prio & 0x7;
1334 v |= rt->prefix_len == 0 ? BIT(20) : 0; // set default route bit
1335
1336 // set bit mask for entry type always to 0x3
1337 sw_w32(0x3 << 29, rtl_table_data(r, 5));
1338
1339 switch (rt->attr.type) {
1340 case 0: // IPv4 Unicast route
1341 sw_w32(0, rtl_table_data(r, 1));
1342 sw_w32(0, rtl_table_data(r, 2));
1343 sw_w32(0, rtl_table_data(r, 3));
1344 sw_w32(rt->dst_ip, rtl_table_data(r, 4));
1345
1346 v |= rt->prefix_len == 32 ? BIT(21) : 0; // set host-route bit
1347 ip4_m = inet_make_mask(rt->prefix_len);
1348 sw_w32(0, rtl_table_data(r, 6));
1349 sw_w32(0, rtl_table_data(r, 7));
1350 sw_w32(0, rtl_table_data(r, 8));
1351 sw_w32(ip4_m, rtl_table_data(r, 9));
1352 break;
1353 case 2: // IPv6 Unicast route
1354 sw_w32(rt->dst_ip6.s6_addr32[0], rtl_table_data(r, 1));
1355 sw_w32(rt->dst_ip6.s6_addr32[1], rtl_table_data(r, 2));
1356 sw_w32(rt->dst_ip6.s6_addr32[2], rtl_table_data(r, 3));
1357 sw_w32(rt->dst_ip6.s6_addr32[3], rtl_table_data(r, 4));
1358
1359 v |= rt->prefix_len == 128 ? BIT(21) : 0; // set host-route bit
1360
1361 rtl930x_net6_mask(rt->prefix_len, &ip6_m);
1362
1363 sw_w32(ip6_m.s6_addr32[0], rtl_table_data(r, 6));
1364 sw_w32(ip6_m.s6_addr32[1], rtl_table_data(r, 7));
1365 sw_w32(ip6_m.s6_addr32[2], rtl_table_data(r, 8));
1366 sw_w32(ip6_m.s6_addr32[3], rtl_table_data(r, 9));
1367 break;
1368 case 1: // IPv4 Multicast route
1369 case 3: // IPv6 Multicast route
1370 pr_warn("%s: route type not supported\n", __func__);
1371 rtl_table_release(r);
1372 return;
1373 }
1374 sw_w32(v, rtl_table_data(r, 10));
1375
1376 pr_debug("%s: %08x %08x %08x %08x %08x %08x %08x %08x %08x %08x %08x\n", __func__,
1377 sw_r32(rtl_table_data(r, 0)), sw_r32(rtl_table_data(r, 1)), sw_r32(rtl_table_data(r, 2)),
1378 sw_r32(rtl_table_data(r, 3)), sw_r32(rtl_table_data(r, 4)), sw_r32(rtl_table_data(r, 5)),
1379 sw_r32(rtl_table_data(r, 6)), sw_r32(rtl_table_data(r, 7)), sw_r32(rtl_table_data(r, 8)),
1380 sw_r32(rtl_table_data(r, 9)), sw_r32(rtl_table_data(r, 10)));
1381
1382 rtl_table_write(r, idx);
1383 rtl_table_release(r);
1384 }
1385
1386
1387 /*
1388 * Get the destination MAC and L3 egress interface ID of a nexthop entry from
1389 * the SoC's L3_NEXTHOP table
1390 */
1391 static void rtl930x_get_l3_nexthop(int idx, u16 *dmac_id, u16 *interface)
1392 {
1393 u32 v;
1394 // Read L3_NEXTHOP table (3) via register RTL9300_TBL_1
1395 struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 3);
1396
1397 rtl_table_read(r, idx);
1398 // The table has a size of 1 register
1399 v = sw_r32(rtl_table_data(r, 0));
1400 rtl_table_release(r);
1401
1402 *dmac_id = (v >> 7) & 0x7fff;
1403 *interface = v & 0x7f;
1404 }
1405
1406 static int rtl930x_l3_mtu_del(struct rtl838x_switch_priv *priv, int mtu)
1407 {
1408 int i;
1409
1410 for (i = 0; i < MAX_INTF_MTUS; i++) {
1411 if (mtu == priv->intf_mtus[i])
1412 break;
1413 }
1414 if (i >= MAX_INTF_MTUS || !priv->intf_mtu_count[i]) {
1415 pr_err("%s: No MTU slot found for MTU: %d\n", __func__, mtu);
1416 return -EINVAL;
1417 }
1418
1419 priv->intf_mtu_count[i]--;
1420 }
1421
1422 static int rtl930x_l3_mtu_add(struct rtl838x_switch_priv *priv, int mtu)
1423 {
1424 int i, free_mtu;
1425 int mtu_id;
1426
1427 // Try to find an existing mtu-value or a free slot
1428 free_mtu = MAX_INTF_MTUS;
1429 for (i = 0; i < MAX_INTF_MTUS && priv->intf_mtus[i] != mtu; i++) {
1430 if ((!priv->intf_mtu_count[i]) && (free_mtu == MAX_INTF_MTUS))
1431 free_mtu = i;
1432 }
1433 i = (i < MAX_INTF_MTUS) ? i : free_mtu;
1434 if (i < MAX_INTF_MTUS) {
1435 mtu_id = i;
1436 } else {
1437 pr_err("%s: No free MTU slot available!\n", __func__);
1438 return -EINVAL;
1439 }
1440
1441 priv->intf_mtus[i] = mtu;
1442 pr_info("Writing MTU %d to slot %d\n", priv->intf_mtus[i], i);
1443 // Set MTU-value of the slot TODO: distinguish between IPv4/IPv6 routes / slots
1444 sw_w32_mask(0xffff << ((i % 2) * 16), priv->intf_mtus[i] << ((i % 2) * 16),
1445 RTL930X_L3_IP_MTU_CTRL(i));
1446 sw_w32_mask(0xffff << ((i % 2) * 16), priv->intf_mtus[i] << ((i % 2) * 16),
1447 RTL930X_L3_IP6_MTU_CTRL(i));
1448
1449 priv->intf_mtu_count[i]++;
1450
1451 return mtu_id;
1452 }
1453
1454 /*
1455 * Creates an interface for a route by setting up the HW tables in the SoC
1456 */
1457 static int rtl930x_l3_intf_add(struct rtl838x_switch_priv *priv, struct rtl838x_l3_intf *intf)
1458 {
1459 int i, intf_id, mtu_id;
1460 // number of MTU-values < 16384
1461
1462 // Use the same IPv6 mtu as the ip4 mtu for this route if unset
1463 intf->ip6_mtu = intf->ip6_mtu ? intf->ip6_mtu : intf->ip4_mtu;
1464
1465 mtu_id = rtl930x_l3_mtu_add(priv, intf->ip4_mtu);
1466 pr_info("%s: added mtu %d with mtu-id %d\n", __func__, intf->ip4_mtu, mtu_id);
1467 if (mtu_id < 0)
1468 return -ENOSPC;
1469 intf->ip4_mtu_id = mtu_id;
1470 intf->ip6_mtu_id = mtu_id;
1471
1472 for (i = 0; i < MAX_INTERFACES; i++) {
1473 if (!priv->interfaces[i])
1474 break;
1475 }
1476 if (i >= MAX_INTERFACES) {
1477 pr_err("%s: cannot find free interface entry\n", __func__);
1478 return -EINVAL;
1479 }
1480 intf_id = i;
1481 priv->interfaces[i] = kzalloc(sizeof(struct rtl838x_l3_intf), GFP_KERNEL);
1482 if (!priv->interfaces[i]) {
1483 pr_err("%s: no memory to allocate new interface\n", __func__);
1484 return -ENOMEM;
1485 }
1486 }
1487
1488 /*
1489 * Set the destination MAC and L3 egress interface ID for a nexthop entry in the SoC's
1490 * L3_NEXTHOP table. The nexthop entry is identified by idx.
1491 * dmac_id is the reference to the L2 entry in the L2 forwarding table, special values are
1492 * 0x7ffe: TRAP2CPU
1493 * 0x7ffd: TRAP2MASTERCPU
1494 * 0x7fff: DMAC_ID_DROP
1495 */
1496 static void rtl930x_set_l3_nexthop(int idx, u16 dmac_id, u16 interface)
1497 {
1498 // Access L3_NEXTHOP table (3) via register RTL9300_TBL_1
1499 struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 3);
1500
1501 pr_info("%s: Writing to L3_NEXTHOP table, index %d, dmac_id %d, interface %d\n",
1502 __func__, idx, dmac_id, interface);
1503 sw_w32(((dmac_id & 0x7fff) << 7) | (interface & 0x7f), rtl_table_data(r, 0));
1504
1505 pr_info("%s: %08x\n", __func__, sw_r32(rtl_table_data(r,0)));
1506 rtl_table_write(r, idx);
1507 rtl_table_release(r);
1508 }
1509
1510 static void rtl930x_pie_lookup_enable(struct rtl838x_switch_priv *priv, int index)
1511 {
1512 int block = index / PIE_BLOCK_SIZE;
1513
1514 sw_w32_mask(0, BIT(block), RTL930X_PIE_BLK_LOOKUP_CTRL);
1515 }
1516
1517 /*
1518 * Reads the intermediate representation of the templated match-fields of the
1519 * PIE rule in the pie_rule structure and fills in the raw data fields in the
1520 * raw register space r[].
1521 * The register space configuration size is identical for the RTL8380/90 and RTL9300,
1522 * however the RTL9310 has 2 more registers / fields and the physical field-ids are different
1523 * on all SoCs
1524 * On the RTL9300 the mask fields are not word-aligend!
1525 */
1526 static void rtl930x_write_pie_templated(u32 r[], struct pie_rule *pr, enum template_field_id t[])
1527 {
1528 int i;
1529 enum template_field_id field_type;
1530 u16 data, data_m;
1531
1532 for (i = 0; i < N_FIXED_FIELDS; i++) {
1533 field_type = t[i];
1534 data = data_m = 0;
1535
1536 switch (field_type) {
1537 case TEMPLATE_FIELD_SPM0:
1538 data = pr->spm;
1539 data_m = pr->spm_m;
1540 break;
1541 case TEMPLATE_FIELD_SPM1:
1542 data = pr->spm >> 16;
1543 data_m = pr->spm_m >> 16;
1544 break;
1545 case TEMPLATE_FIELD_OTAG:
1546 data = pr->otag;
1547 data_m = pr->otag_m;
1548 break;
1549 case TEMPLATE_FIELD_SMAC0:
1550 data = pr->smac[4];
1551 data = (data << 8) | pr->smac[5];
1552 data_m = pr->smac_m[4];
1553 data_m = (data_m << 8) | pr->smac_m[5];
1554 break;
1555 case TEMPLATE_FIELD_SMAC1:
1556 data = pr->smac[2];
1557 data = (data << 8) | pr->smac[3];
1558 data_m = pr->smac_m[2];
1559 data_m = (data_m << 8) | pr->smac_m[3];
1560 break;
1561 case TEMPLATE_FIELD_SMAC2:
1562 data = pr->smac[0];
1563 data = (data << 8) | pr->smac[1];
1564 data_m = pr->smac_m[0];
1565 data_m = (data_m << 8) | pr->smac_m[1];
1566 break;
1567 case TEMPLATE_FIELD_DMAC0:
1568 data = pr->dmac[4];
1569 data = (data << 8) | pr->dmac[5];
1570 data_m = pr->dmac_m[4];
1571 data_m = (data_m << 8) | pr->dmac_m[5];
1572 break;
1573 case TEMPLATE_FIELD_DMAC1:
1574 data = pr->dmac[2];
1575 data = (data << 8) | pr->dmac[3];
1576 data_m = pr->dmac_m[2];
1577 data_m = (data_m << 8) | pr->dmac_m[3];
1578 break;
1579 case TEMPLATE_FIELD_DMAC2:
1580 data = pr->dmac[0];
1581 data = (data << 8) | pr->dmac[1];
1582 data_m = pr->dmac_m[0];
1583 data_m = (data_m << 8) | pr->dmac_m[1];
1584 break;
1585 case TEMPLATE_FIELD_ETHERTYPE:
1586 data = pr->ethertype;
1587 data_m = pr->ethertype_m;
1588 break;
1589 case TEMPLATE_FIELD_ITAG:
1590 data = pr->itag;
1591 data_m = pr->itag_m;
1592 break;
1593 case TEMPLATE_FIELD_SIP0:
1594 if (pr->is_ipv6) {
1595 data = pr->sip6.s6_addr16[7];
1596 data_m = pr->sip6_m.s6_addr16[7];
1597 } else {
1598 data = pr->sip;
1599 data_m = pr->sip_m;
1600 }
1601 break;
1602 case TEMPLATE_FIELD_SIP1:
1603 if (pr->is_ipv6) {
1604 data = pr->sip6.s6_addr16[6];
1605 data_m = pr->sip6_m.s6_addr16[6];
1606 } else {
1607 data = pr->sip >> 16;
1608 data_m = pr->sip_m >> 16;
1609 }
1610 break;
1611
1612 case TEMPLATE_FIELD_SIP2:
1613 case TEMPLATE_FIELD_SIP3:
1614 case TEMPLATE_FIELD_SIP4:
1615 case TEMPLATE_FIELD_SIP5:
1616 case TEMPLATE_FIELD_SIP6:
1617 case TEMPLATE_FIELD_SIP7:
1618 data = pr->sip6.s6_addr16[5 - (field_type - TEMPLATE_FIELD_SIP2)];
1619 data_m = pr->sip6_m.s6_addr16[5 - (field_type - TEMPLATE_FIELD_SIP2)];
1620 break;
1621
1622 case TEMPLATE_FIELD_DIP0:
1623 if (pr->is_ipv6) {
1624 data = pr->dip6.s6_addr16[7];
1625 data_m = pr->dip6_m.s6_addr16[7];
1626 } else {
1627 data = pr->dip;
1628 data_m = pr->dip_m;
1629 }
1630 break;
1631
1632 case TEMPLATE_FIELD_DIP1:
1633 if (pr->is_ipv6) {
1634 data = pr->dip6.s6_addr16[6];
1635 data_m = pr->dip6_m.s6_addr16[6];
1636 } else {
1637 data = pr->dip >> 16;
1638 data_m = pr->dip_m >> 16;
1639 }
1640 break;
1641
1642 case TEMPLATE_FIELD_DIP2:
1643 case TEMPLATE_FIELD_DIP3:
1644 case TEMPLATE_FIELD_DIP4:
1645 case TEMPLATE_FIELD_DIP5:
1646 case TEMPLATE_FIELD_DIP6:
1647 case TEMPLATE_FIELD_DIP7:
1648 data = pr->dip6.s6_addr16[5 - (field_type - TEMPLATE_FIELD_DIP2)];
1649 data_m = pr->dip6_m.s6_addr16[5 - (field_type - TEMPLATE_FIELD_DIP2)];
1650 break;
1651
1652 case TEMPLATE_FIELD_IP_TOS_PROTO:
1653 data = pr->tos_proto;
1654 data_m = pr->tos_proto_m;
1655 break;
1656 case TEMPLATE_FIELD_L4_SPORT:
1657 data = pr->sport;
1658 data_m = pr->sport_m;
1659 break;
1660 case TEMPLATE_FIELD_L4_DPORT:
1661 data = pr->dport;
1662 data_m = pr->dport_m;
1663 break;
1664 case TEMPLATE_FIELD_DSAP_SSAP:
1665 data = pr->dsap_ssap;
1666 data_m = pr->dsap_ssap_m;
1667 break;
1668 case TEMPLATE_FIELD_TCP_INFO:
1669 data = pr->tcp_info;
1670 data_m = pr->tcp_info_m;
1671 break;
1672 case TEMPLATE_FIELD_RANGE_CHK:
1673 pr_warn("Warning: TEMPLATE_FIELD_RANGE_CHK: not configured\n");
1674 break;
1675 default:
1676 pr_info("%s: unknown field %d\n", __func__, field_type);
1677 }
1678
1679 // On the RTL9300, the mask fields are not word aligned!
1680 if (!(i % 2)) {
1681 r[5 - i / 2] = data;
1682 r[12 - i / 2] |= ((u32)data_m << 8);
1683 } else {
1684 r[5 - i / 2] |= ((u32)data) << 16;
1685 r[12 - i / 2] |= ((u32)data_m) << 24;
1686 r[11 - i / 2] |= ((u32)data_m) >> 8;
1687 }
1688 }
1689 }
1690
1691 static void rtl930x_read_pie_fixed_fields(u32 r[], struct pie_rule *pr)
1692 {
1693 pr->stacking_port = r[6] & BIT(31);
1694 pr->spn = (r[6] >> 24) & 0x7f;
1695 pr->mgnt_vlan = r[6] & BIT(23);
1696 if (pr->phase == PHASE_IACL)
1697 pr->dmac_hit_sw = r[6] & BIT(22);
1698 else
1699 pr->content_too_deep = r[6] & BIT(22);
1700 pr->not_first_frag = r[6] & BIT(21);
1701 pr->frame_type_l4 = (r[6] >> 18) & 7;
1702 pr->frame_type = (r[6] >> 16) & 3;
1703 pr->otag_fmt = (r[6] >> 15) & 1;
1704 pr->itag_fmt = (r[6] >> 14) & 1;
1705 pr->otag_exist = (r[6] >> 13) & 1;
1706 pr->itag_exist = (r[6] >> 12) & 1;
1707 pr->frame_type_l2 = (r[6] >> 10) & 3;
1708 pr->igr_normal_port = (r[6] >> 9) & 1;
1709 pr->tid = (r[6] >> 8) & 1;
1710
1711 pr->stacking_port_m = r[12] & BIT(7);
1712 pr->spn_m = r[12] & 0x7f;
1713 pr->mgnt_vlan_m = r[13] & BIT(31);
1714 if (pr->phase == PHASE_IACL)
1715 pr->dmac_hit_sw_m = r[13] & BIT(30);
1716 else
1717 pr->content_too_deep_m = r[13] & BIT(30);
1718 pr->not_first_frag_m = r[13] & BIT(29);
1719 pr->frame_type_l4_m = (r[13] >> 26) & 7;
1720 pr->frame_type_m = (r[13] >> 24) & 3;
1721 pr->otag_fmt_m = r[13] & BIT(23);
1722 pr->itag_fmt_m = r[13] & BIT(22);
1723 pr->otag_exist_m = r[13] & BIT(21);
1724 pr->itag_exist_m = r[13] & BIT (20);
1725 pr->frame_type_l2_m = (r[13] >> 18) & 3;
1726 pr->igr_normal_port_m = r[13] & BIT(17);
1727 pr->tid_m = (r[13] >> 16) & 1;
1728
1729 pr->valid = r[13] & BIT(15);
1730 pr->cond_not = r[13] & BIT(14);
1731 pr->cond_and1 = r[13] & BIT(13);
1732 pr->cond_and2 = r[13] & BIT(12);
1733 }
1734
1735 static void rtl930x_write_pie_fixed_fields(u32 r[], struct pie_rule *pr)
1736 {
1737 r[6] = pr->stacking_port ? BIT(31) : 0;
1738 r[6] |= ((u32) (pr->spn & 0x7f)) << 24;
1739 r[6] |= pr->mgnt_vlan ? BIT(23) : 0;
1740 if (pr->phase == PHASE_IACL)
1741 r[6] |= pr->dmac_hit_sw ? BIT(22) : 0;
1742 else
1743 r[6] |= pr->content_too_deep ? BIT(22) : 0;
1744 r[6] |= pr->not_first_frag ? BIT(21) : 0;
1745 r[6] |= ((u32) (pr->frame_type_l4 & 0x7)) << 18;
1746 r[6] |= ((u32) (pr->frame_type & 0x3)) << 16;
1747 r[6] |= pr->otag_fmt ? BIT(15) : 0;
1748 r[6] |= pr->itag_fmt ? BIT(14) : 0;
1749 r[6] |= pr->otag_exist ? BIT(13) : 0;
1750 r[6] |= pr->itag_exist ? BIT(12) : 0;
1751 r[6] |= ((u32) (pr->frame_type_l2 & 0x3)) << 10;
1752 r[6] |= pr->igr_normal_port ? BIT(9) : 0;
1753 r[6] |= ((u32) (pr->tid & 0x1)) << 8;
1754
1755 r[12] |= pr->stacking_port_m ? BIT(7) : 0;
1756 r[12] |= (u32) (pr->spn_m & 0x7f);
1757 r[13] |= pr->mgnt_vlan_m ? BIT(31) : 0;
1758 if (pr->phase == PHASE_IACL)
1759 r[13] |= pr->dmac_hit_sw_m ? BIT(30) : 0;
1760 else
1761 r[13] |= pr->content_too_deep_m ? BIT(30) : 0;
1762 r[13] |= pr->not_first_frag_m ? BIT(29) : 0;
1763 r[13] |= ((u32) (pr->frame_type_l4_m & 0x7)) << 26;
1764 r[13] |= ((u32) (pr->frame_type_m & 0x3)) << 24;
1765 r[13] |= pr->otag_fmt_m ? BIT(23) : 0;
1766 r[13] |= pr->itag_fmt_m ? BIT(22) : 0;
1767 r[13] |= pr->otag_exist_m ? BIT(21) : 0;
1768 r[13] |= pr->itag_exist_m ? BIT(20) : 0;
1769 r[13] |= ((u32) (pr->frame_type_l2_m & 0x3)) << 18;
1770 r[13] |= pr->igr_normal_port_m ? BIT(17) : 0;
1771 r[13] |= ((u32) (pr->tid_m & 0x1)) << 16;
1772
1773 r[13] |= pr->valid ? BIT(15) : 0;
1774 r[13] |= pr->cond_not ? BIT(14) : 0;
1775 r[13] |= pr->cond_and1 ? BIT(13) : 0;
1776 r[13] |= pr->cond_and2 ? BIT(12) : 0;
1777 }
1778
1779 static void rtl930x_write_pie_action(u32 r[], struct pie_rule *pr)
1780 {
1781 // Either drop or forward
1782 if (pr->drop) {
1783 r[14] |= BIT(24) | BIT(25) | BIT(26); // Do Green, Yellow and Red drops
1784 // Actually DROP, not PERMIT in Green / Yellow / Red
1785 r[14] |= BIT(23) | BIT(22) | BIT(20);
1786 } else {
1787 r[14] |= pr->fwd_sel ? BIT(27) : 0;
1788 r[14] |= pr->fwd_act << 18;
1789 r[14] |= BIT(14); // We overwrite any drop
1790 }
1791 if (pr->phase == PHASE_VACL)
1792 r[14] |= pr->fwd_sa_lrn ? BIT(15) : 0;
1793 r[13] |= pr->bypass_sel ? BIT(5) : 0;
1794 r[13] |= pr->nopri_sel ? BIT(4) : 0;
1795 r[13] |= pr->tagst_sel ? BIT(3) : 0;
1796 r[13] |= pr->ovid_sel ? BIT(1) : 0;
1797 r[14] |= pr->ivid_sel ? BIT(31) : 0;
1798 r[14] |= pr->meter_sel ? BIT(30) : 0;
1799 r[14] |= pr->mir_sel ? BIT(29) : 0;
1800 r[14] |= pr->log_sel ? BIT(28) : 0;
1801
1802 r[14] |= ((u32)(pr->fwd_data & 0x3fff)) << 3;
1803 r[15] |= pr->log_octets ? BIT(31) : 0;
1804 r[15] |= (u32)(pr->meter_data) << 23;
1805
1806 r[15] |= ((u32)(pr->ivid_act) << 21) & 0x3;
1807 r[15] |= ((u32)(pr->ivid_data) << 9) & 0xfff;
1808 r[16] |= ((u32)(pr->ovid_act) << 30) & 0x3;
1809 r[16] |= ((u32)(pr->ovid_data) & 0xfff) << 16;
1810 r[16] |= (pr->mir_data & 0x3) << 6;
1811 r[17] |= ((u32)(pr->tagst_data) & 0xf) << 28;
1812 r[17] |= ((u32)(pr->nopri_data) & 0x7) << 25;
1813 r[17] |= pr->bypass_ibc_sc ? BIT(16) : 0;
1814 }
1815
1816 void rtl930x_pie_rule_dump_raw(u32 r[])
1817 {
1818 pr_info("Raw IACL table entry:\n");
1819 pr_info("r 0 - 7: %08x %08x %08x %08x %08x %08x %08x %08x\n",
1820 r[0], r[1], r[2], r[3], r[4], r[5], r[6], r[7]);
1821 pr_info("r 8 - 15: %08x %08x %08x %08x %08x %08x %08x %08x\n",
1822 r[8], r[9], r[10], r[11], r[12], r[13], r[14], r[15]);
1823 pr_info("r 16 - 18: %08x %08x %08x\n", r[16], r[17], r[18]);
1824 pr_info("Match : %08x %08x %08x %08x %08x %08x\n", r[0], r[1], r[2], r[3], r[4], r[5]);
1825 pr_info("Fixed : %06x\n", r[6] >> 8);
1826 pr_info("Match M: %08x %08x %08x %08x %08x %08x\n",
1827 (r[6] << 24) | (r[7] >> 8), (r[7] << 24) | (r[8] >> 8), (r[8] << 24) | (r[9] >> 8),
1828 (r[9] << 24) | (r[10] >> 8), (r[10] << 24) | (r[11] >> 8),
1829 (r[11] << 24) | (r[12] >> 8));
1830 pr_info("R[13]: %08x\n", r[13]);
1831 pr_info("Fixed M: %06x\n", ((r[12] << 16) | (r[13] >> 16)) & 0xffffff);
1832 pr_info("Valid / not / and1 / and2 : %1x\n", (r[13] >> 12) & 0xf);
1833 pr_info("r 13-16: %08x %08x %08x %08x\n", r[13], r[14], r[15], r[16]);
1834 }
1835
1836 static int rtl930x_pie_rule_write(struct rtl838x_switch_priv *priv, int idx, struct pie_rule *pr)
1837 {
1838 // Access IACL table (2) via register 0
1839 struct table_reg *q = rtl_table_get(RTL9300_TBL_0, 2);
1840 u32 r[19];
1841 int i;
1842 int block = idx / PIE_BLOCK_SIZE;
1843 u32 t_select = sw_r32(RTL930X_PIE_BLK_TMPLTE_CTRL(block));
1844
1845 pr_debug("%s: %d, t_select: %08x\n", __func__, idx, t_select);
1846
1847 for (i = 0; i < 19; i++)
1848 r[i] = 0;
1849
1850 if (!pr->valid) {
1851 rtl_table_write(q, idx);
1852 rtl_table_release(q);
1853 return 0;
1854 }
1855 rtl930x_write_pie_fixed_fields(r, pr);
1856
1857 pr_debug("%s: template %d\n", __func__, (t_select >> (pr->tid * 4)) & 0xf);
1858 rtl930x_write_pie_templated(r, pr, fixed_templates[(t_select >> (pr->tid * 4)) & 0xf]);
1859
1860 rtl930x_write_pie_action(r, pr);
1861
1862 // rtl930x_pie_rule_dump_raw(r);
1863
1864 for (i = 0; i < 19; i++)
1865 sw_w32(r[i], rtl_table_data(q, i));
1866
1867 rtl_table_write(q, idx);
1868 rtl_table_release(q);
1869
1870 return 0;
1871 }
1872
1873 static bool rtl930x_pie_templ_has(int t, enum template_field_id field_type)
1874 {
1875 int i;
1876 enum template_field_id ft;
1877
1878 for (i = 0; i < N_FIXED_FIELDS; i++) {
1879 ft = fixed_templates[t][i];
1880 if (field_type == ft)
1881 return true;
1882 }
1883
1884 return false;
1885 }
1886
1887 /*
1888 * Verify that the rule pr is compatible with a given template t in block block
1889 * Note that this function is SoC specific since the values of e.g. TEMPLATE_FIELD_SIP0
1890 * depend on the SoC
1891 */
1892 static int rtl930x_pie_verify_template(struct rtl838x_switch_priv *priv,
1893 struct pie_rule *pr, int t, int block)
1894 {
1895 int i;
1896
1897 if (!pr->is_ipv6 && pr->sip_m && !rtl930x_pie_templ_has(t, TEMPLATE_FIELD_SIP0))
1898 return -1;
1899
1900 if (!pr->is_ipv6 && pr->dip_m && !rtl930x_pie_templ_has(t, TEMPLATE_FIELD_DIP0))
1901 return -1;
1902
1903 if (pr->is_ipv6) {
1904 if ((pr->sip6_m.s6_addr32[0] || pr->sip6_m.s6_addr32[1]
1905 || pr->sip6_m.s6_addr32[2] || pr->sip6_m.s6_addr32[3])
1906 && !rtl930x_pie_templ_has(t, TEMPLATE_FIELD_SIP2))
1907 return -1;
1908 if ((pr->dip6_m.s6_addr32[0] || pr->dip6_m.s6_addr32[1]
1909 || pr->dip6_m.s6_addr32[2] || pr->dip6_m.s6_addr32[3])
1910 && !rtl930x_pie_templ_has(t, TEMPLATE_FIELD_DIP2))
1911 return -1;
1912 }
1913
1914 if (ether_addr_to_u64(pr->smac) && !rtl930x_pie_templ_has(t, TEMPLATE_FIELD_SMAC0))
1915 return -1;
1916
1917 if (ether_addr_to_u64(pr->dmac) && !rtl930x_pie_templ_has(t, TEMPLATE_FIELD_DMAC0))
1918 return -1;
1919
1920 // TODO: Check more
1921
1922 i = find_first_zero_bit(&priv->pie_use_bm[block * 4], PIE_BLOCK_SIZE);
1923
1924 if (i >= PIE_BLOCK_SIZE)
1925 return -1;
1926
1927 return i + PIE_BLOCK_SIZE * block;
1928 }
1929
1930 static int rtl930x_pie_rule_add(struct rtl838x_switch_priv *priv, struct pie_rule *pr)
1931 {
1932 int idx, block, j, t;
1933 int min_block = 0;
1934 int max_block = priv->n_pie_blocks / 2;
1935
1936 if (pr->is_egress) {
1937 min_block = max_block;
1938 max_block = priv->n_pie_blocks;
1939 }
1940 pr_debug("In %s\n", __func__);
1941
1942 mutex_lock(&priv->pie_mutex);
1943
1944 for (block = min_block; block < max_block; block++) {
1945 for (j = 0; j < 2; j++) {
1946 t = (sw_r32(RTL930X_PIE_BLK_TMPLTE_CTRL(block)) >> (j * 4)) & 0xf;
1947 pr_debug("Testing block %d, template %d, template id %d\n", block, j, t);
1948 pr_debug("%s: %08x\n",
1949 __func__, sw_r32(RTL930X_PIE_BLK_TMPLTE_CTRL(block)));
1950 idx = rtl930x_pie_verify_template(priv, pr, t, block);
1951 if (idx >= 0)
1952 break;
1953 }
1954 if (j < 2)
1955 break;
1956 }
1957
1958 if (block >= priv->n_pie_blocks) {
1959 mutex_unlock(&priv->pie_mutex);
1960 return -EOPNOTSUPP;
1961 }
1962
1963 pr_debug("Using block: %d, index %d, template-id %d\n", block, idx, j);
1964 set_bit(idx, priv->pie_use_bm);
1965
1966 pr->valid = true;
1967 pr->tid = j; // Mapped to template number
1968 pr->tid_m = 0x1;
1969 pr->id = idx;
1970
1971 rtl930x_pie_lookup_enable(priv, idx);
1972 rtl930x_pie_rule_write(priv, idx, pr);
1973
1974 mutex_unlock(&priv->pie_mutex);
1975 return 0;
1976 }
1977
1978 /*
1979 * Delete a range of Packet Inspection Engine rules
1980 */
1981 static int rtl930x_pie_rule_del(struct rtl838x_switch_priv *priv, int index_from, int index_to)
1982 {
1983 u32 v = (index_from << 1)| (index_to << 12 ) | BIT(0);
1984
1985 pr_debug("%s: from %d to %d\n", __func__, index_from, index_to);
1986 mutex_lock(&priv->reg_mutex);
1987
1988 // Write from-to and execute bit into control register
1989 sw_w32(v, RTL930X_PIE_CLR_CTRL);
1990
1991 // Wait until command has completed
1992 do {
1993 } while (sw_r32(RTL930X_PIE_CLR_CTRL) & BIT(0));
1994
1995 mutex_unlock(&priv->reg_mutex);
1996 return 0;
1997 }
1998
1999 static void rtl930x_pie_rule_rm(struct rtl838x_switch_priv *priv, struct pie_rule *pr)
2000 {
2001 int idx = pr->id;
2002
2003 rtl930x_pie_rule_del(priv, idx, idx);
2004 clear_bit(idx, priv->pie_use_bm);
2005 }
2006
2007 static void rtl930x_pie_init(struct rtl838x_switch_priv *priv)
2008 {
2009 int i;
2010 u32 template_selectors;
2011
2012 mutex_init(&priv->pie_mutex);
2013
2014 pr_info("%s\n", __func__);
2015 // Enable ACL lookup on all ports, including CPU_PORT
2016 for (i = 0; i <= priv->cpu_port; i++)
2017 sw_w32(1, RTL930X_ACL_PORT_LOOKUP_CTRL(i));
2018
2019 // Include IPG in metering
2020 sw_w32_mask(0, 1, RTL930X_METER_GLB_CTRL);
2021
2022 // Delete all present rules, block size is 128 on all SoC families
2023 rtl930x_pie_rule_del(priv, 0, priv->n_pie_blocks * 128 - 1);
2024
2025 // Assign blocks 0-7 to VACL phase (bit = 0), blocks 8-15 to IACL (bit = 1)
2026 sw_w32(0xff00, RTL930X_PIE_BLK_PHASE_CTRL);
2027
2028 // Enable predefined templates 0, 1 for first quarter of all blocks
2029 template_selectors = 0 | (1 << 4);
2030 for (i = 0; i < priv->n_pie_blocks / 4; i++)
2031 sw_w32(template_selectors, RTL930X_PIE_BLK_TMPLTE_CTRL(i));
2032
2033 // Enable predefined templates 2, 3 for second quarter of all blocks
2034 template_selectors = 2 | (3 << 4);
2035 for (i = priv->n_pie_blocks / 4; i < priv->n_pie_blocks / 2; i++)
2036 sw_w32(template_selectors, RTL930X_PIE_BLK_TMPLTE_CTRL(i));
2037
2038 // Enable predefined templates 0, 1 for third half of all blocks
2039 template_selectors = 0 | (1 << 4);
2040 for (i = priv->n_pie_blocks / 2; i < priv->n_pie_blocks * 3 / 4; i++)
2041 sw_w32(template_selectors, RTL930X_PIE_BLK_TMPLTE_CTRL(i));
2042
2043 // Enable predefined templates 2, 3 for fourth quater of all blocks
2044 template_selectors = 2 | (3 << 4);
2045 for (i = priv->n_pie_blocks * 3 / 4; i < priv->n_pie_blocks; i++)
2046 sw_w32(template_selectors, RTL930X_PIE_BLK_TMPLTE_CTRL(i));
2047
2048 }
2049
2050 /*
2051 * Sets up an egress interface for L3 actions
2052 * Actions for ip4/6_icmp_redirect, ip4/6_pbr_icmp_redirect are:
2053 * 0: FORWARD, 1: DROP, 2: TRAP2CPU, 3: COPY2CPU, 4: TRAP2MASTERCPU 5: COPY2MASTERCPU
2054 * 6: HARDDROP
2055 * idx is the index in the HW interface table: idx < 0x80
2056 */
2057 static void rtl930x_set_l3_egress_intf(int idx, struct rtl838x_l3_intf *intf)
2058 {
2059 u32 u, v;
2060 // Read L3_EGR_INTF table (4) via register RTL9300_TBL_1
2061 struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 4);
2062
2063 // The table has 2 registers
2064 u = (intf->vid & 0xfff) << 9;
2065 u |= (intf->smac_idx & 0x3f) << 3;
2066 u |= (intf->ip4_mtu_id & 0x7);
2067
2068 v = (intf->ip6_mtu_id & 0x7) << 28;
2069 v |= (intf->ttl_scope & 0xff) << 20;
2070 v |= (intf->hl_scope & 0xff) << 12;
2071 v |= (intf->ip4_icmp_redirect & 0x7) << 9;
2072 v |= (intf->ip6_icmp_redirect & 0x7)<< 6;
2073 v |= (intf->ip4_pbr_icmp_redirect & 0x7) << 3;
2074 v |= (intf->ip6_pbr_icmp_redirect & 0x7);
2075
2076 sw_w32(u, rtl_table_data(r, 0));
2077 sw_w32(v, rtl_table_data(r, 1));
2078
2079 pr_info("%s writing to index %d: %08x %08x\n", __func__, idx, u, v);
2080 rtl_table_write(r, idx & 0x7f);
2081 rtl_table_release(r);
2082 }
2083
2084 /*
2085 * Reads a MAC entry for L3 termination as entry point for routing
2086 * from the hardware table
2087 * idx is the index into the L3_ROUTER_MAC table
2088 */
2089 static void rtl930x_get_l3_router_mac(u32 idx, struct rtl93xx_rt_mac *m)
2090 {
2091 u32 v, w;
2092 // Read L3_ROUTER_MAC table (0) via register RTL9300_TBL_1
2093 struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 0);
2094
2095 rtl_table_read(r, idx);
2096 // The table has a size of 7 registers, 64 entries
2097 v = sw_r32(rtl_table_data(r, 0));
2098 w = sw_r32(rtl_table_data(r, 3));
2099 m->valid = !!(v & BIT(20));
2100 if (!m->valid)
2101 goto out;
2102
2103 m->p_type = !!(v & BIT(19));
2104 m->p_id = (v >> 13) & 0x3f; // trunk id of port
2105 m->vid = v & 0xfff;
2106 m->vid_mask = w & 0xfff;
2107 m->action = sw_r32(rtl_table_data(r, 6)) & 0x7;
2108 m->mac_mask = ((((u64)sw_r32(rtl_table_data(r, 5))) << 32) & 0xffffffffffffULL)
2109 | (sw_r32(rtl_table_data(r, 4)));
2110 m->mac = ((((u64)sw_r32(rtl_table_data(r, 1))) << 32) & 0xffffffffffffULL)
2111 | (sw_r32(rtl_table_data(r, 2)));
2112 // Bits L3_INTF and BMSK_L3_INTF are 0
2113
2114 out:
2115 rtl_table_release(r);
2116 }
2117
2118 /*
2119 * Writes a MAC entry for L3 termination as entry point for routing
2120 * into the hardware table
2121 * idx is the index into the L3_ROUTER_MAC table
2122 */
2123 static void rtl930x_set_l3_router_mac(u32 idx, struct rtl93xx_rt_mac *m)
2124 {
2125 u32 v, w;
2126 // Read L3_ROUTER_MAC table (0) via register RTL9300_TBL_1
2127 struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 0);
2128
2129 // The table has a size of 7 registers, 64 entries
2130 v = BIT(20); // mac entry valid, port type is 0: individual
2131 v |= (m->p_id & 0x3f) << 13;
2132 v |= (m->vid & 0xfff); // Set the interface_id to the vlan id
2133
2134 w = m->vid_mask;
2135 w |= (m->p_id_mask & 0x3f) << 13;
2136
2137 sw_w32(v, rtl_table_data(r, 0));
2138 sw_w32(w, rtl_table_data(r, 3));
2139
2140 // Set MAC address, L3_INTF (bit 12 in register 1) needs to be 0
2141 sw_w32((u32)(m->mac), rtl_table_data(r, 2));
2142 sw_w32(m->mac >> 32, rtl_table_data(r, 1));
2143
2144 // Set MAC address mask, BMSK_L3_INTF (bit 12 in register 5) needs to be 0
2145 sw_w32((u32)(m->mac_mask >> 32), rtl_table_data(r, 4));
2146 sw_w32((u32)m->mac_mask, rtl_table_data(r, 5));
2147
2148 sw_w32(m->action & 0x7, rtl_table_data(r, 6));
2149
2150 pr_debug("%s writing index %d: %08x %08x %08x %08x %08x %08x %08x\n", __func__, idx,
2151 sw_r32(rtl_table_data(r, 0)), sw_r32(rtl_table_data(r, 1)), sw_r32(rtl_table_data(r, 2)),
2152 sw_r32(rtl_table_data(r, 3)), sw_r32(rtl_table_data(r, 4)), sw_r32(rtl_table_data(r, 5)),
2153 sw_r32(rtl_table_data(r, 6))
2154 );
2155 rtl_table_write(r, idx);
2156 rtl_table_release(r);
2157 }
2158
2159 /*
2160 * Get the Destination-MAC of an L3 egress interface or the Source MAC for routed packets
2161 * from the SoC's L3_EGR_INTF_MAC table
2162 * Indexes 0-2047 are DMACs, 2048+ are SMACs
2163 */
2164 static u64 rtl930x_get_l3_egress_mac(u32 idx)
2165 {
2166 u64 mac;
2167 // Read L3_EGR_INTF_MAC table (2) via register RTL9300_TBL_2
2168 struct table_reg *r = rtl_table_get(RTL9300_TBL_2, 2);
2169
2170 rtl_table_read(r, idx);
2171 // The table has a size of 2 registers
2172 mac = sw_r32(rtl_table_data(r, 0));
2173 mac <<= 32;
2174 mac |= sw_r32(rtl_table_data(r, 1));
2175 rtl_table_release(r);
2176
2177 return mac;
2178 }
2179 /*
2180 * Set the Destination-MAC of a route or the Source MAC of an L3 egress interface
2181 * in the SoC's L3_EGR_INTF_MAC table
2182 * Indexes 0-2047 are DMACs, 2048+ are SMACs
2183 */
2184 static void rtl930x_set_l3_egress_mac(u32 idx, u64 mac)
2185 {
2186 // Access L3_EGR_INTF_MAC table (2) via register RTL9300_TBL_2
2187 struct table_reg *r = rtl_table_get(RTL9300_TBL_2, 2);
2188
2189 // The table has a size of 2 registers
2190 sw_w32(mac >> 32, rtl_table_data(r, 0));
2191 sw_w32(mac, rtl_table_data(r, 1));
2192
2193 pr_debug("%s: setting index %d to %016llx\n", __func__, idx, mac);
2194 rtl_table_write(r, idx);
2195 rtl_table_release(r);
2196 }
2197
2198 /*
2199 * Configure L3 routing settings of the device:
2200 * - MTUs
2201 * - Egress interface
2202 * - The router's MAC address on which routed packets are expected
2203 * - MAC addresses used as source macs of routed packets
2204 */
2205 int rtl930x_l3_setup(struct rtl838x_switch_priv *priv)
2206 {
2207 int i;
2208
2209 // Setup MTU with id 0 for default interface
2210 for (i = 0; i < MAX_INTF_MTUS; i++)
2211 priv->intf_mtu_count[i] = priv->intf_mtus[i] = 0;
2212
2213 priv->intf_mtu_count[0] = 0; // Needs to stay forever
2214 priv->intf_mtus[0] = DEFAULT_MTU;
2215 sw_w32_mask(0xffff, DEFAULT_MTU, RTL930X_L3_IP_MTU_CTRL(0));
2216 sw_w32_mask(0xffff, DEFAULT_MTU, RTL930X_L3_IP6_MTU_CTRL(0));
2217 priv->intf_mtus[1] = DEFAULT_MTU;
2218 sw_w32_mask(0xffff0000, DEFAULT_MTU << 16, RTL930X_L3_IP_MTU_CTRL(0));
2219 sw_w32_mask(0xffff0000, DEFAULT_MTU << 16, RTL930X_L3_IP6_MTU_CTRL(0));
2220
2221 sw_w32_mask(0xffff, DEFAULT_MTU, RTL930X_L3_IP_MTU_CTRL(1));
2222 sw_w32_mask(0xffff, DEFAULT_MTU, RTL930X_L3_IP6_MTU_CTRL(1));
2223 sw_w32_mask(0xffff0000, DEFAULT_MTU << 16, RTL930X_L3_IP_MTU_CTRL(1));
2224 sw_w32_mask(0xffff0000, DEFAULT_MTU << 16, RTL930X_L3_IP6_MTU_CTRL(1));
2225
2226 // Clear all source port MACs
2227 for (i = 0; i < MAX_SMACS; i++)
2228 rtl930x_set_l3_egress_mac(L3_EGRESS_DMACS + i, 0ULL);
2229
2230 // Configure the default L3 hash algorithm
2231 sw_w32_mask(BIT(2), 0, RTL930X_L3_HOST_TBL_CTRL); // Algorithm selection 0 = 0
2232 sw_w32_mask(0, BIT(3), RTL930X_L3_HOST_TBL_CTRL); // Algorithm selection 1 = 1
2233
2234 pr_info("L3_IPUC_ROUTE_CTRL %08x, IPMC_ROUTE %08x, IP6UC_ROUTE %08x, IP6MC_ROUTE %08x\n",
2235 sw_r32(RTL930X_L3_IPUC_ROUTE_CTRL), sw_r32(RTL930X_L3_IPMC_ROUTE_CTRL),
2236 sw_r32(RTL930X_L3_IP6UC_ROUTE_CTRL), sw_r32(RTL930X_L3_IP6MC_ROUTE_CTRL));
2237 sw_w32_mask(0, 1, RTL930X_L3_IPUC_ROUTE_CTRL);
2238 sw_w32_mask(0, 1, RTL930X_L3_IP6UC_ROUTE_CTRL);
2239 sw_w32_mask(0, 1, RTL930X_L3_IPMC_ROUTE_CTRL);
2240 sw_w32_mask(0, 1, RTL930X_L3_IP6MC_ROUTE_CTRL);
2241
2242 sw_w32(0x00002001, RTL930X_L3_IPUC_ROUTE_CTRL);
2243 sw_w32(0x00014581, RTL930X_L3_IP6UC_ROUTE_CTRL);
2244 sw_w32(0x00000501, RTL930X_L3_IPMC_ROUTE_CTRL);
2245 sw_w32(0x00012881, RTL930X_L3_IP6MC_ROUTE_CTRL);
2246
2247 pr_info("L3_IPUC_ROUTE_CTRL %08x, IPMC_ROUTE %08x, IP6UC_ROUTE %08x, IP6MC_ROUTE %08x\n",
2248 sw_r32(RTL930X_L3_IPUC_ROUTE_CTRL), sw_r32(RTL930X_L3_IPMC_ROUTE_CTRL),
2249 sw_r32(RTL930X_L3_IP6UC_ROUTE_CTRL), sw_r32(RTL930X_L3_IP6MC_ROUTE_CTRL));
2250
2251 // Trap non-ip traffic to the CPU-port (e.g. ARP so we stay reachable)
2252 sw_w32_mask(0x3 << 8, 0x1 << 8, RTL930X_L3_IP_ROUTE_CTRL);
2253 pr_info("L3_IP_ROUTE_CTRL %08x\n", sw_r32(RTL930X_L3_IP_ROUTE_CTRL));
2254
2255 // PORT_ISO_RESTRICT_ROUTE_CTRL ?
2256
2257 // Do not use prefix route 0 because of HW limitations
2258 set_bit(0, priv->route_use_bm);
2259
2260 return 0;
2261 }
2262
2263 static u32 rtl930x_packet_cntr_read(int counter)
2264 {
2265 u32 v;
2266
2267 // Read LOG table (3) via register RTL9300_TBL_0
2268 struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 3);
2269
2270 pr_debug("In %s, id %d\n", __func__, counter);
2271 rtl_table_read(r, counter / 2);
2272
2273 pr_debug("Registers: %08x %08x\n",
2274 sw_r32(rtl_table_data(r, 0)), sw_r32(rtl_table_data(r, 1)));
2275 // The table has a size of 2 registers
2276 if (counter % 2)
2277 v = sw_r32(rtl_table_data(r, 0));
2278 else
2279 v = sw_r32(rtl_table_data(r, 1));
2280
2281 rtl_table_release(r);
2282
2283 return v;
2284 }
2285
2286 static void rtl930x_packet_cntr_clear(int counter)
2287 {
2288 // Access LOG table (3) via register RTL9300_TBL_0
2289 struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 3);
2290
2291 pr_info("In %s, id %d\n", __func__, counter);
2292 // The table has a size of 2 registers
2293 if (counter % 2)
2294 sw_w32(0, rtl_table_data(r, 0));
2295 else
2296 sw_w32(0, rtl_table_data(r, 1));
2297
2298 rtl_table_write(r, counter / 2);
2299
2300 rtl_table_release(r);
2301 }
2302
2303 void rtl930x_vlan_port_pvidmode_set(int port, enum pbvlan_type type, enum pbvlan_mode mode)
2304 {
2305 if (type == PBVLAN_TYPE_INNER)
2306 sw_w32_mask(0x3, mode, RTL930X_VLAN_PORT_PB_VLAN + (port << 2));
2307 else
2308 sw_w32_mask(0x3 << 14, mode << 14 ,RTL930X_VLAN_PORT_PB_VLAN + (port << 2));
2309 }
2310
2311 void rtl930x_vlan_port_pvid_set(int port, enum pbvlan_type type, int pvid)
2312 {
2313 if (type == PBVLAN_TYPE_INNER)
2314 sw_w32_mask(0xfff << 2, pvid << 2, RTL930X_VLAN_PORT_PB_VLAN + (port << 2));
2315 else
2316 sw_w32_mask(0xfff << 16, pvid << 16, RTL930X_VLAN_PORT_PB_VLAN + (port << 2));
2317 }
2318
2319 static int rtl930x_set_ageing_time(unsigned long msec)
2320 {
2321 int t = sw_r32(RTL930X_L2_AGE_CTRL);
2322
2323 t &= 0x1FFFFF;
2324 t = (t * 7) / 10;
2325 pr_debug("L2 AGING time: %d sec\n", t);
2326
2327 t = (msec / 100 + 6) / 7;
2328 t = t > 0x1FFFFF ? 0x1FFFFF : t;
2329 sw_w32_mask(0x1FFFFF, t, RTL930X_L2_AGE_CTRL);
2330 pr_debug("Dynamic aging for ports: %x\n", sw_r32(RTL930X_L2_PORT_AGE_CTRL));
2331
2332 return 0;
2333 }
2334
2335 static void rtl930x_set_igr_filter(int port, enum igr_filter state)
2336 {
2337 sw_w32_mask(0x3 << ((port & 0xf)<<1), state << ((port & 0xf)<<1),
2338 RTL930X_VLAN_PORT_IGR_FLTR + (((port >> 4) << 2)));
2339 }
2340
2341 static void rtl930x_set_egr_filter(int port, enum egr_filter state)
2342 {
2343 sw_w32_mask(0x1 << (port % 0x1D), state << (port % 0x1D),
2344 RTL930X_VLAN_PORT_EGR_FLTR + (((port / 29) << 2)));
2345 }
2346
2347 void rtl930x_set_distribution_algorithm(int group, int algoidx, u32 algomsk)
2348 {
2349 u32 l3shift = 0;
2350 u32 newmask = 0;
2351
2352 /* TODO: for now we set algoidx to 0 */
2353 algoidx = 0;
2354 if (algomsk & TRUNK_DISTRIBUTION_ALGO_SIP_BIT) {
2355 l3shift = 4;
2356 newmask |= TRUNK_DISTRIBUTION_ALGO_L3_SIP_BIT;
2357 }
2358 if (algomsk & TRUNK_DISTRIBUTION_ALGO_DIP_BIT) {
2359 l3shift = 4;
2360 newmask |= TRUNK_DISTRIBUTION_ALGO_L3_DIP_BIT;
2361 }
2362 if (algomsk & TRUNK_DISTRIBUTION_ALGO_SRC_L4PORT_BIT) {
2363 l3shift = 4;
2364 newmask |= TRUNK_DISTRIBUTION_ALGO_L3_SRC_L4PORT_BIT;
2365 }
2366 if (algomsk & TRUNK_DISTRIBUTION_ALGO_SRC_L4PORT_BIT) {
2367 l3shift = 4;
2368 newmask |= TRUNK_DISTRIBUTION_ALGO_L3_SRC_L4PORT_BIT;
2369 }
2370
2371 if (l3shift == 4) {
2372 if (algomsk & TRUNK_DISTRIBUTION_ALGO_SMAC_BIT)
2373 newmask |= TRUNK_DISTRIBUTION_ALGO_L3_SMAC_BIT;
2374
2375 if (algomsk & TRUNK_DISTRIBUTION_ALGO_DMAC_BIT)
2376 newmask |= TRUNK_DISTRIBUTION_ALGO_L3_DMAC_BIT;
2377 } else {
2378 if (algomsk & TRUNK_DISTRIBUTION_ALGO_SMAC_BIT)
2379 newmask |= TRUNK_DISTRIBUTION_ALGO_L2_SMAC_BIT;
2380 if (algomsk & TRUNK_DISTRIBUTION_ALGO_DMAC_BIT)
2381 newmask |= TRUNK_DISTRIBUTION_ALGO_L2_DMAC_BIT;
2382 }
2383
2384 sw_w32(newmask << l3shift, RTL930X_TRK_HASH_CTRL + (algoidx << 2));
2385 }
2386
2387 static void rtl930x_led_init(struct rtl838x_switch_priv *priv)
2388 {
2389 int i, pos;
2390 u32 v, pm = 0, set;
2391 u32 setlen;
2392 const __be32 *led_set;
2393 char set_name[9];
2394 struct device_node *node;
2395
2396 pr_info("%s called\n", __func__);
2397 node = of_find_compatible_node(NULL, NULL, "realtek,rtl9300-leds");
2398 if (!node) {
2399 pr_info("%s No compatible LED node found\n", __func__);
2400 return;
2401 }
2402
2403 for (i= 0; i < priv->cpu_port; i++) {
2404 pos = (i << 1) % 32;
2405 sw_w32_mask(0x3 << pos, 0, RTL930X_LED_PORT_FIB_SET_SEL_CTRL(i));
2406 sw_w32_mask(0x3 << pos, 0, RTL930X_LED_PORT_COPR_SET_SEL_CTRL(i));
2407
2408 if (!priv->ports[i].phy)
2409 continue;
2410
2411 v = 0x1;
2412 if (priv->ports[i].is10G)
2413 v = 0x3;
2414 if (priv->ports[i].phy_is_integrated)
2415 v = 0x1;
2416 sw_w32_mask(0x3 << pos, v << pos, RTL930X_LED_PORT_NUM_CTRL(i));
2417
2418 pm |= BIT(i);
2419
2420 set = priv->ports[i].led_set;
2421 sw_w32_mask(0, set << pos, RTL930X_LED_PORT_COPR_SET_SEL_CTRL(i));
2422 sw_w32_mask(0, set << pos, RTL930X_LED_PORT_FIB_SET_SEL_CTRL(i));
2423 }
2424
2425 for (i = 0; i < 4; i++) {
2426 sprintf(set_name, "led_set%d", i);
2427 led_set = of_get_property(node, set_name, &setlen);
2428 if (!led_set || setlen != 16)
2429 break;
2430 v = be32_to_cpup(led_set) << 16 | be32_to_cpup(led_set + 1);
2431 sw_w32(v, RTL930X_LED_SET0_0_CTRL - 4 - i * 8);
2432 v = be32_to_cpup(led_set + 2) << 16 | be32_to_cpup(led_set + 3);
2433 sw_w32(v, RTL930X_LED_SET0_0_CTRL - i * 8);
2434 }
2435
2436 // Set LED mode to serial (0x1)
2437 sw_w32_mask(0x3, 0x1, RTL930X_LED_GLB_CTRL);
2438
2439 // Set port type masks
2440 sw_w32(pm, RTL930X_LED_PORT_COPR_MASK_CTRL);
2441 sw_w32(pm, RTL930X_LED_PORT_FIB_MASK_CTRL);
2442 sw_w32(pm, RTL930X_LED_PORT_COMBO_MASK_CTRL);
2443
2444 for (i = 0; i < 24; i++)
2445 pr_info("%s %08x: %08x\n",__func__, 0xbb00cc00 + i * 4, sw_r32(0xcc00 + i * 4));
2446 }
2447
2448 const struct rtl838x_reg rtl930x_reg = {
2449 .mask_port_reg_be = rtl838x_mask_port_reg,
2450 .set_port_reg_be = rtl838x_set_port_reg,
2451 .get_port_reg_be = rtl838x_get_port_reg,
2452 .mask_port_reg_le = rtl838x_mask_port_reg,
2453 .set_port_reg_le = rtl838x_set_port_reg,
2454 .get_port_reg_le = rtl838x_get_port_reg,
2455 .stat_port_rst = RTL930X_STAT_PORT_RST,
2456 .stat_rst = RTL930X_STAT_RST,
2457 .stat_port_std_mib = RTL930X_STAT_PORT_MIB_CNTR,
2458 .traffic_enable = rtl930x_traffic_enable,
2459 .traffic_disable = rtl930x_traffic_disable,
2460 .traffic_get = rtl930x_traffic_get,
2461 .traffic_set = rtl930x_traffic_set,
2462 .l2_ctrl_0 = RTL930X_L2_CTRL,
2463 .l2_ctrl_1 = RTL930X_L2_AGE_CTRL,
2464 .l2_port_aging_out = RTL930X_L2_PORT_AGE_CTRL,
2465 .set_ageing_time = rtl930x_set_ageing_time,
2466 .smi_poll_ctrl = RTL930X_SMI_POLL_CTRL, // TODO: Difference to RTL9300_SMI_PRVTE_POLLING_CTRL
2467 .l2_tbl_flush_ctrl = RTL930X_L2_TBL_FLUSH_CTRL,
2468 .exec_tbl0_cmd = rtl930x_exec_tbl0_cmd,
2469 .exec_tbl1_cmd = rtl930x_exec_tbl1_cmd,
2470 .tbl_access_data_0 = rtl930x_tbl_access_data_0,
2471 .isr_glb_src = RTL930X_ISR_GLB,
2472 .isr_port_link_sts_chg = RTL930X_ISR_PORT_LINK_STS_CHG,
2473 .imr_port_link_sts_chg = RTL930X_IMR_PORT_LINK_STS_CHG,
2474 .imr_glb = RTL930X_IMR_GLB,
2475 .vlan_tables_read = rtl930x_vlan_tables_read,
2476 .vlan_set_tagged = rtl930x_vlan_set_tagged,
2477 .vlan_set_untagged = rtl930x_vlan_set_untagged,
2478 .vlan_profile_dump = rtl930x_vlan_profile_dump,
2479 .vlan_profile_setup = rtl930x_vlan_profile_setup,
2480 .vlan_fwd_on_inner = rtl930x_vlan_fwd_on_inner,
2481 .set_vlan_igr_filter = rtl930x_set_igr_filter,
2482 .set_vlan_egr_filter = rtl930x_set_egr_filter,
2483 .stp_get = rtl930x_stp_get,
2484 .stp_set = rtl930x_stp_set,
2485 .mac_force_mode_ctrl = rtl930x_mac_force_mode_ctrl,
2486 .mac_port_ctrl = rtl930x_mac_port_ctrl,
2487 .l2_port_new_salrn = rtl930x_l2_port_new_salrn,
2488 .l2_port_new_sa_fwd = rtl930x_l2_port_new_sa_fwd,
2489 .mir_ctrl = RTL930X_MIR_CTRL,
2490 .mir_dpm = RTL930X_MIR_DPM_CTRL,
2491 .mir_spm = RTL930X_MIR_SPM_CTRL,
2492 .mac_link_sts = RTL930X_MAC_LINK_STS,
2493 .mac_link_dup_sts = RTL930X_MAC_LINK_DUP_STS,
2494 .mac_link_spd_sts = rtl930x_mac_link_spd_sts,
2495 .mac_rx_pause_sts = RTL930X_MAC_RX_PAUSE_STS,
2496 .mac_tx_pause_sts = RTL930X_MAC_TX_PAUSE_STS,
2497 .read_l2_entry_using_hash = rtl930x_read_l2_entry_using_hash,
2498 .write_l2_entry_using_hash = rtl930x_write_l2_entry_using_hash,
2499 .read_cam = rtl930x_read_cam,
2500 .write_cam = rtl930x_write_cam,
2501 .vlan_port_tag_sts_ctrl = RTL930X_VLAN_PORT_TAG_STS_CTRL,
2502 .vlan_port_pvidmode_set = rtl930x_vlan_port_pvidmode_set,
2503 .vlan_port_pvid_set = rtl930x_vlan_port_pvid_set,
2504 .trk_mbr_ctr = rtl930x_trk_mbr_ctr,
2505 .rma_bpdu_fld_pmask = RTL930X_RMA_BPDU_FLD_PMSK,
2506 .init_eee = rtl930x_init_eee,
2507 .port_eee_set = rtl930x_port_eee_set,
2508 .eee_port_ability = rtl930x_eee_port_ability,
2509 .l2_hash_seed = rtl930x_l2_hash_seed,
2510 .l2_hash_key = rtl930x_l2_hash_key,
2511 .read_mcast_pmask = rtl930x_read_mcast_pmask,
2512 .write_mcast_pmask = rtl930x_write_mcast_pmask,
2513 .pie_init = rtl930x_pie_init,
2514 .pie_rule_write = rtl930x_pie_rule_write,
2515 .pie_rule_add = rtl930x_pie_rule_add,
2516 .pie_rule_rm = rtl930x_pie_rule_rm,
2517 .l2_learning_setup = rtl930x_l2_learning_setup,
2518 .packet_cntr_read = rtl930x_packet_cntr_read,
2519 .packet_cntr_clear = rtl930x_packet_cntr_clear,
2520 .route_read = rtl930x_route_read,
2521 .route_write = rtl930x_route_write,
2522 .host_route_write = rtl930x_host_route_write,
2523 .l3_setup = rtl930x_l3_setup,
2524 .set_l3_nexthop = rtl930x_set_l3_nexthop,
2525 .get_l3_nexthop = rtl930x_get_l3_nexthop,
2526 .get_l3_egress_mac = rtl930x_get_l3_egress_mac,
2527 .set_l3_egress_mac = rtl930x_set_l3_egress_mac,
2528 .find_l3_slot = rtl930x_find_l3_slot,
2529 .route_lookup_hw = rtl930x_route_lookup_hw,
2530 .get_l3_router_mac = rtl930x_get_l3_router_mac,
2531 .set_l3_router_mac = rtl930x_set_l3_router_mac,
2532 .set_l3_egress_intf = rtl930x_set_l3_egress_intf,
2533 .set_distribution_algorithm = rtl930x_set_distribution_algorithm,
2534 .led_init = rtl930x_led_init,
2535 };
Kevin D-Bs staging tree