target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl931x.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2
   3 #include <asm/mach-rtl838x/mach-rtl83xx.h>
   4 #include "rtl83xx.h"
   5
   6 extern struct mutex smi_lock;
   7 extern struct rtl83xx_soc_info soc_info;
   8
   9 inline void rtl931x_exec_tbl0_cmd(u32 cmd)
  10 {
  11         sw_w32(cmd, RTL931X_TBL_ACCESS_CTRL_0);
  12         do { } while (sw_r32(RTL931X_TBL_ACCESS_CTRL_0) & (1 << 20));
  13 }
  14
  15 inline void rtl931x_exec_tbl1_cmd(u32 cmd)
  16 {
  17         sw_w32(cmd, RTL931X_TBL_ACCESS_CTRL_1);
  18         do { } while (sw_r32(RTL931X_TBL_ACCESS_CTRL_1) & (1 << 17));
  19 }
  20
  21 inline int rtl931x_tbl_access_data_0(int i)
  22 {
  23         return RTL931X_TBL_ACCESS_DATA_0(i);
  24 }
  25
  26 void rtl931x_vlan_profile_dump(int index)
  27 {
  28         u64 profile[4];
  29
  30         if (index < 0 || index > 15)
  31                 return;
  32
  33         profile[0] = sw_r32(RTL931X_VLAN_PROFILE_SET(index));
  34         profile[1] = (sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 4) & 0x1FFFFFFFULL) << 32
  35                 | (sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 8) & 0xFFFFFFFF);
  36         profile[2] = (sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 16) & 0xFFFFFFFFULL) << 32
  37                 | (sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 12) & 0x1FFFFFFULL);
  38         profile[3] = (sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 20) & 0x1FFFFFFFULL) << 32
  39                 | (sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 24) & 0xFFFFFFFF);
  40
  41         pr_info("VLAN %d: L2 learning: %d, L2 Unknown MultiCast Field %llx, \
  42                 IPv4 Unknown MultiCast Field %llx, IPv6 Unknown MultiCast Field: %llx",
  43                 index, (u32) (profile[0] & (3 << 14)), profile[1], profile[2], profile[3]);
  44 }
  45
  46 static void rtl931x_stp_get(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])
  47 {
  48         int i;
  49         u32 cmd = 1 << 20 /* Execute cmd */
  50                 | 0 << 19 /* Read */
  51                 | 2 << 15 /* Table type 0b10 */
  52                 | (msti & 0x3fff);
  53         priv->r->exec_tbl0_cmd(cmd);
  54
  55         for (i = 0; i < 4; i++)
  56                 port_state[i] = sw_r32(priv->r->tbl_access_data_0(i));
  57 }
  58
  59 static void rtl931x_stp_set(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])
  60 {
  61         int i;
  62         u32 cmd = 1 << 20 /* Execute cmd */
  63                 | 1 << 19 /* Write */
  64                 | 5 << 15 /* Table type 0b101 */
  65                 | (msti & 0x3fff);
  66         for (i = 0; i < 4; i++)
  67                 sw_w32(port_state[i], priv->r->tbl_access_data_0(i));
  68         priv->r->exec_tbl0_cmd(cmd);
  69 }
  70
  71 inline static int rtl931x_trk_mbr_ctr(int group)
  72 {
  73         return RTL931X_TRK_MBR_CTRL + (group << 2);
  74 }
  75
  76 static void rtl931x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info)
  77 {
  78         u32 v, w, x, y;
  79         // Read VLAN table (3) via register 0
  80         struct table_reg *r = rtl_table_get(RTL9310_TBL_0, 3);
  81
  82         rtl_table_read(r, vlan);
  83         v = sw_r32(rtl_table_data(r, 0));
  84         w = sw_r32(rtl_table_data(r, 1));
  85         x = sw_r32(rtl_table_data(r, 2));
  86         y = sw_r32(rtl_table_data(r, 3));
  87         pr_debug("VLAN_READ %d: %08x %08x\n", vlan, v, w);
  88         rtl_table_release(r);
  89
  90         info->tagged_ports = ((u64) v) << 25 | (w >> 7);
  91         info->profile_id = (x >> 16) & 0xf;
  92         info->hash_mc_fid = !!(x & BIT(30));
  93         info->hash_uc_fid = !!(x & BIT(31));
  94         info->fid = w & 0x7f;
  95         // TODO: use also info in 4th register
  96
  97         // Read UNTAG table via table register 3
  98         r = rtl_table_get(RTL9310_TBL_3, 0);
  99         rtl_table_read(r, vlan);
 100         v = ((u64)sw_r32(rtl_table_data(r, 0))) << 25;
 101         v |= sw_r32(rtl_table_data(r, 1)) >> 7;
 102         rtl_table_release(r);
 103
 104         info->untagged_ports = v;
 105 }
 106
 107 static void rtl931x_vlan_set_tagged(u32 vlan, struct rtl838x_vlan_info *info)
 108 {
 109         u32 v, w, x;
 110         // Access VLAN table (1) via register 0
 111         struct table_reg *r = rtl_table_get(RTL9310_TBL_0, 3);
 112
 113         v = info->tagged_ports << 7;
 114         w = (info->tagged_ports & 0x7f000000) << 25;
 115         w |= (u32)info->fid;
 116         x = info->profile_id << 16;
 117         w |= info->hash_mc_fid ? BIT(30) : 0;
 118         w |= info->hash_uc_fid ? BIT(31) : 0;
 119         // TODO: use also info in 4th register
 120
 121         sw_w32(v, rtl_table_data(r, 0));
 122         sw_w32(w, rtl_table_data(r, 1));
 123         sw_w32(x, rtl_table_data(r, 2));
 124
 125         rtl_table_write(r, vlan);
 126         rtl_table_release(r);
 127 }
 128
 129 static void rtl931x_vlan_set_untagged(u32 vlan, u64 portmask)
 130 {
 131         struct table_reg *r = rtl_table_get(RTL9310_TBL_3, 0);
 132
 133         rtl839x_set_port_reg_be(portmask << 7, rtl_table_data(r, 0));
 134         rtl_table_write(r, vlan);
 135         rtl_table_release(r);
 136 }
 137
 138 static inline int rtl931x_mac_force_mode_ctrl(int p)
 139 {
 140         return RTL931X_MAC_FORCE_MODE_CTRL + (p << 2);
 141 }
 142
 143 static inline int rtl931x_mac_link_spd_sts(int p)
 144 {
 145         return RTL931X_MAC_LINK_SPD_STS(p);
 146 }
 147
 148 static inline int rtl931x_mac_port_ctrl(int p)
 149 {
 150         return RTL931X_MAC_PORT_CTRL(p);
 151 }
 152
 153 static inline int rtl931x_l2_port_new_salrn(int p)
 154 {
 155         return RTL931X_L2_PORT_NEW_SALRN(p);
 156 }
 157
 158 static inline int rtl931x_l2_port_new_sa_fwd(int p)
 159 {
 160         return RTL931X_L2_PORT_NEW_SA_FWD(p);
 161 }
 162
 163 static u64 rtl931x_read_l2_entry_using_hash(u32 hash, u32 position, struct rtl838x_l2_entry *e)
 164 {
 165         u64 entry = 0;
 166
 167         // TODO: Implement
 168         return entry;
 169 }
 170
 171 static u64 rtl931x_read_cam(int idx, struct rtl838x_l2_entry *e)
 172 {
 173         u64 entry = 0;
 174
 175         // TODO: Implement
 176         return entry;
 177 }
 178
 179 irqreturn_t rtl931x_switch_irq(int irq, void *dev_id)
 180 {
 181         struct dsa_switch *ds = dev_id;
 182         u32 status = sw_r32(RTL931X_ISR_GLB_SRC);
 183         u64 ports = rtl839x_get_port_reg_le(RTL931X_ISR_PORT_LINK_STS_CHG);
 184         u64 link;
 185         int i;
 186
 187         /* Clear status */
 188         rtl839x_set_port_reg_le(ports, RTL931X_ISR_PORT_LINK_STS_CHG);
 189         pr_info("RTL9310 Link change: status: %x, ports %llx\n", status, ports);
 190
 191         for (i = 0; i < 56; i++) {
 192                 if (ports & BIT_ULL(i)) {
 193                         link = rtl839x_get_port_reg_le(RTL931X_MAC_LINK_STS);
 194                         if (link & BIT_ULL(i))
 195                                 dsa_port_phylink_mac_change(ds, i, true);
 196                         else
 197                                 dsa_port_phylink_mac_change(ds, i, false);
 198                 }
 199         }
 200         return IRQ_HANDLED;
 201 }
 202
 203 int rtl931x_write_phy(u32 port, u32 page, u32 reg, u32 val)
 204 {
 205         u32 v;
 206         int err = 0;
 207
 208         val &= 0xffff;
 209         if (port > 63 || page > 4095 || reg > 31)
 210                 return -ENOTSUPP;
 211
 212         mutex_lock(&smi_lock);
 213         /* Clear both port registers */
 214         sw_w32(0, RTL931X_SMI_INDRT_ACCESS_CTRL_2);
 215         sw_w32(0, RTL931X_SMI_INDRT_ACCESS_CTRL_2 + 4);
 216         sw_w32_mask(0, BIT(port), RTL931X_SMI_INDRT_ACCESS_CTRL_2+ (port % 32) * 4);
 217
 218         sw_w32_mask(0xffff0000, val << 16, RTL931X_SMI_INDRT_ACCESS_CTRL_3);
 219
 220         v = reg << 6 | page << 11 ;
 221         sw_w32(v, RTL931X_SMI_INDRT_ACCESS_CTRL_0);
 222
 223         sw_w32(0x1ff, RTL931X_SMI_INDRT_ACCESS_CTRL_1);
 224
 225         v |= 1 << 3 | 1; /* Write operation and execute */
 226         sw_w32(v, RTL931X_SMI_INDRT_ACCESS_CTRL_0);
 227
 228         do {
 229         } while (sw_r32(RTL931X_SMI_INDRT_ACCESS_CTRL_0) & 0x1);
 230
 231         if (sw_r32(RTL931X_SMI_INDRT_ACCESS_CTRL_0) & 0x2)
 232                 err = -EIO;
 233
 234         mutex_unlock(&smi_lock);
 235         return err;
 236 }
 237
 238 int rtl931x_read_phy(u32 port, u32 page, u32 reg, u32 *val)
 239 {
 240         u32 v;
 241
 242         if (port > 63 || page > 4095 || reg > 31)
 243                 return -ENOTSUPP;
 244
 245         mutex_lock(&smi_lock);
 246
 247         sw_w32_mask(0xffff, port, RTL931X_SMI_INDRT_ACCESS_CTRL_3);
 248         v = reg << 6 | page << 11; // TODO: ACCESS Offset? Park page
 249         sw_w32(v, RTL931X_SMI_INDRT_ACCESS_CTRL_0);
 250
 251         sw_w32(0x1ff, RTL931X_SMI_INDRT_ACCESS_CTRL_1);
 252
 253         v |= 1;
 254         sw_w32(v, RTL931X_SMI_INDRT_ACCESS_CTRL_0);
 255
 256         do {
 257         } while (sw_r32(RTL931X_SMI_INDRT_ACCESS_CTRL_0) & 0x1);
 258
 259         *val = (sw_r32(RTL931X_SMI_INDRT_ACCESS_CTRL_3) & 0xffff0000) >> 16;
 260
 261         pr_info("%s: port %d, page: %d, reg: %x, val: %x\n", __func__, port, page, reg, *val);
 262
 263         mutex_unlock(&smi_lock);
 264         return 0;
 265 }
 266
 267 /*
 268  * Read an mmd register of the PHY
 269  */
 270 int rtl931x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val)
 271 {
 272         int err = 0;
 273         u32 v;
 274         int type = 1; // TODO: For C45 PHYs need to set to 2
 275
 276         mutex_lock(&smi_lock);
 277
 278         // Set PHY to access via port-number
 279         sw_w32(port << 5, RTL931X_SMI_INDRT_ACCESS_BC_PHYID_CTRL);
 280
 281         // Set MMD device number and register to write to
 282         sw_w32(devnum << 16 | (regnum & 0xffff), RTL931X_SMI_INDRT_ACCESS_MMD_CTRL);
 283
 284         v = type << 2 | BIT(0); // MMD-access-type | EXEC
 285         sw_w32(v, RTL931X_SMI_INDRT_ACCESS_CTRL_0);
 286
 287         do {
 288                 v = sw_r32(RTL931X_SMI_INDRT_ACCESS_CTRL_0);
 289         } while (v & BIT(0));
 290
 291         // There is no error-checking via BIT 1 of v, as it does not seem to be set correctly
 292
 293         *val = (sw_r32(RTL931X_SMI_INDRT_ACCESS_CTRL_3) & 0xffff);
 294
 295         pr_debug("%s: port %d, regnum: %x, val: %x (err %d)\n", __func__, port, regnum, *val, err);
 296
 297         mutex_unlock(&smi_lock);
 298
 299         return err;
 300 }
 301
 302 /*
 303  * Write to an mmd register of the PHY
 304  */
 305 int rtl931x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val)
 306 {
 307         int err = 0;
 308         u32 v;
 309         int type = 1; // TODO: For C45 PHYs need to set to 2
 310
 311         mutex_lock(&smi_lock);
 312
 313         // Set PHY to access via port-number
 314         sw_w32(port << 5, RTL931X_SMI_INDRT_ACCESS_BC_PHYID_CTRL);
 315
 316         // Set data to write
 317         sw_w32_mask(0xffff << 16, val << 16, RTL931X_SMI_INDRT_ACCESS_CTRL_3);
 318
 319         // Set MMD device number and register to write to
 320         sw_w32(devnum << 16 | (regnum & 0xffff), RTL931X_SMI_INDRT_ACCESS_MMD_CTRL);
 321
 322         v = BIT(4) | type << 2 | BIT(0); // WRITE | MMD-access-type | EXEC
 323         sw_w32(v, RTL931X_SMI_INDRT_ACCESS_CTRL_0);
 324
 325         do {
 326                 v = sw_r32(RTL931X_SMI_INDRT_ACCESS_CTRL_0);
 327         } while (v & BIT(0));
 328
 329         pr_debug("%s: port %d, regnum: %x, val: %x (err %d)\n", __func__, port, regnum, val, err);
 330         mutex_unlock(&smi_lock);
 331         return err;
 332 }
 333
 334 void rtl931x_print_matrix(void)
 335 {
 336         volatile u64 *ptr = RTL838X_SW_BASE + RTL839X_PORT_ISO_CTRL(0);
 337         int i;
 338
 339         for (i = 0; i < 52; i += 4)
 340                 pr_info("> %16llx %16llx %16llx %16llx\n",
 341                         ptr[i + 0], ptr[i + 1], ptr[i + 2], ptr[i + 3]);
 342         pr_info("CPU_PORT> %16llx\n", ptr[52]);
 343 }
 344
 345
 346 static int rtl931x_set_ageing_time(unsigned long msec)
 347 {
 348         int t = sw_r32(RTL931X_L2_AGE_CTRL);
 349
 350         t &= 0x1FFFFF;
 351         t = (t * 8) / 10;
 352         pr_debug("L2 AGING time: %d sec\n", t);
 353
 354         t = (msec / 100 + 7) / 8;
 355         t = t > 0x1FFFFF ? 0x1FFFFF : t;
 356         sw_w32_mask(0x1FFFFF, t, RTL931X_L2_AGE_CTRL);
 357         pr_debug("Dynamic aging for ports: %x\n", sw_r32(RTL931X_L2_PORT_AGE_CTRL));
 358         return 0;
 359 }
 360
 361 void rtl931x_vlan_port_pvidmode_set(int port, enum pbvlan_type type, enum pbvlan_mode mode)
 362 {
 363         if (type == PBVLAN_TYPE_INNER)
 364                 sw_w32_mask(0x3 << 12, mode << 12, RTL931X_VLAN_PORT_IGR_CTRL + (port << 2));
 365         else
 366                 sw_w32_mask(0x3 << 26, mode << 26, RTL931X_VLAN_PORT_IGR_CTRL + (port << 2));
 367 }
 368
 369 void rtl931x_vlan_port_pvid_set(int port, enum pbvlan_type type, int pvid)
 370 {
 371         if (type == PBVLAN_TYPE_INNER)
 372                 sw_w32_mask(0xfff, pvid, RTL931X_VLAN_PORT_IGR_CTRL + (port << 2));
 373         else
 374                 sw_w32_mask(0xfff << 14, pvid << 14, RTL931X_VLAN_PORT_IGR_CTRL + (port << 2));
 375 }
 376
 377 static void rtl931x_set_igr_filter(int port, enum igr_filter state)
 378 {
 379         sw_w32_mask(0x3 << ((port & 0xf)<<1), state << ((port & 0xf)<<1),
 380                     RTL931X_VLAN_PORT_IGR_FLTR + (((port >> 4) << 2)));
 381 }
 382
 383 static void rtl931x_set_egr_filter(int port,  enum egr_filter state)
 384 {
 385         sw_w32_mask(0x1 << (port % 0x20), state << (port % 0x20),
 386                     RTL931X_VLAN_PORT_EGR_FLTR + (((port >> 5) << 2)));
 387 }
 388
 389 const struct rtl838x_reg rtl931x_reg = {
 390         .mask_port_reg_be = rtl839x_mask_port_reg_be,
 391         .set_port_reg_be = rtl839x_set_port_reg_be,
 392         .get_port_reg_be = rtl839x_get_port_reg_be,
 393         .mask_port_reg_le = rtl839x_mask_port_reg_le,
 394         .set_port_reg_le = rtl839x_set_port_reg_le,
 395         .get_port_reg_le = rtl839x_get_port_reg_le,
 396         .stat_port_rst = RTL931X_STAT_PORT_RST,
 397         .stat_rst = RTL931X_STAT_RST,
 398         .stat_port_std_mib = 0,  // Not defined
 399         .l2_ctrl_0 = RTL931X_L2_CTRL,
 400         .l2_ctrl_1 = RTL931X_L2_AGE_CTRL,
 401         .l2_port_aging_out = RTL931X_L2_PORT_AGE_CTRL,
 402         // .smi_poll_ctrl does not exist
 403         .l2_tbl_flush_ctrl = RTL931X_L2_TBL_FLUSH_CTRL,
 404         .exec_tbl0_cmd = rtl931x_exec_tbl0_cmd,
 405         .exec_tbl1_cmd = rtl931x_exec_tbl1_cmd,
 406         .tbl_access_data_0 = rtl931x_tbl_access_data_0,
 407         .isr_glb_src = RTL931X_ISR_GLB_SRC,
 408         .isr_port_link_sts_chg = RTL931X_ISR_PORT_LINK_STS_CHG,
 409         .imr_port_link_sts_chg = RTL931X_IMR_PORT_LINK_STS_CHG,
 410         // imr_glb does not exist on RTL931X
 411         .vlan_tables_read = rtl931x_vlan_tables_read,
 412         .vlan_set_tagged = rtl931x_vlan_set_tagged,
 413         .vlan_set_untagged = rtl931x_vlan_set_untagged,
 414         .vlan_profile_dump = rtl931x_vlan_profile_dump,
 415         .stp_get = rtl931x_stp_get,
 416         .stp_set = rtl931x_stp_set,
 417         .mac_force_mode_ctrl = rtl931x_mac_force_mode_ctrl,
 418         .mac_port_ctrl = rtl931x_mac_port_ctrl,
 419         .l2_port_new_salrn = rtl931x_l2_port_new_salrn,
 420         .l2_port_new_sa_fwd = rtl931x_l2_port_new_sa_fwd,
 421         .mir_ctrl = RTL931X_MIR_CTRL,
 422         .mir_dpm = RTL931X_MIR_DPM_CTRL,
 423         .mir_spm = RTL931X_MIR_SPM_CTRL,
 424         .mac_link_sts = RTL931X_MAC_LINK_STS,
 425         .mac_link_dup_sts = RTL931X_MAC_LINK_DUP_STS,
 426         .mac_link_spd_sts = rtl931x_mac_link_spd_sts,
 427         .mac_rx_pause_sts = RTL931X_MAC_RX_PAUSE_STS,
 428         .mac_tx_pause_sts = RTL931X_MAC_TX_PAUSE_STS,
 429         .read_l2_entry_using_hash = rtl931x_read_l2_entry_using_hash,
 430         .read_cam = rtl931x_read_cam,
 431         .vlan_port_tag_sts_ctrl = RTL931X_VLAN_PORT_TAG_CTRL,
 432         .vlan_port_pvidmode_set = rtl931x_vlan_port_pvidmode_set,
 433         .vlan_port_pvid_set = rtl931x_vlan_port_pvid_set,
 434         .trk_mbr_ctr = rtl931x_trk_mbr_ctr,
 435         .set_vlan_igr_filter = rtl931x_set_igr_filter,
 436         .set_vlan_egr_filter = rtl931x_set_egr_filter,
 437 };
 438