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realtek: Fix Ethernet driver IRQ service routine for SMP
[openwrt/staging/ldir.git] / target / linux / realtek / files-5.10 / drivers / net / ethernet / rtl838x_eth.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * linux/drivers/net/ethernet/rtl838x_eth.c
4 * Copyright (C) 2020 B. Koblitz
5 */
6
7 #include <linux/dma-mapping.h>
8 #include <linux/etherdevice.h>
9 #include <linux/interrupt.h>
10 #include <linux/io.h>
11 #include <linux/platform_device.h>
12 #include <linux/sched.h>
13 #include <linux/slab.h>
14 #include <linux/of.h>
15 #include <linux/of_net.h>
16 #include <linux/of_mdio.h>
17 #include <linux/module.h>
18 #include <linux/phylink.h>
19 #include <linux/pkt_sched.h>
20 #include <net/dsa.h>
21 #include <net/switchdev.h>
22 #include <asm/cacheflush.h>
23
24 #include <asm/mach-rtl838x/mach-rtl83xx.h>
25 #include "rtl838x_eth.h"
26
27 extern struct rtl83xx_soc_info soc_info;
28
29 /*
30 * Maximum number of RX rings is 8 on RTL83XX and 32 on the 93XX
31 * The ring is assigned by switch based on packet/port priortity
32 * Maximum number of TX rings is 2, Ring 2 being the high priority
33 * ring on the RTL93xx SoCs. MAX_RXLEN gives the maximum length
34 * for an RX ring, MAX_ENTRIES the maximum number of entries
35 * available in total for all queues.
36 */
37 #define MAX_RXRINGS 32
38 #define MAX_RXLEN 300
39 #define MAX_ENTRIES (300 * 8)
40 #define TXRINGS 2
41 #define TXRINGLEN 160
42 #define NOTIFY_EVENTS 10
43 #define NOTIFY_BLOCKS 10
44 #define TX_EN 0x8
45 #define RX_EN 0x4
46 #define TX_EN_93XX 0x20
47 #define RX_EN_93XX 0x10
48 #define TX_DO 0x2
49 #define WRAP 0x2
50 #define MAX_PORTS 57
51 #define MAX_SMI_BUSSES 4
52
53 #define RING_BUFFER 1600
54
55 struct p_hdr {
56 uint8_t *buf;
57 uint16_t reserved;
58 uint16_t size; /* buffer size */
59 uint16_t offset;
60 uint16_t len; /* pkt len */
61 uint16_t cpu_tag[10];
62 } __packed __aligned(1);
63
64 struct n_event {
65 uint32_t type:2;
66 uint32_t fidVid:12;
67 uint64_t mac:48;
68 uint32_t slp:6;
69 uint32_t valid:1;
70 uint32_t reserved:27;
71 } __packed __aligned(1);
72
73 struct ring_b {
74 uint32_t rx_r[MAX_RXRINGS][MAX_RXLEN];
75 uint32_t tx_r[TXRINGS][TXRINGLEN];
76 struct p_hdr rx_header[MAX_RXRINGS][MAX_RXLEN];
77 struct p_hdr tx_header[TXRINGS][TXRINGLEN];
78 uint32_t c_rx[MAX_RXRINGS];
79 uint32_t c_tx[TXRINGS];
80 uint8_t tx_space[TXRINGS * TXRINGLEN * RING_BUFFER];
81 uint8_t *rx_space;
82 };
83
84 struct notify_block {
85 struct n_event events[NOTIFY_EVENTS];
86 };
87
88 struct notify_b {
89 struct notify_block blocks[NOTIFY_BLOCKS];
90 u32 reserved1[8];
91 u32 ring[NOTIFY_BLOCKS];
92 u32 reserved2[8];
93 };
94
95 static void rtl838x_create_tx_header(struct p_hdr *h, int dest_port, int prio)
96 {
97 prio &= 0x7;
98
99 if (dest_port > 0) {
100 // cpu_tag[0] is reserved on the RTL83XX SoCs
101 h->cpu_tag[1] = 0x0401; // BIT 10: RTL8380_CPU_TAG, BIT0: L2LEARNING on
102 h->cpu_tag[2] = 0x0200; // Set only AS_DPM, to enable DPM settings below
103 h->cpu_tag[3] = 0x0000;
104 h->cpu_tag[4] = BIT(dest_port) >> 16;
105 h->cpu_tag[5] = BIT(dest_port) & 0xffff;
106 // Set internal priority and AS_PRIO
107 if (prio >= 0)
108 h->cpu_tag[2] |= (prio | 0x8) << 12;
109 }
110 }
111
112 static void rtl839x_create_tx_header(struct p_hdr *h, int dest_port, int prio)
113 {
114 prio &= 0x7;
115
116 if (dest_port > 0) {
117 // cpu_tag[0] is reserved on the RTL83XX SoCs
118 h->cpu_tag[1] = 0x0100; // RTL8390_CPU_TAG marker
119 h->cpu_tag[2] = h->cpu_tag[3] = h->cpu_tag[4] = h->cpu_tag[5] = 0;
120 // h->cpu_tag[1] |= BIT(1) | BIT(0); // Bypass filter 1/2
121 if (dest_port >= 32) {
122 dest_port -= 32;
123 h->cpu_tag[2] = BIT(dest_port) >> 16;
124 h->cpu_tag[3] = BIT(dest_port) & 0xffff;
125 } else {
126 h->cpu_tag[4] = BIT(dest_port) >> 16;
127 h->cpu_tag[5] = BIT(dest_port) & 0xffff;
128 }
129 h->cpu_tag[2] |= BIT(5); // Enable destination port mask use
130 h->cpu_tag[2] |= BIT(8); // Enable L2 Learning
131 // Set internal priority and AS_PRIO
132 if (prio >= 0)
133 h->cpu_tag[1] |= prio | BIT(3);
134 }
135 }
136
137 static void rtl930x_create_tx_header(struct p_hdr *h, int dest_port, int prio)
138 {
139 h->cpu_tag[0] = 0x8000; // CPU tag marker
140 h->cpu_tag[1] = h->cpu_tag[2] = 0;
141 if (prio >= 0)
142 h->cpu_tag[2] = BIT(13) | prio << 8; // Enable and set Priority Queue
143 h->cpu_tag[3] = 0;
144 h->cpu_tag[4] = 0;
145 h->cpu_tag[5] = 0;
146 h->cpu_tag[6] = BIT(dest_port) >> 16;
147 h->cpu_tag[7] = BIT(dest_port) & 0xffff;
148 }
149
150 static void rtl931x_create_tx_header(struct p_hdr *h, int dest_port, int prio)
151 {
152 h->cpu_tag[0] = 0x8000; // CPU tag marker
153 h->cpu_tag[1] = h->cpu_tag[2] = 0;
154 if (prio >= 0)
155 h->cpu_tag[2] = BIT(13) | prio << 8; // Enable and set Priority Queue
156 h->cpu_tag[3] = 0;
157 h->cpu_tag[4] = h->cpu_tag[5] = h->cpu_tag[6] = h->cpu_tag[7] = 0;
158 if (dest_port >= 32) {
159 dest_port -= 32;
160 h->cpu_tag[4] = BIT(dest_port) >> 16;
161 h->cpu_tag[5] = BIT(dest_port) & 0xffff;
162 } else {
163 h->cpu_tag[6] = BIT(dest_port) >> 16;
164 h->cpu_tag[7] = BIT(dest_port) & 0xffff;
165 }
166 }
167
168 static void rtl93xx_header_vlan_set(struct p_hdr *h, int vlan)
169 {
170 h->cpu_tag[2] |= BIT(4); // Enable VLAN forwarding offload
171 h->cpu_tag[2] |= (vlan >> 8) & 0xf;
172 h->cpu_tag[3] |= (vlan & 0xff) << 8;
173 }
174
175 struct rtl838x_rx_q {
176 int id;
177 struct rtl838x_eth_priv *priv;
178 struct napi_struct napi;
179 };
180
181 struct rtl838x_eth_priv {
182 struct net_device *netdev;
183 struct platform_device *pdev;
184 void *membase;
185 spinlock_t lock;
186 struct mii_bus *mii_bus;
187 struct rtl838x_rx_q rx_qs[MAX_RXRINGS];
188 struct phylink *phylink;
189 struct phylink_config phylink_config;
190 u16 id;
191 u16 family_id;
192 const struct rtl838x_eth_reg *r;
193 u8 cpu_port;
194 u32 lastEvent;
195 u16 rxrings;
196 u16 rxringlen;
197 u8 smi_bus[MAX_PORTS];
198 u8 smi_addr[MAX_PORTS];
199 u32 sds_id[MAX_PORTS];
200 bool smi_bus_isc45[MAX_SMI_BUSSES];
201 bool phy_is_internal[MAX_PORTS];
202 };
203
204 extern int rtl838x_phy_init(struct rtl838x_eth_priv *priv);
205 extern int rtl838x_read_sds_phy(int phy_addr, int phy_reg);
206 extern int rtl839x_read_sds_phy(int phy_addr, int phy_reg);
207 extern int rtl839x_write_sds_phy(int phy_addr, int phy_reg, u16 v);
208 extern int rtl930x_read_sds_phy(int phy_addr, int page, int phy_reg);
209 extern int rtl930x_write_sds_phy(int phy_addr, int page, int phy_reg, u16 v);
210 extern int rtl931x_read_sds_phy(int phy_addr, int page, int phy_reg);
211 extern int rtl931x_write_sds_phy(int phy_addr, int page, int phy_reg, u16 v);
212 extern int rtl930x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val);
213 extern int rtl930x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val);
214 extern int rtl931x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val);
215 extern int rtl931x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val);
216
217 /*
218 * On the RTL93XX, the RTL93XX_DMA_IF_RX_RING_CNTR track the fill level of
219 * the rings. Writing x into these registers substracts x from its content.
220 * When the content reaches the ring size, the ASIC no longer adds
221 * packets to this receive queue.
222 */
223 void rtl838x_update_cntr(int r, int released)
224 {
225 // This feature is not available on RTL838x SoCs
226 }
227
228 void rtl839x_update_cntr(int r, int released)
229 {
230 // This feature is not available on RTL839x SoCs
231 }
232
233 void rtl930x_update_cntr(int r, int released)
234 {
235 int pos = (r % 3) * 10;
236 u32 reg = RTL930X_DMA_IF_RX_RING_CNTR + ((r / 3) << 2);
237 u32 v = sw_r32(reg);
238
239 v = (v >> pos) & 0x3ff;
240 pr_debug("RX: Work done %d, old value: %d, pos %d, reg %04x\n", released, v, pos, reg);
241 sw_w32_mask(0x3ff << pos, released << pos, reg);
242 sw_w32(v, reg);
243 }
244
245 void rtl931x_update_cntr(int r, int released)
246 {
247 int pos = (r % 3) * 10;
248 u32 reg = RTL931X_DMA_IF_RX_RING_CNTR + ((r / 3) << 2);
249 u32 v = sw_r32(reg);
250
251 v = (v >> pos) & 0x3ff;
252 sw_w32_mask(0x3ff << pos, released << pos, reg);
253 sw_w32(v, reg);
254 }
255
256 struct dsa_tag {
257 u8 reason;
258 u8 queue;
259 u16 port;
260 u8 l2_offloaded;
261 u8 prio;
262 bool crc_error;
263 };
264
265 bool rtl838x_decode_tag(struct p_hdr *h, struct dsa_tag *t)
266 {
267 t->reason = h->cpu_tag[3] & 0xf;
268 t->queue = (h->cpu_tag[0] & 0xe0) >> 5;
269 t->port = h->cpu_tag[1] & 0x1f;
270 t->crc_error = t->reason == 13;
271
272 pr_debug("Reason: %d\n", t->reason);
273 if (t->reason != 4) // NIC_RX_REASON_SPECIAL_TRAP
274 t->l2_offloaded = 1;
275 else
276 t->l2_offloaded = 0;
277
278 return t->l2_offloaded;
279 }
280
281 bool rtl839x_decode_tag(struct p_hdr *h, struct dsa_tag *t)
282 {
283 t->reason = h->cpu_tag[5] & 0x1f;
284 t->queue = (h->cpu_tag[3] & 0xe000) >> 13;
285 t->port = h->cpu_tag[1] & 0x3f;
286 t->crc_error = h->cpu_tag[3] & BIT(2);
287
288 pr_debug("Reason: %d\n", t->reason);
289 if ((t->reason >= 7 && t->reason <= 13) || // NIC_RX_REASON_RMA
290 (t->reason >= 23 && t->reason <= 25)) // NIC_RX_REASON_SPECIAL_TRAP
291 t->l2_offloaded = 0;
292 else
293 t->l2_offloaded = 1;
294
295 return t->l2_offloaded;
296 }
297
298 bool rtl930x_decode_tag(struct p_hdr *h, struct dsa_tag *t)
299 {
300 t->reason = h->cpu_tag[7] & 0x3f;
301 t->queue = (h->cpu_tag[2] >> 11) & 0x1f;
302 t->port = (h->cpu_tag[0] >> 8) & 0x1f;
303 t->crc_error = h->cpu_tag[1] & BIT(6);
304
305 pr_debug("Reason %d, port %d, queue %d\n", t->reason, t->port, t->queue);
306 if (t->reason >= 19 && t->reason <= 27)
307 t->l2_offloaded = 0;
308 else
309 t->l2_offloaded = 1;
310
311 return t->l2_offloaded;
312 }
313
314 bool rtl931x_decode_tag(struct p_hdr *h, struct dsa_tag *t)
315 {
316 t->reason = h->cpu_tag[7] & 0x3f;
317 t->queue = (h->cpu_tag[2] >> 11) & 0x1f;
318 t->port = (h->cpu_tag[0] >> 8) & 0x3f;
319 t->crc_error = h->cpu_tag[1] & BIT(6);
320
321 if (t->reason != 63)
322 pr_info("%s: Reason %d, port %d, queue %d\n", __func__, t->reason, t->port, t->queue);
323 if (t->reason >= 19 && t->reason <= 27) // NIC_RX_REASON_RMA
324 t->l2_offloaded = 0;
325 else
326 t->l2_offloaded = 1;
327
328 return t->l2_offloaded;
329 }
330
331 /*
332 * Discard the RX ring-buffers, called as part of the net-ISR
333 * when the buffer runs over
334 */
335 static void rtl838x_rb_cleanup(struct rtl838x_eth_priv *priv, int status)
336 {
337 int r;
338 u32 *last;
339 struct p_hdr *h;
340 struct ring_b *ring = priv->membase;
341
342 for (r = 0; r < priv->rxrings; r++) {
343 pr_debug("In %s working on r: %d\n", __func__, r);
344 last = (u32 *)KSEG1ADDR(sw_r32(priv->r->dma_if_rx_cur + r * 4));
345 do {
346 if ((ring->rx_r[r][ring->c_rx[r]] & 0x1))
347 break;
348 pr_debug("Got something: %d\n", ring->c_rx[r]);
349 h = &ring->rx_header[r][ring->c_rx[r]];
350 memset(h, 0, sizeof(struct p_hdr));
351 h->buf = (u8 *)KSEG1ADDR(ring->rx_space
352 + r * priv->rxringlen * RING_BUFFER
353 + ring->c_rx[r] * RING_BUFFER);
354 h->size = RING_BUFFER;
355 /* make sure the header is visible to the ASIC */
356 mb();
357
358 ring->rx_r[r][ring->c_rx[r]] = KSEG1ADDR(h) | 0x1
359 | (ring->c_rx[r] == (priv->rxringlen - 1) ? WRAP : 0x1);
360 ring->c_rx[r] = (ring->c_rx[r] + 1) % priv->rxringlen;
361 } while (&ring->rx_r[r][ring->c_rx[r]] != last);
362 }
363 }
364
365 struct fdb_update_work {
366 struct work_struct work;
367 struct net_device *ndev;
368 u64 macs[NOTIFY_EVENTS + 1];
369 };
370
371 void rtl838x_fdb_sync(struct work_struct *work)
372 {
373 const struct fdb_update_work *uw =
374 container_of(work, struct fdb_update_work, work);
375 struct switchdev_notifier_fdb_info info;
376 u8 addr[ETH_ALEN];
377 int i = 0;
378 int action;
379
380 while (uw->macs[i]) {
381 action = (uw->macs[i] & (1ULL << 63)) ? SWITCHDEV_FDB_ADD_TO_BRIDGE
382 : SWITCHDEV_FDB_DEL_TO_BRIDGE;
383 u64_to_ether_addr(uw->macs[i] & 0xffffffffffffULL, addr);
384 info.addr = &addr[0];
385 info.vid = 0;
386 info.offloaded = 1;
387 pr_debug("FDB entry %d: %llx, action %d\n", i, uw->macs[0], action);
388 call_switchdev_notifiers(action, uw->ndev, &info.info, NULL);
389 i++;
390 }
391 kfree(work);
392 }
393
394 static void rtl839x_l2_notification_handler(struct rtl838x_eth_priv *priv)
395 {
396 struct notify_b *nb = priv->membase + sizeof(struct ring_b);
397 u32 e = priv->lastEvent;
398 struct n_event *event;
399 int i;
400 u64 mac;
401 struct fdb_update_work *w;
402
403 while (!(nb->ring[e] & 1)) {
404 w = kzalloc(sizeof(*w), GFP_ATOMIC);
405 if (!w) {
406 pr_err("Out of memory: %s", __func__);
407 return;
408 }
409 INIT_WORK(&w->work, rtl838x_fdb_sync);
410
411 for (i = 0; i < NOTIFY_EVENTS; i++) {
412 event = &nb->blocks[e].events[i];
413 if (!event->valid)
414 continue;
415 mac = event->mac;
416 if (event->type)
417 mac |= 1ULL << 63;
418 w->ndev = priv->netdev;
419 w->macs[i] = mac;
420 }
421
422 /* Hand the ring entry back to the switch */
423 nb->ring[e] = nb->ring[e] | 1;
424 e = (e + 1) % NOTIFY_BLOCKS;
425
426 w->macs[i] = 0ULL;
427 schedule_work(&w->work);
428 }
429 priv->lastEvent = e;
430 }
431
432 static irqreturn_t rtl83xx_net_irq(int irq, void *dev_id)
433 {
434 struct net_device *dev = dev_id;
435 struct rtl838x_eth_priv *priv = netdev_priv(dev);
436 u32 status = sw_r32(priv->r->dma_if_intr_sts);
437 int i;
438
439 pr_debug("IRQ: %08x\n", status);
440
441 /* Ignore TX interrupt */
442 if ((status & 0xf0000)) {
443 /* Clear ISR */
444 sw_w32(0x000f0000, priv->r->dma_if_intr_sts);
445 }
446
447 /* RX interrupt */
448 if (status & 0x0ff00) {
449 /* ACK and disable RX interrupt for this ring */
450 sw_w32_mask(0xff00 & status, 0, priv->r->dma_if_intr_msk);
451 sw_w32(0x0000ff00 & status, priv->r->dma_if_intr_sts);
452 for (i = 0; i < priv->rxrings; i++) {
453 if (status & BIT(i + 8)) {
454 pr_debug("Scheduling queue: %d\n", i);
455 napi_schedule(&priv->rx_qs[i].napi);
456 }
457 }
458 }
459
460 /* RX buffer overrun */
461 if (status & 0x000ff) {
462 pr_debug("RX buffer overrun: status %x, mask: %x\n",
463 status, sw_r32(priv->r->dma_if_intr_msk));
464 sw_w32(status, priv->r->dma_if_intr_sts);
465 rtl838x_rb_cleanup(priv, status & 0xff);
466 }
467
468 if (priv->family_id == RTL8390_FAMILY_ID && status & 0x00100000) {
469 sw_w32(0x00100000, priv->r->dma_if_intr_sts);
470 rtl839x_l2_notification_handler(priv);
471 }
472
473 if (priv->family_id == RTL8390_FAMILY_ID && status & 0x00200000) {
474 sw_w32(0x00200000, priv->r->dma_if_intr_sts);
475 rtl839x_l2_notification_handler(priv);
476 }
477
478 if (priv->family_id == RTL8390_FAMILY_ID && status & 0x00400000) {
479 sw_w32(0x00400000, priv->r->dma_if_intr_sts);
480 rtl839x_l2_notification_handler(priv);
481 }
482
483 return IRQ_HANDLED;
484 }
485
486 static irqreturn_t rtl93xx_net_irq(int irq, void *dev_id)
487 {
488 struct net_device *dev = dev_id;
489 struct rtl838x_eth_priv *priv = netdev_priv(dev);
490 u32 status_rx_r = sw_r32(priv->r->dma_if_intr_rx_runout_sts);
491 u32 status_rx = sw_r32(priv->r->dma_if_intr_rx_done_sts);
492 u32 status_tx = sw_r32(priv->r->dma_if_intr_tx_done_sts);
493 int i;
494
495 pr_debug("In %s, status_tx: %08x, status_rx: %08x, status_rx_r: %08x\n",
496 __func__, status_tx, status_rx, status_rx_r);
497
498 /* Ignore TX interrupt */
499 if (status_tx) {
500 /* Clear ISR */
501 pr_debug("TX done\n");
502 sw_w32(status_tx, priv->r->dma_if_intr_tx_done_sts);
503 }
504
505 /* RX interrupt */
506 if (status_rx) {
507 pr_debug("RX IRQ\n");
508 /* ACK and disable RX interrupt for given rings */
509 sw_w32(status_rx, priv->r->dma_if_intr_rx_done_sts);
510 sw_w32_mask(status_rx, 0, priv->r->dma_if_intr_rx_done_msk);
511 for (i = 0; i < priv->rxrings; i++) {
512 if (status_rx & BIT(i)) {
513 pr_debug("Scheduling queue: %d\n", i);
514 napi_schedule(&priv->rx_qs[i].napi);
515 }
516 }
517 }
518
519 /* RX buffer overrun */
520 if (status_rx_r) {
521 pr_debug("RX buffer overrun: status %x, mask: %x\n",
522 status_rx_r, sw_r32(priv->r->dma_if_intr_rx_runout_msk));
523 sw_w32(status_rx_r, priv->r->dma_if_intr_rx_runout_sts);
524 rtl838x_rb_cleanup(priv, status_rx_r);
525 }
526
527 return IRQ_HANDLED;
528 }
529
530 static const struct rtl838x_eth_reg rtl838x_reg = {
531 .net_irq = rtl83xx_net_irq,
532 .mac_port_ctrl = rtl838x_mac_port_ctrl,
533 .dma_if_intr_sts = RTL838X_DMA_IF_INTR_STS,
534 .dma_if_intr_msk = RTL838X_DMA_IF_INTR_MSK,
535 .dma_if_ctrl = RTL838X_DMA_IF_CTRL,
536 .mac_force_mode_ctrl = RTL838X_MAC_FORCE_MODE_CTRL,
537 .dma_rx_base = RTL838X_DMA_RX_BASE,
538 .dma_tx_base = RTL838X_DMA_TX_BASE,
539 .dma_if_rx_ring_size = rtl838x_dma_if_rx_ring_size,
540 .dma_if_rx_ring_cntr = rtl838x_dma_if_rx_ring_cntr,
541 .dma_if_rx_cur = RTL838X_DMA_IF_RX_CUR,
542 .rst_glb_ctrl = RTL838X_RST_GLB_CTRL_0,
543 .get_mac_link_sts = rtl838x_get_mac_link_sts,
544 .get_mac_link_dup_sts = rtl838x_get_mac_link_dup_sts,
545 .get_mac_link_spd_sts = rtl838x_get_mac_link_spd_sts,
546 .get_mac_rx_pause_sts = rtl838x_get_mac_rx_pause_sts,
547 .get_mac_tx_pause_sts = rtl838x_get_mac_tx_pause_sts,
548 .mac = RTL838X_MAC,
549 .l2_tbl_flush_ctrl = RTL838X_L2_TBL_FLUSH_CTRL,
550 .update_cntr = rtl838x_update_cntr,
551 .create_tx_header = rtl838x_create_tx_header,
552 .decode_tag = rtl838x_decode_tag,
553 };
554
555 static const struct rtl838x_eth_reg rtl839x_reg = {
556 .net_irq = rtl83xx_net_irq,
557 .mac_port_ctrl = rtl839x_mac_port_ctrl,
558 .dma_if_intr_sts = RTL839X_DMA_IF_INTR_STS,
559 .dma_if_intr_msk = RTL839X_DMA_IF_INTR_MSK,
560 .dma_if_ctrl = RTL839X_DMA_IF_CTRL,
561 .mac_force_mode_ctrl = RTL839X_MAC_FORCE_MODE_CTRL,
562 .dma_rx_base = RTL839X_DMA_RX_BASE,
563 .dma_tx_base = RTL839X_DMA_TX_BASE,
564 .dma_if_rx_ring_size = rtl839x_dma_if_rx_ring_size,
565 .dma_if_rx_ring_cntr = rtl839x_dma_if_rx_ring_cntr,
566 .dma_if_rx_cur = RTL839X_DMA_IF_RX_CUR,
567 .rst_glb_ctrl = RTL839X_RST_GLB_CTRL,
568 .get_mac_link_sts = rtl839x_get_mac_link_sts,
569 .get_mac_link_dup_sts = rtl839x_get_mac_link_dup_sts,
570 .get_mac_link_spd_sts = rtl839x_get_mac_link_spd_sts,
571 .get_mac_rx_pause_sts = rtl839x_get_mac_rx_pause_sts,
572 .get_mac_tx_pause_sts = rtl839x_get_mac_tx_pause_sts,
573 .mac = RTL839X_MAC,
574 .l2_tbl_flush_ctrl = RTL839X_L2_TBL_FLUSH_CTRL,
575 .update_cntr = rtl839x_update_cntr,
576 .create_tx_header = rtl839x_create_tx_header,
577 .decode_tag = rtl839x_decode_tag,
578 };
579
580 static const struct rtl838x_eth_reg rtl930x_reg = {
581 .net_irq = rtl93xx_net_irq,
582 .mac_port_ctrl = rtl930x_mac_port_ctrl,
583 .dma_if_intr_rx_runout_sts = RTL930X_DMA_IF_INTR_RX_RUNOUT_STS,
584 .dma_if_intr_rx_done_sts = RTL930X_DMA_IF_INTR_RX_DONE_STS,
585 .dma_if_intr_tx_done_sts = RTL930X_DMA_IF_INTR_TX_DONE_STS,
586 .dma_if_intr_rx_runout_msk = RTL930X_DMA_IF_INTR_RX_RUNOUT_MSK,
587 .dma_if_intr_rx_done_msk = RTL930X_DMA_IF_INTR_RX_DONE_MSK,
588 .dma_if_intr_tx_done_msk = RTL930X_DMA_IF_INTR_TX_DONE_MSK,
589 .l2_ntfy_if_intr_sts = RTL930X_L2_NTFY_IF_INTR_STS,
590 .l2_ntfy_if_intr_msk = RTL930X_L2_NTFY_IF_INTR_MSK,
591 .dma_if_ctrl = RTL930X_DMA_IF_CTRL,
592 .mac_force_mode_ctrl = RTL930X_MAC_FORCE_MODE_CTRL,
593 .dma_rx_base = RTL930X_DMA_RX_BASE,
594 .dma_tx_base = RTL930X_DMA_TX_BASE,
595 .dma_if_rx_ring_size = rtl930x_dma_if_rx_ring_size,
596 .dma_if_rx_ring_cntr = rtl930x_dma_if_rx_ring_cntr,
597 .dma_if_rx_cur = RTL930X_DMA_IF_RX_CUR,
598 .rst_glb_ctrl = RTL930X_RST_GLB_CTRL_0,
599 .get_mac_link_sts = rtl930x_get_mac_link_sts,
600 .get_mac_link_dup_sts = rtl930x_get_mac_link_dup_sts,
601 .get_mac_link_spd_sts = rtl930x_get_mac_link_spd_sts,
602 .get_mac_rx_pause_sts = rtl930x_get_mac_rx_pause_sts,
603 .get_mac_tx_pause_sts = rtl930x_get_mac_tx_pause_sts,
604 .mac = RTL930X_MAC_L2_ADDR_CTRL,
605 .l2_tbl_flush_ctrl = RTL930X_L2_TBL_FLUSH_CTRL,
606 .update_cntr = rtl930x_update_cntr,
607 .create_tx_header = rtl930x_create_tx_header,
608 .decode_tag = rtl930x_decode_tag,
609 };
610
611 static const struct rtl838x_eth_reg rtl931x_reg = {
612 .net_irq = rtl93xx_net_irq,
613 .mac_port_ctrl = rtl931x_mac_port_ctrl,
614 .dma_if_intr_rx_runout_sts = RTL931X_DMA_IF_INTR_RX_RUNOUT_STS,
615 .dma_if_intr_rx_done_sts = RTL931X_DMA_IF_INTR_RX_DONE_STS,
616 .dma_if_intr_tx_done_sts = RTL931X_DMA_IF_INTR_TX_DONE_STS,
617 .dma_if_intr_rx_runout_msk = RTL931X_DMA_IF_INTR_RX_RUNOUT_MSK,
618 .dma_if_intr_rx_done_msk = RTL931X_DMA_IF_INTR_RX_DONE_MSK,
619 .dma_if_intr_tx_done_msk = RTL931X_DMA_IF_INTR_TX_DONE_MSK,
620 .l2_ntfy_if_intr_sts = RTL931X_L2_NTFY_IF_INTR_STS,
621 .l2_ntfy_if_intr_msk = RTL931X_L2_NTFY_IF_INTR_MSK,
622 .dma_if_ctrl = RTL931X_DMA_IF_CTRL,
623 .mac_force_mode_ctrl = RTL931X_MAC_FORCE_MODE_CTRL,
624 .dma_rx_base = RTL931X_DMA_RX_BASE,
625 .dma_tx_base = RTL931X_DMA_TX_BASE,
626 .dma_if_rx_ring_size = rtl931x_dma_if_rx_ring_size,
627 .dma_if_rx_ring_cntr = rtl931x_dma_if_rx_ring_cntr,
628 .dma_if_rx_cur = RTL931X_DMA_IF_RX_CUR,
629 .rst_glb_ctrl = RTL931X_RST_GLB_CTRL,
630 .get_mac_link_sts = rtl931x_get_mac_link_sts,
631 .get_mac_link_dup_sts = rtl931x_get_mac_link_dup_sts,
632 .get_mac_link_spd_sts = rtl931x_get_mac_link_spd_sts,
633 .get_mac_rx_pause_sts = rtl931x_get_mac_rx_pause_sts,
634 .get_mac_tx_pause_sts = rtl931x_get_mac_tx_pause_sts,
635 .mac = RTL931X_MAC_L2_ADDR_CTRL,
636 .l2_tbl_flush_ctrl = RTL931X_L2_TBL_FLUSH_CTRL,
637 .update_cntr = rtl931x_update_cntr,
638 .create_tx_header = rtl931x_create_tx_header,
639 .decode_tag = rtl931x_decode_tag,
640 };
641
642 static void rtl838x_hw_reset(struct rtl838x_eth_priv *priv)
643 {
644 u32 int_saved, nbuf;
645 u32 reset_mask;
646 int i, pos;
647
648 pr_info("RESETTING %x, CPU_PORT %d\n", priv->family_id, priv->cpu_port);
649 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(priv->cpu_port));
650 mdelay(100);
651
652 /* Disable and clear interrupts */
653 if (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID) {
654 sw_w32(0x00000000, priv->r->dma_if_intr_rx_runout_msk);
655 sw_w32(0xffffffff, priv->r->dma_if_intr_rx_runout_sts);
656 sw_w32(0x00000000, priv->r->dma_if_intr_rx_done_msk);
657 sw_w32(0xffffffff, priv->r->dma_if_intr_rx_done_sts);
658 sw_w32(0x00000000, priv->r->dma_if_intr_tx_done_msk);
659 sw_w32(0x0000000f, priv->r->dma_if_intr_tx_done_sts);
660 } else {
661 sw_w32(0x00000000, priv->r->dma_if_intr_msk);
662 sw_w32(0xffffffff, priv->r->dma_if_intr_sts);
663 }
664
665 if (priv->family_id == RTL8390_FAMILY_ID) {
666 /* Preserve L2 notification and NBUF settings */
667 int_saved = sw_r32(priv->r->dma_if_intr_msk);
668 nbuf = sw_r32(RTL839X_DMA_IF_NBUF_BASE_DESC_ADDR_CTRL);
669
670 /* Disable link change interrupt on RTL839x */
671 sw_w32(0, RTL839X_IMR_PORT_LINK_STS_CHG);
672 sw_w32(0, RTL839X_IMR_PORT_LINK_STS_CHG + 4);
673
674 sw_w32(0x00000000, priv->r->dma_if_intr_msk);
675 sw_w32(0xffffffff, priv->r->dma_if_intr_sts);
676 }
677
678 /* Reset NIC (SW_NIC_RST) and queues (SW_Q_RST) */
679 if (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID)
680 reset_mask = 0x6;
681 else
682 reset_mask = 0xc;
683
684 sw_w32(reset_mask, priv->r->rst_glb_ctrl);
685
686 do { /* Wait for reset of NIC and Queues done */
687 udelay(20);
688 } while (sw_r32(priv->r->rst_glb_ctrl) & reset_mask);
689 mdelay(100);
690
691 /* Setup Head of Line */
692 if (priv->family_id == RTL8380_FAMILY_ID)
693 sw_w32(0, RTL838X_DMA_IF_RX_RING_SIZE); // Disabled on RTL8380
694 if (priv->family_id == RTL8390_FAMILY_ID)
695 sw_w32(0xffffffff, RTL839X_DMA_IF_RX_RING_CNTR);
696 if (priv->family_id == RTL9300_FAMILY_ID) {
697 for (i = 0; i < priv->rxrings; i++) {
698 pos = (i % 3) * 10;
699 sw_w32_mask(0x3ff << pos, 0, priv->r->dma_if_rx_ring_size(i));
700 sw_w32_mask(0x3ff << pos, priv->rxringlen,
701 priv->r->dma_if_rx_ring_cntr(i));
702 }
703 }
704
705 /* Re-enable link change interrupt */
706 if (priv->family_id == RTL8390_FAMILY_ID) {
707 sw_w32(0xffffffff, RTL839X_ISR_PORT_LINK_STS_CHG);
708 sw_w32(0xffffffff, RTL839X_ISR_PORT_LINK_STS_CHG + 4);
709 sw_w32(0xffffffff, RTL839X_IMR_PORT_LINK_STS_CHG);
710 sw_w32(0xffffffff, RTL839X_IMR_PORT_LINK_STS_CHG + 4);
711
712 /* Restore notification settings: on RTL838x these bits are null */
713 sw_w32_mask(7 << 20, int_saved & (7 << 20), priv->r->dma_if_intr_msk);
714 sw_w32(nbuf, RTL839X_DMA_IF_NBUF_BASE_DESC_ADDR_CTRL);
715 }
716 }
717
718 static void rtl838x_hw_ring_setup(struct rtl838x_eth_priv *priv)
719 {
720 int i;
721 struct ring_b *ring = priv->membase;
722
723 for (i = 0; i < priv->rxrings; i++)
724 sw_w32(KSEG1ADDR(&ring->rx_r[i]), priv->r->dma_rx_base + i * 4);
725
726 for (i = 0; i < TXRINGS; i++)
727 sw_w32(KSEG1ADDR(&ring->tx_r[i]), priv->r->dma_tx_base + i * 4);
728 }
729
730 static void rtl838x_hw_en_rxtx(struct rtl838x_eth_priv *priv)
731 {
732 /* Disable Head of Line features for all RX rings */
733 sw_w32(0xffffffff, priv->r->dma_if_rx_ring_size(0));
734
735 /* Truncate RX buffer to 0x640 (1600) bytes, pad TX */
736 sw_w32(0x06400020, priv->r->dma_if_ctrl);
737
738 /* Enable RX done, RX overflow and TX done interrupts */
739 sw_w32(0xfffff, priv->r->dma_if_intr_msk);
740
741 /* Enable DMA, engine expects empty FCS field */
742 sw_w32_mask(0, RX_EN | TX_EN, priv->r->dma_if_ctrl);
743
744 /* Restart TX/RX to CPU port */
745 sw_w32_mask(0x0, 0x3, priv->r->mac_port_ctrl(priv->cpu_port));
746 /* Set Speed, duplex, flow control
747 * FORCE_EN | LINK_EN | NWAY_EN | DUP_SEL
748 * | SPD_SEL = 0b10 | FORCE_FC_EN | PHY_MASTER_SLV_MANUAL_EN
749 * | MEDIA_SEL
750 */
751 sw_w32(0x6192F, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
752
753 /* Enable CRC checks on CPU-port */
754 sw_w32_mask(0, BIT(3), priv->r->mac_port_ctrl(priv->cpu_port));
755 }
756
757 static void rtl839x_hw_en_rxtx(struct rtl838x_eth_priv *priv)
758 {
759 /* Setup CPU-Port: RX Buffer */
760 sw_w32(0x0000c808, priv->r->dma_if_ctrl);
761
762 /* Enable Notify, RX done, RX overflow and TX done interrupts */
763 sw_w32(0x007fffff, priv->r->dma_if_intr_msk); // Notify IRQ!
764
765 /* Enable DMA */
766 sw_w32_mask(0, RX_EN | TX_EN, priv->r->dma_if_ctrl);
767
768 /* Restart TX/RX to CPU port, enable CRC checking */
769 sw_w32_mask(0x0, 0x3 | BIT(3), priv->r->mac_port_ctrl(priv->cpu_port));
770
771 /* CPU port joins Lookup Miss Flooding Portmask */
772 // TODO: The code below should also work for the RTL838x
773 sw_w32(0x28000, RTL839X_TBL_ACCESS_L2_CTRL);
774 sw_w32_mask(0, 0x80000000, RTL839X_TBL_ACCESS_L2_DATA(0));
775 sw_w32(0x38000, RTL839X_TBL_ACCESS_L2_CTRL);
776
777 /* Force CPU port link up */
778 sw_w32_mask(0, 3, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
779 }
780
781 static void rtl93xx_hw_en_rxtx(struct rtl838x_eth_priv *priv)
782 {
783 int i, pos;
784 u32 v;
785
786 /* Setup CPU-Port: RX Buffer truncated at 1600 Bytes */
787 sw_w32(0x06400040, priv->r->dma_if_ctrl);
788
789 for (i = 0; i < priv->rxrings; i++) {
790 pos = (i % 3) * 10;
791 sw_w32_mask(0x3ff << pos, priv->rxringlen << pos, priv->r->dma_if_rx_ring_size(i));
792
793 // Some SoCs have issues with missing underflow protection
794 v = (sw_r32(priv->r->dma_if_rx_ring_cntr(i)) >> pos) & 0x3ff;
795 sw_w32_mask(0x3ff << pos, v, priv->r->dma_if_rx_ring_cntr(i));
796 }
797
798 /* Enable Notify, RX done, RX overflow and TX done interrupts */
799 sw_w32(0xffffffff, priv->r->dma_if_intr_rx_runout_msk);
800 sw_w32(0xffffffff, priv->r->dma_if_intr_rx_done_msk);
801 sw_w32(0x0000000f, priv->r->dma_if_intr_tx_done_msk);
802
803 /* Enable DMA */
804 sw_w32_mask(0, RX_EN_93XX | TX_EN_93XX, priv->r->dma_if_ctrl);
805
806 /* Restart TX/RX to CPU port, enable CRC checking */
807 sw_w32_mask(0x0, 0x3 | BIT(4), priv->r->mac_port_ctrl(priv->cpu_port));
808
809 sw_w32_mask(0, BIT(priv->cpu_port), RTL930X_L2_UNKN_UC_FLD_PMSK);
810 sw_w32(0x217, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
811 }
812
813 static void rtl838x_setup_ring_buffer(struct rtl838x_eth_priv *priv, struct ring_b *ring)
814 {
815 int i, j;
816
817 struct p_hdr *h;
818
819 for (i = 0; i < priv->rxrings; i++) {
820 for (j = 0; j < priv->rxringlen; j++) {
821 h = &ring->rx_header[i][j];
822 memset(h, 0, sizeof(struct p_hdr));
823 h->buf = (u8 *)KSEG1ADDR(ring->rx_space
824 + i * priv->rxringlen * RING_BUFFER
825 + j * RING_BUFFER);
826 h->size = RING_BUFFER;
827 /* All rings owned by switch, last one wraps */
828 ring->rx_r[i][j] = KSEG1ADDR(h) | 1
829 | (j == (priv->rxringlen - 1) ? WRAP : 0);
830 }
831 ring->c_rx[i] = 0;
832 }
833
834 for (i = 0; i < TXRINGS; i++) {
835 for (j = 0; j < TXRINGLEN; j++) {
836 h = &ring->tx_header[i][j];
837 memset(h, 0, sizeof(struct p_hdr));
838 h->buf = (u8 *)KSEG1ADDR(ring->tx_space
839 + i * TXRINGLEN * RING_BUFFER
840 + j * RING_BUFFER);
841 h->size = RING_BUFFER;
842 ring->tx_r[i][j] = KSEG1ADDR(&ring->tx_header[i][j]);
843 }
844 /* Last header is wrapping around */
845 ring->tx_r[i][j-1] |= WRAP;
846 ring->c_tx[i] = 0;
847 }
848 }
849
850 static void rtl839x_setup_notify_ring_buffer(struct rtl838x_eth_priv *priv)
851 {
852 int i;
853 struct notify_b *b = priv->membase + sizeof(struct ring_b);
854
855 for (i = 0; i < NOTIFY_BLOCKS; i++)
856 b->ring[i] = KSEG1ADDR(&b->blocks[i]) | 1 | (i == (NOTIFY_BLOCKS - 1) ? WRAP : 0);
857
858 sw_w32((u32) b->ring, RTL839X_DMA_IF_NBUF_BASE_DESC_ADDR_CTRL);
859 sw_w32_mask(0x3ff << 2, 100 << 2, RTL839X_L2_NOTIFICATION_CTRL);
860
861 /* Setup notification events */
862 sw_w32_mask(0, 1 << 14, RTL839X_L2_CTRL_0); // RTL8390_L2_CTRL_0_FLUSH_NOTIFY_EN
863 sw_w32_mask(0, 1 << 12, RTL839X_L2_NOTIFICATION_CTRL); // SUSPEND_NOTIFICATION_EN
864
865 /* Enable Notification */
866 sw_w32_mask(0, 1 << 0, RTL839X_L2_NOTIFICATION_CTRL);
867 priv->lastEvent = 0;
868 }
869
870 static int rtl838x_eth_open(struct net_device *ndev)
871 {
872 unsigned long flags;
873 struct rtl838x_eth_priv *priv = netdev_priv(ndev);
874 struct ring_b *ring = priv->membase;
875 int i, err;
876
877 pr_debug("%s called: RX rings %d(length %d), TX rings %d(length %d)\n",
878 __func__, priv->rxrings, priv->rxringlen, TXRINGS, TXRINGLEN);
879
880 spin_lock_irqsave(&priv->lock, flags);
881 rtl838x_hw_reset(priv);
882 rtl838x_setup_ring_buffer(priv, ring);
883 if (priv->family_id == RTL8390_FAMILY_ID) {
884 rtl839x_setup_notify_ring_buffer(priv);
885 /* Make sure the ring structure is visible to the ASIC */
886 mb();
887 flush_cache_all();
888 }
889
890 rtl838x_hw_ring_setup(priv);
891 err = request_irq(ndev->irq, priv->r->net_irq, IRQF_SHARED, ndev->name, ndev);
892 if (err) {
893 netdev_err(ndev, "%s: could not acquire interrupt: %d\n",
894 __func__, err);
895 return err;
896 }
897 phylink_start(priv->phylink);
898
899 for (i = 0; i < priv->rxrings; i++)
900 napi_enable(&priv->rx_qs[i].napi);
901
902 switch (priv->family_id) {
903 case RTL8380_FAMILY_ID:
904 rtl838x_hw_en_rxtx(priv);
905 /* Trap IGMP/MLD traffic to CPU-Port */
906 sw_w32(0x3, RTL838X_SPCL_TRAP_IGMP_CTRL);
907 /* Flush learned FDB entries on link down of a port */
908 sw_w32_mask(0, BIT(7), RTL838X_L2_CTRL_0);
909 break;
910
911 case RTL8390_FAMILY_ID:
912 rtl839x_hw_en_rxtx(priv);
913 // Trap MLD and IGMP messages to CPU_PORT
914 sw_w32(0x3, RTL839X_SPCL_TRAP_IGMP_CTRL);
915 /* Flush learned FDB entries on link down of a port */
916 sw_w32_mask(0, BIT(7), RTL839X_L2_CTRL_0);
917 break;
918
919 case RTL9300_FAMILY_ID:
920 rtl93xx_hw_en_rxtx(priv);
921 /* Flush learned FDB entries on link down of a port */
922 sw_w32_mask(0, BIT(7), RTL930X_L2_CTRL);
923 // Trap MLD and IGMP messages to CPU_PORT
924 sw_w32((0x2 << 3) | 0x2, RTL930X_VLAN_APP_PKT_CTRL);
925 break;
926
927 case RTL9310_FAMILY_ID:
928 rtl93xx_hw_en_rxtx(priv);
929 break;
930 }
931
932 netif_tx_start_all_queues(ndev);
933
934 spin_unlock_irqrestore(&priv->lock, flags);
935
936 return 0;
937 }
938
939 static void rtl838x_hw_stop(struct rtl838x_eth_priv *priv)
940 {
941 u32 force_mac = priv->family_id == RTL8380_FAMILY_ID ? 0x6192C : 0x75;
942 u32 clear_irq = priv->family_id == RTL8380_FAMILY_ID ? 0x000fffff : 0x007fffff;
943 int i;
944
945 // Disable RX/TX from/to CPU-port
946 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(priv->cpu_port));
947
948 /* Disable traffic */
949 if (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID)
950 sw_w32_mask(RX_EN_93XX | TX_EN_93XX, 0, priv->r->dma_if_ctrl);
951 else
952 sw_w32_mask(RX_EN | TX_EN, 0, priv->r->dma_if_ctrl);
953 mdelay(200); // Test, whether this is needed
954
955 /* Block all ports */
956 if (priv->family_id == RTL8380_FAMILY_ID) {
957 sw_w32(0x03000000, RTL838X_TBL_ACCESS_DATA_0(0));
958 sw_w32(0x00000000, RTL838X_TBL_ACCESS_DATA_0(1));
959 sw_w32(1 << 15 | 2 << 12, RTL838X_TBL_ACCESS_CTRL_0);
960 }
961
962 /* Flush L2 address cache */
963 if (priv->family_id == RTL8380_FAMILY_ID) {
964 for (i = 0; i <= priv->cpu_port; i++) {
965 sw_w32(1 << 26 | 1 << 23 | i << 5, priv->r->l2_tbl_flush_ctrl);
966 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & (1 << 26));
967 }
968 } else if (priv->family_id == RTL8390_FAMILY_ID) {
969 for (i = 0; i <= priv->cpu_port; i++) {
970 sw_w32(1 << 28 | 1 << 25 | i << 5, priv->r->l2_tbl_flush_ctrl);
971 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & (1 << 28));
972 }
973 }
974 // TODO: L2 flush register is 64 bit on RTL931X and 930X
975
976 /* CPU-Port: Link down */
977 if (priv->family_id == RTL8380_FAMILY_ID || priv->family_id == RTL8390_FAMILY_ID)
978 sw_w32(force_mac, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
979 else
980 sw_w32_mask(0x3, 0, priv->r->mac_force_mode_ctrl + priv->cpu_port *4);
981 mdelay(100);
982
983 /* Disable all TX/RX interrupts */
984 if (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID) {
985 sw_w32(0x00000000, priv->r->dma_if_intr_rx_runout_msk);
986 sw_w32(0xffffffff, priv->r->dma_if_intr_rx_runout_sts);
987 sw_w32(0x00000000, priv->r->dma_if_intr_rx_done_msk);
988 sw_w32(0xffffffff, priv->r->dma_if_intr_rx_done_sts);
989 sw_w32(0x00000000, priv->r->dma_if_intr_tx_done_msk);
990 sw_w32(0x0000000f, priv->r->dma_if_intr_tx_done_sts);
991 } else {
992 sw_w32(0x00000000, priv->r->dma_if_intr_msk);
993 sw_w32(clear_irq, priv->r->dma_if_intr_sts);
994 }
995
996 /* Disable TX/RX DMA */
997 sw_w32(0x00000000, priv->r->dma_if_ctrl);
998 mdelay(200);
999 }
1000
1001 static int rtl838x_eth_stop(struct net_device *ndev)
1002 {
1003 unsigned long flags;
1004 int i;
1005 struct rtl838x_eth_priv *priv = netdev_priv(ndev);
1006
1007 pr_info("in %s\n", __func__);
1008
1009 spin_lock_irqsave(&priv->lock, flags);
1010 phylink_stop(priv->phylink);
1011 rtl838x_hw_stop(priv);
1012 free_irq(ndev->irq, ndev);
1013
1014 for (i = 0; i < priv->rxrings; i++)
1015 napi_disable(&priv->rx_qs[i].napi);
1016
1017 netif_tx_stop_all_queues(ndev);
1018
1019 spin_unlock_irqrestore(&priv->lock, flags);
1020
1021 return 0;
1022 }
1023
1024 static void rtl839x_eth_set_multicast_list(struct net_device *ndev)
1025 {
1026 if (!(ndev->flags & (IFF_PROMISC | IFF_ALLMULTI))) {
1027 sw_w32(0x0, RTL839X_RMA_CTRL_0);
1028 sw_w32(0x0, RTL839X_RMA_CTRL_1);
1029 sw_w32(0x0, RTL839X_RMA_CTRL_2);
1030 sw_w32(0x0, RTL839X_RMA_CTRL_3);
1031 }
1032 if (ndev->flags & IFF_ALLMULTI) {
1033 sw_w32(0x7fffffff, RTL839X_RMA_CTRL_0);
1034 sw_w32(0x7fffffff, RTL839X_RMA_CTRL_1);
1035 sw_w32(0x7fffffff, RTL839X_RMA_CTRL_2);
1036 }
1037 if (ndev->flags & IFF_PROMISC) {
1038 sw_w32(0x7fffffff, RTL839X_RMA_CTRL_0);
1039 sw_w32(0x7fffffff, RTL839X_RMA_CTRL_1);
1040 sw_w32(0x7fffffff, RTL839X_RMA_CTRL_2);
1041 sw_w32(0x3ff, RTL839X_RMA_CTRL_3);
1042 }
1043 }
1044
1045 static void rtl838x_eth_set_multicast_list(struct net_device *ndev)
1046 {
1047 struct rtl838x_eth_priv *priv = netdev_priv(ndev);
1048
1049 if (priv->family_id == RTL8390_FAMILY_ID)
1050 return rtl839x_eth_set_multicast_list(ndev);
1051
1052 if (!(ndev->flags & (IFF_PROMISC | IFF_ALLMULTI))) {
1053 sw_w32(0x0, RTL838X_RMA_CTRL_0);
1054 sw_w32(0x0, RTL838X_RMA_CTRL_1);
1055 }
1056 if (ndev->flags & IFF_ALLMULTI)
1057 sw_w32(0x1fffff, RTL838X_RMA_CTRL_0);
1058 if (ndev->flags & IFF_PROMISC) {
1059 sw_w32(0x1fffff, RTL838X_RMA_CTRL_0);
1060 sw_w32(0x7fff, RTL838X_RMA_CTRL_1);
1061 }
1062 }
1063
1064 static void rtl930x_eth_set_multicast_list(struct net_device *ndev)
1065 {
1066 if (!(ndev->flags & (IFF_PROMISC | IFF_ALLMULTI))) {
1067 sw_w32(0x0, RTL930X_RMA_CTRL_0);
1068 sw_w32(0x0, RTL930X_RMA_CTRL_1);
1069 sw_w32(0x0, RTL930X_RMA_CTRL_2);
1070 }
1071 if (ndev->flags & IFF_ALLMULTI) {
1072 sw_w32(0x7fffffff, RTL930X_RMA_CTRL_0);
1073 sw_w32(0x7fffffff, RTL930X_RMA_CTRL_1);
1074 sw_w32(0x7fffffff, RTL930X_RMA_CTRL_2);
1075 }
1076 if (ndev->flags & IFF_PROMISC) {
1077 sw_w32(0x7fffffff, RTL930X_RMA_CTRL_0);
1078 sw_w32(0x7fffffff, RTL930X_RMA_CTRL_1);
1079 sw_w32(0x7fffffff, RTL930X_RMA_CTRL_2);
1080 }
1081 }
1082
1083 static void rtl931x_eth_set_multicast_list(struct net_device *ndev)
1084 {
1085 if (!(ndev->flags & (IFF_PROMISC | IFF_ALLMULTI))) {
1086 sw_w32(0x0, RTL931X_RMA_CTRL_0);
1087 sw_w32(0x0, RTL931X_RMA_CTRL_1);
1088 sw_w32(0x0, RTL931X_RMA_CTRL_2);
1089 }
1090 if (ndev->flags & IFF_ALLMULTI) {
1091 sw_w32(0x7fffffff, RTL931X_RMA_CTRL_0);
1092 sw_w32(0x7fffffff, RTL931X_RMA_CTRL_1);
1093 sw_w32(0x7fffffff, RTL931X_RMA_CTRL_2);
1094 }
1095 if (ndev->flags & IFF_PROMISC) {
1096 sw_w32(0x7fffffff, RTL931X_RMA_CTRL_0);
1097 sw_w32(0x7fffffff, RTL931X_RMA_CTRL_1);
1098 sw_w32(0x7fffffff, RTL931X_RMA_CTRL_2);
1099 }
1100 }
1101
1102 static void rtl838x_eth_tx_timeout(struct net_device *ndev, unsigned int txqueue)
1103 {
1104 unsigned long flags;
1105 struct rtl838x_eth_priv *priv = netdev_priv(ndev);
1106
1107 pr_warn("%s\n", __func__);
1108 spin_lock_irqsave(&priv->lock, flags);
1109 rtl838x_hw_stop(priv);
1110 rtl838x_hw_ring_setup(priv);
1111 rtl838x_hw_en_rxtx(priv);
1112 netif_trans_update(ndev);
1113 netif_start_queue(ndev);
1114 spin_unlock_irqrestore(&priv->lock, flags);
1115 }
1116
1117 static int rtl838x_eth_tx(struct sk_buff *skb, struct net_device *dev)
1118 {
1119 int len, i;
1120 struct rtl838x_eth_priv *priv = netdev_priv(dev);
1121 struct ring_b *ring = priv->membase;
1122 uint32_t val;
1123 int ret;
1124 unsigned long flags;
1125 struct p_hdr *h;
1126 int dest_port = -1;
1127 int q = skb_get_queue_mapping(skb) % TXRINGS;
1128
1129 if (q) // Check for high prio queue
1130 pr_debug("SKB priority: %d\n", skb->priority);
1131
1132 spin_lock_irqsave(&priv->lock, flags);
1133 len = skb->len;
1134
1135 /* Check for DSA tagging at the end of the buffer */
1136 if (netdev_uses_dsa(dev) && skb->data[len-4] == 0x80 && skb->data[len-3] > 0
1137 && skb->data[len-3] < priv->cpu_port && skb->data[len-2] == 0x10
1138 && skb->data[len-1] == 0x00) {
1139 /* Reuse tag space for CRC if possible */
1140 dest_port = skb->data[len-3];
1141 skb->data[len-4] = skb->data[len-3] = skb->data[len-2] = skb->data[len-1] = 0x00;
1142 len -= 4;
1143 }
1144
1145 len += 4; // Add space for CRC
1146
1147 if (skb_padto(skb, len)) {
1148 ret = NETDEV_TX_OK;
1149 goto txdone;
1150 }
1151
1152 /* We can send this packet if CPU owns the descriptor */
1153 if (!(ring->tx_r[q][ring->c_tx[q]] & 0x1)) {
1154
1155 /* Set descriptor for tx */
1156 h = &ring->tx_header[q][ring->c_tx[q]];
1157 h->size = len;
1158 h->len = len;
1159 // On RTL8380 SoCs, small packet lengths being sent need adjustments
1160 if (priv->family_id == RTL8380_FAMILY_ID) {
1161 if (len < ETH_ZLEN - 4)
1162 h->len -= 4;
1163 }
1164
1165 priv->r->create_tx_header(h, dest_port, skb->priority >> 1);
1166
1167 /* Copy packet data to tx buffer */
1168 memcpy((void *)KSEG1ADDR(h->buf), skb->data, len);
1169 /* Make sure packet data is visible to ASIC */
1170 wmb();
1171
1172 /* Hand over to switch */
1173 ring->tx_r[q][ring->c_tx[q]] |= 1;
1174
1175 // Before starting TX, prevent a Lextra bus bug on RTL8380 SoCs
1176 if (priv->family_id == RTL8380_FAMILY_ID) {
1177 for (i = 0; i < 10; i++) {
1178 val = sw_r32(priv->r->dma_if_ctrl);
1179 if ((val & 0xc) == 0xc)
1180 break;
1181 }
1182 }
1183
1184 /* Tell switch to send data */
1185 if (priv->family_id == RTL9310_FAMILY_ID
1186 || priv->family_id == RTL9300_FAMILY_ID) {
1187 // Ring ID q == 0: Low priority, Ring ID = 1: High prio queue
1188 if (!q)
1189 sw_w32_mask(0, BIT(2), priv->r->dma_if_ctrl);
1190 else
1191 sw_w32_mask(0, BIT(3), priv->r->dma_if_ctrl);
1192 } else {
1193 sw_w32_mask(0, TX_DO, priv->r->dma_if_ctrl);
1194 }
1195
1196 dev->stats.tx_packets++;
1197 dev->stats.tx_bytes += len;
1198 dev_kfree_skb(skb);
1199 ring->c_tx[q] = (ring->c_tx[q] + 1) % TXRINGLEN;
1200 ret = NETDEV_TX_OK;
1201 } else {
1202 dev_warn(&priv->pdev->dev, "Data is owned by switch\n");
1203 ret = NETDEV_TX_BUSY;
1204 }
1205 txdone:
1206 spin_unlock_irqrestore(&priv->lock, flags);
1207 return ret;
1208 }
1209
1210 /*
1211 * Return queue number for TX. On the RTL83XX, these queues have equal priority
1212 * so we do round-robin
1213 */
1214 u16 rtl83xx_pick_tx_queue(struct net_device *dev, struct sk_buff *skb,
1215 struct net_device *sb_dev)
1216 {
1217 static u8 last = 0;
1218
1219 last++;
1220 return last % TXRINGS;
1221 }
1222
1223 /*
1224 * Return queue number for TX. On the RTL93XX, queue 1 is the high priority queue
1225 */
1226 u16 rtl93xx_pick_tx_queue(struct net_device *dev, struct sk_buff *skb,
1227 struct net_device *sb_dev)
1228 {
1229 if (skb->priority >= TC_PRIO_CONTROL)
1230 return 1;
1231 return 0;
1232 }
1233
1234 static int rtl838x_hw_receive(struct net_device *dev, int r, int budget)
1235 {
1236 struct rtl838x_eth_priv *priv = netdev_priv(dev);
1237 struct ring_b *ring = priv->membase;
1238 struct sk_buff *skb;
1239 unsigned long flags;
1240 int i, len, work_done = 0;
1241 u8 *data, *skb_data;
1242 unsigned int val;
1243 u32 *last;
1244 struct p_hdr *h;
1245 bool dsa = netdev_uses_dsa(dev);
1246 struct dsa_tag tag;
1247
1248 spin_lock_irqsave(&priv->lock, flags);
1249 last = (u32 *)KSEG1ADDR(sw_r32(priv->r->dma_if_rx_cur + r * 4));
1250 pr_debug("---------------------------------------------------------- RX - %d\n", r);
1251
1252 do {
1253 if ((ring->rx_r[r][ring->c_rx[r]] & 0x1)) {
1254 if (&ring->rx_r[r][ring->c_rx[r]] != last) {
1255 netdev_warn(dev, "Ring contention: r: %x, last %x, cur %x\n",
1256 r, (uint32_t)last, (u32) &ring->rx_r[r][ring->c_rx[r]]);
1257 }
1258 break;
1259 }
1260
1261 h = &ring->rx_header[r][ring->c_rx[r]];
1262 data = (u8 *)KSEG1ADDR(h->buf);
1263 len = h->len;
1264 if (!len)
1265 break;
1266 work_done++;
1267
1268 len -= 4; /* strip the CRC */
1269 /* Add 4 bytes for cpu_tag */
1270 if (dsa)
1271 len += 4;
1272
1273 skb = alloc_skb(len + 4, GFP_KERNEL);
1274 skb_reserve(skb, NET_IP_ALIGN);
1275
1276 if (likely(skb)) {
1277 /* BUG: Prevent bug on RTL838x SoCs*/
1278 if (priv->family_id == RTL8380_FAMILY_ID) {
1279 sw_w32(0xffffffff, priv->r->dma_if_rx_ring_size(0));
1280 for (i = 0; i < priv->rxrings; i++) {
1281 /* Update each ring cnt */
1282 val = sw_r32(priv->r->dma_if_rx_ring_cntr(i));
1283 sw_w32(val, priv->r->dma_if_rx_ring_cntr(i));
1284 }
1285 }
1286
1287 skb_data = skb_put(skb, len);
1288 /* Make sure data is visible */
1289 mb();
1290 memcpy(skb->data, (u8 *)KSEG1ADDR(data), len);
1291 /* Overwrite CRC with cpu_tag */
1292 if (dsa) {
1293 priv->r->decode_tag(h, &tag);
1294 skb->data[len-4] = 0x80;
1295 skb->data[len-3] = tag.port;
1296 skb->data[len-2] = 0x10;
1297 skb->data[len-1] = 0x00;
1298 if (tag.l2_offloaded)
1299 skb->data[len-3] |= 0x40;
1300 }
1301
1302 if (tag.queue >= 0)
1303 pr_debug("Queue: %d, len: %d, reason %d port %d\n",
1304 tag.queue, len, tag.reason, tag.port);
1305
1306 skb->protocol = eth_type_trans(skb, dev);
1307 if (dev->features & NETIF_F_RXCSUM) {
1308 if (tag.crc_error)
1309 skb_checksum_none_assert(skb);
1310 else
1311 skb->ip_summed = CHECKSUM_UNNECESSARY;
1312 }
1313 dev->stats.rx_packets++;
1314 dev->stats.rx_bytes += len;
1315
1316 netif_receive_skb(skb);
1317 } else {
1318 if (net_ratelimit())
1319 dev_warn(&dev->dev, "low on memory - packet dropped\n");
1320 dev->stats.rx_dropped++;
1321 }
1322
1323 /* Reset header structure */
1324 memset(h, 0, sizeof(struct p_hdr));
1325 h->buf = data;
1326 h->size = RING_BUFFER;
1327
1328 ring->rx_r[r][ring->c_rx[r]] = KSEG1ADDR(h) | 0x1
1329 | (ring->c_rx[r] == (priv->rxringlen - 1) ? WRAP : 0x1);
1330 ring->c_rx[r] = (ring->c_rx[r] + 1) % priv->rxringlen;
1331 last = (u32 *)KSEG1ADDR(sw_r32(priv->r->dma_if_rx_cur + r * 4));
1332 } while (&ring->rx_r[r][ring->c_rx[r]] != last && work_done < budget);
1333
1334 // Update counters
1335 priv->r->update_cntr(r, 0);
1336
1337 spin_unlock_irqrestore(&priv->lock, flags);
1338 return work_done;
1339 }
1340
1341 static int rtl838x_poll_rx(struct napi_struct *napi, int budget)
1342 {
1343 struct rtl838x_rx_q *rx_q = container_of(napi, struct rtl838x_rx_q, napi);
1344 struct rtl838x_eth_priv *priv = rx_q->priv;
1345 int work_done = 0;
1346 int r = rx_q->id;
1347 int work;
1348
1349 while (work_done < budget) {
1350 work = rtl838x_hw_receive(priv->netdev, r, budget - work_done);
1351 if (!work)
1352 break;
1353 work_done += work;
1354 }
1355
1356 if (work_done < budget) {
1357 napi_complete_done(napi, work_done);
1358
1359 /* Enable RX interrupt */
1360 if (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID)
1361 sw_w32(0xffffffff, priv->r->dma_if_intr_rx_done_msk);
1362 else
1363 sw_w32_mask(0, 0xf00ff | BIT(r + 8), priv->r->dma_if_intr_msk);
1364 }
1365 return work_done;
1366 }
1367
1368
1369 static void rtl838x_validate(struct phylink_config *config,
1370 unsigned long *supported,
1371 struct phylink_link_state *state)
1372 {
1373 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
1374
1375 pr_debug("In %s\n", __func__);
1376
1377 if (!phy_interface_mode_is_rgmii(state->interface) &&
1378 state->interface != PHY_INTERFACE_MODE_1000BASEX &&
1379 state->interface != PHY_INTERFACE_MODE_MII &&
1380 state->interface != PHY_INTERFACE_MODE_REVMII &&
1381 state->interface != PHY_INTERFACE_MODE_GMII &&
1382 state->interface != PHY_INTERFACE_MODE_QSGMII &&
1383 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
1384 state->interface != PHY_INTERFACE_MODE_SGMII) {
1385 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
1386 pr_err("Unsupported interface: %d\n", state->interface);
1387 return;
1388 }
1389
1390 /* Allow all the expected bits */
1391 phylink_set(mask, Autoneg);
1392 phylink_set_port_modes(mask);
1393 phylink_set(mask, Pause);
1394 phylink_set(mask, Asym_Pause);
1395
1396 /* With the exclusion of MII and Reverse MII, we support Gigabit,
1397 * including Half duplex
1398 */
1399 if (state->interface != PHY_INTERFACE_MODE_MII &&
1400 state->interface != PHY_INTERFACE_MODE_REVMII) {
1401 phylink_set(mask, 1000baseT_Full);
1402 phylink_set(mask, 1000baseT_Half);
1403 }
1404
1405 phylink_set(mask, 10baseT_Half);
1406 phylink_set(mask, 10baseT_Full);
1407 phylink_set(mask, 100baseT_Half);
1408 phylink_set(mask, 100baseT_Full);
1409
1410 bitmap_and(supported, supported, mask,
1411 __ETHTOOL_LINK_MODE_MASK_NBITS);
1412 bitmap_and(state->advertising, state->advertising, mask,
1413 __ETHTOOL_LINK_MODE_MASK_NBITS);
1414 }
1415
1416
1417 static void rtl838x_mac_config(struct phylink_config *config,
1418 unsigned int mode,
1419 const struct phylink_link_state *state)
1420 {
1421 /* This is only being called for the master device,
1422 * i.e. the CPU-Port. We don't need to do anything.
1423 */
1424
1425 pr_info("In %s, mode %x\n", __func__, mode);
1426 }
1427
1428 static void rtl838x_mac_an_restart(struct phylink_config *config)
1429 {
1430 struct net_device *dev = container_of(config->dev, struct net_device, dev);
1431 struct rtl838x_eth_priv *priv = netdev_priv(dev);
1432
1433 /* This works only on RTL838x chips */
1434 if (priv->family_id != RTL8380_FAMILY_ID)
1435 return;
1436
1437 pr_debug("In %s\n", __func__);
1438 /* Restart by disabling and re-enabling link */
1439 sw_w32(0x6192D, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
1440 mdelay(20);
1441 sw_w32(0x6192F, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
1442 }
1443
1444 static void rtl838x_mac_pcs_get_state(struct phylink_config *config,
1445 struct phylink_link_state *state)
1446 {
1447 u32 speed;
1448 struct net_device *dev = container_of(config->dev, struct net_device, dev);
1449 struct rtl838x_eth_priv *priv = netdev_priv(dev);
1450 int port = priv->cpu_port;
1451
1452 pr_debug("In %s\n", __func__);
1453
1454 state->link = priv->r->get_mac_link_sts(port) ? 1 : 0;
1455 state->duplex = priv->r->get_mac_link_dup_sts(port) ? 1 : 0;
1456
1457 speed = priv->r->get_mac_link_spd_sts(port);
1458 switch (speed) {
1459 case 0:
1460 state->speed = SPEED_10;
1461 break;
1462 case 1:
1463 state->speed = SPEED_100;
1464 break;
1465 case 2:
1466 state->speed = SPEED_1000;
1467 break;
1468 default:
1469 state->speed = SPEED_UNKNOWN;
1470 break;
1471 }
1472
1473 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
1474 if (priv->r->get_mac_rx_pause_sts(port))
1475 state->pause |= MLO_PAUSE_RX;
1476 if (priv->r->get_mac_tx_pause_sts(port))
1477 state->pause |= MLO_PAUSE_TX;
1478 }
1479
1480 static void rtl838x_mac_link_down(struct phylink_config *config,
1481 unsigned int mode,
1482 phy_interface_t interface)
1483 {
1484 struct net_device *dev = container_of(config->dev, struct net_device, dev);
1485 struct rtl838x_eth_priv *priv = netdev_priv(dev);
1486
1487 pr_debug("In %s\n", __func__);
1488 /* Stop TX/RX to port */
1489 sw_w32_mask(0x03, 0, priv->r->mac_port_ctrl(priv->cpu_port));
1490 }
1491
1492 static void rtl838x_mac_link_up(struct phylink_config *config,
1493 struct phy_device *phy, unsigned int mode,
1494 phy_interface_t interface, int speed, int duplex,
1495 bool tx_pause, bool rx_pause)
1496 {
1497 struct net_device *dev = container_of(config->dev, struct net_device, dev);
1498 struct rtl838x_eth_priv *priv = netdev_priv(dev);
1499
1500 pr_debug("In %s\n", __func__);
1501 /* Restart TX/RX to port */
1502 sw_w32_mask(0, 0x03, priv->r->mac_port_ctrl(priv->cpu_port));
1503 }
1504
1505 static void rtl838x_set_mac_hw(struct net_device *dev, u8 *mac)
1506 {
1507 struct rtl838x_eth_priv *priv = netdev_priv(dev);
1508 unsigned long flags;
1509
1510 spin_lock_irqsave(&priv->lock, flags);
1511 pr_debug("In %s\n", __func__);
1512 sw_w32((mac[0] << 8) | mac[1], priv->r->mac);
1513 sw_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5], priv->r->mac + 4);
1514
1515 if (priv->family_id == RTL8380_FAMILY_ID) {
1516 /* 2 more registers, ALE/MAC block */
1517 sw_w32((mac[0] << 8) | mac[1], RTL838X_MAC_ALE);
1518 sw_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
1519 (RTL838X_MAC_ALE + 4));
1520
1521 sw_w32((mac[0] << 8) | mac[1], RTL838X_MAC2);
1522 sw_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
1523 RTL838X_MAC2 + 4);
1524 }
1525 spin_unlock_irqrestore(&priv->lock, flags);
1526 }
1527
1528 static int rtl838x_set_mac_address(struct net_device *dev, void *p)
1529 {
1530 struct rtl838x_eth_priv *priv = netdev_priv(dev);
1531 const struct sockaddr *addr = p;
1532 u8 *mac = (u8 *) (addr->sa_data);
1533
1534 if (!is_valid_ether_addr(addr->sa_data))
1535 return -EADDRNOTAVAIL;
1536
1537 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
1538 rtl838x_set_mac_hw(dev, mac);
1539
1540 pr_info("Using MAC %08x%08x\n", sw_r32(priv->r->mac), sw_r32(priv->r->mac + 4));
1541 return 0;
1542 }
1543
1544 static int rtl8390_init_mac(struct rtl838x_eth_priv *priv)
1545 {
1546 // We will need to set-up EEE and the egress-rate limitation
1547 return 0;
1548 }
1549
1550 static int rtl8380_init_mac(struct rtl838x_eth_priv *priv)
1551 {
1552 int i;
1553
1554 if (priv->family_id == 0x8390)
1555 return rtl8390_init_mac(priv);
1556
1557 pr_info("%s\n", __func__);
1558 /* fix timer for EEE */
1559 sw_w32(0x5001411, RTL838X_EEE_TX_TIMER_GIGA_CTRL);
1560 sw_w32(0x5001417, RTL838X_EEE_TX_TIMER_GELITE_CTRL);
1561
1562 /* Init VLAN */
1563 if (priv->id == 0x8382) {
1564 for (i = 0; i <= 28; i++)
1565 sw_w32(0, 0xd57c + i * 0x80);
1566 }
1567 if (priv->id == 0x8380) {
1568 for (i = 8; i <= 28; i++)
1569 sw_w32(0, 0xd57c + i * 0x80);
1570 }
1571 return 0;
1572 }
1573
1574 static int rtl838x_get_link_ksettings(struct net_device *ndev,
1575 struct ethtool_link_ksettings *cmd)
1576 {
1577 struct rtl838x_eth_priv *priv = netdev_priv(ndev);
1578
1579 pr_debug("%s called\n", __func__);
1580 return phylink_ethtool_ksettings_get(priv->phylink, cmd);
1581 }
1582
1583 static int rtl838x_set_link_ksettings(struct net_device *ndev,
1584 const struct ethtool_link_ksettings *cmd)
1585 {
1586 struct rtl838x_eth_priv *priv = netdev_priv(ndev);
1587
1588 pr_debug("%s called\n", __func__);
1589 return phylink_ethtool_ksettings_set(priv->phylink, cmd);
1590 }
1591
1592 static int rtl838x_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1593 {
1594 u32 val;
1595 int err;
1596 struct rtl838x_eth_priv *priv = bus->priv;
1597
1598 if (mii_id >= 24 && mii_id <= 27 && priv->id == 0x8380)
1599 return rtl838x_read_sds_phy(mii_id, regnum);
1600 err = rtl838x_read_phy(mii_id, 0, regnum, &val);
1601 if (err)
1602 return err;
1603 return val;
1604 }
1605
1606 static int rtl839x_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1607 {
1608 u32 val;
1609 int err;
1610 struct rtl838x_eth_priv *priv = bus->priv;
1611
1612 if (mii_id >= 48 && mii_id <= 49 && priv->id == 0x8393)
1613 return rtl839x_read_sds_phy(mii_id, regnum);
1614
1615 err = rtl839x_read_phy(mii_id, 0, regnum, &val);
1616 if (err)
1617 return err;
1618 return val;
1619 }
1620
1621 static int rtl930x_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1622 {
1623 u32 val;
1624 int err;
1625
1626 // TODO: These are hard-coded for the 2 Fibre Ports of the XGS1210
1627 if (mii_id >= 26 && mii_id <= 27)
1628 return rtl930x_read_sds_phy(mii_id - 18, 0, regnum);
1629
1630 if (regnum & MII_ADDR_C45) {
1631 regnum &= ~MII_ADDR_C45;
1632 err = rtl930x_read_mmd_phy(mii_id, regnum >> 16, regnum & 0xffff, &val);
1633 } else {
1634 err = rtl930x_read_phy(mii_id, 0, regnum, &val);
1635 }
1636 if (err)
1637 return err;
1638 return val;
1639 }
1640
1641 static int rtl931x_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1642 {
1643 u32 val;
1644 int err;
1645 // struct rtl838x_eth_priv *priv = bus->priv;
1646
1647 // if (mii_id >= 48 && mii_id <= 49 && priv->id == 0x8393)
1648 // return rtl839x_read_sds_phy(mii_id, regnum);
1649
1650 err = rtl931x_read_phy(mii_id, 0, regnum, &val);
1651 if (err)
1652 return err;
1653 return val;
1654 }
1655
1656 static int rtl838x_mdio_write(struct mii_bus *bus, int mii_id,
1657 int regnum, u16 value)
1658 {
1659 u32 offset = 0;
1660 struct rtl838x_eth_priv *priv = bus->priv;
1661
1662 if (mii_id >= 24 && mii_id <= 27 && priv->id == 0x8380) {
1663 if (mii_id == 26)
1664 offset = 0x100;
1665 sw_w32(value, RTL838X_SDS4_FIB_REG0 + offset + (regnum << 2));
1666 return 0;
1667 }
1668 return rtl838x_write_phy(mii_id, 0, regnum, value);
1669 }
1670
1671 static int rtl839x_mdio_write(struct mii_bus *bus, int mii_id,
1672 int regnum, u16 value)
1673 {
1674 struct rtl838x_eth_priv *priv = bus->priv;
1675
1676 if (mii_id >= 48 && mii_id <= 49 && priv->id == 0x8393)
1677 return rtl839x_write_sds_phy(mii_id, regnum, value);
1678
1679 return rtl839x_write_phy(mii_id, 0, regnum, value);
1680 }
1681
1682 static int rtl930x_mdio_write(struct mii_bus *bus, int mii_id,
1683 int regnum, u16 value)
1684 {
1685 // struct rtl838x_eth_priv *priv = bus->priv;
1686
1687 // if (mii_id >= 48 && mii_id <= 49 && priv->id == 0x8393)
1688 // return rtl839x_write_sds_phy(mii_id, regnum, value);
1689 if (regnum & MII_ADDR_C45) {
1690 regnum &= ~MII_ADDR_C45;
1691 return rtl930x_write_mmd_phy(mii_id, regnum >> 16, regnum & 0xffff, value);
1692 }
1693
1694 return rtl930x_write_phy(mii_id, 0, regnum, value);
1695 }
1696
1697 static int rtl931x_mdio_write(struct mii_bus *bus, int mii_id,
1698 int regnum, u16 value)
1699 {
1700 // struct rtl838x_eth_priv *priv = bus->priv;
1701
1702 // if (mii_id >= 48 && mii_id <= 49 && priv->id == 0x8393)
1703 // return rtl839x_write_sds_phy(mii_id, regnum, value);
1704
1705 return rtl931x_write_phy(mii_id, 0, regnum, value);
1706 }
1707
1708 static int rtl838x_mdio_reset(struct mii_bus *bus)
1709 {
1710 pr_debug("%s called\n", __func__);
1711 /* Disable MAC polling the PHY so that we can start configuration */
1712 sw_w32(0x00000000, RTL838X_SMI_POLL_CTRL);
1713
1714 /* Enable PHY control via SoC */
1715 sw_w32_mask(0, 1 << 15, RTL838X_SMI_GLB_CTRL);
1716
1717 // Probably should reset all PHYs here...
1718 return 0;
1719 }
1720
1721 static int rtl839x_mdio_reset(struct mii_bus *bus)
1722 {
1723 return 0;
1724
1725 pr_debug("%s called\n", __func__);
1726 /* BUG: The following does not work, but should! */
1727 /* Disable MAC polling the PHY so that we can start configuration */
1728 sw_w32(0x00000000, RTL839X_SMI_PORT_POLLING_CTRL);
1729 sw_w32(0x00000000, RTL839X_SMI_PORT_POLLING_CTRL + 4);
1730 /* Disable PHY polling via SoC */
1731 sw_w32_mask(1 << 7, 0, RTL839X_SMI_GLB_CTRL);
1732
1733 // Probably should reset all PHYs here...
1734 return 0;
1735 }
1736
1737 static int rtl930x_mdio_reset(struct mii_bus *bus)
1738 {
1739 int i;
1740 int pos;
1741 struct rtl838x_eth_priv *priv = bus->priv;
1742 u32 c45_mask = 0;
1743 u32 poll_sel[2];
1744 u32 poll_ctrl = 0;
1745
1746 // Mapping of port to phy-addresses on an SMI bus
1747 poll_sel[0] = poll_sel[1] = 0;
1748 for (i = 0; i < 28; i++) {
1749 pos = (i % 6) * 5;
1750 sw_w32_mask(0x1f << pos, priv->smi_addr[i] << pos,
1751 RTL930X_SMI_PORT0_5_ADDR + (i / 6) * 4);
1752
1753 pos = (i * 2) % 32;
1754 poll_sel[i / 16] |= priv->smi_bus[i] << pos;
1755 poll_ctrl |= BIT(20 + priv->smi_bus[i]);
1756 }
1757
1758 // Configure which SMI bus is behind which port number
1759 sw_w32(poll_sel[0], RTL930X_SMI_PORT0_15_POLLING_SEL);
1760 sw_w32(poll_sel[1], RTL930X_SMI_PORT16_27_POLLING_SEL);
1761
1762 // Enable polling on the respective SMI busses
1763 sw_w32_mask(0, poll_ctrl, RTL930X_SMI_GLB_CTRL);
1764
1765 // Configure which SMI busses are polled in c45 based on a c45 PHY being on that bus
1766 for (i = 0; i < 4; i++)
1767 if (priv->smi_bus_isc45[i])
1768 c45_mask |= BIT(i + 16);
1769
1770 pr_info("c45_mask: %08x\n", c45_mask);
1771 sw_w32_mask(0, c45_mask, RTL930X_SMI_GLB_CTRL);
1772
1773 // Ports 24 to 27 are 2.5 or 10Gig, set this type (1) or (0) for internal SerDes
1774 for (i = 24; i < 28; i++) {
1775 pos = (i - 24) * 3 + 12;
1776 if (priv->phy_is_internal[i])
1777 sw_w32_mask(0x7 << pos, 0 << pos, RTL930X_SMI_MAC_TYPE_CTRL);
1778 else
1779 sw_w32_mask(0x7 << pos, 1 << pos, RTL930X_SMI_MAC_TYPE_CTRL);
1780 }
1781
1782 // TODO: Set up RTL9300_SMI_10GPHY_POLLING_SEL_0 for Aquantia PHYs on e.g. XGS 1250
1783
1784 return 0;
1785 }
1786
1787 static int rtl838x_mdio_init(struct rtl838x_eth_priv *priv)
1788 {
1789 struct device_node *mii_np, *dn;
1790 u32 pn;
1791 int ret;
1792
1793 pr_debug("%s called\n", __func__);
1794 mii_np = of_get_child_by_name(priv->pdev->dev.of_node, "mdio-bus");
1795
1796 if (!mii_np) {
1797 dev_err(&priv->pdev->dev, "no %s child node found", "mdio-bus");
1798 return -ENODEV;
1799 }
1800
1801 if (!of_device_is_available(mii_np)) {
1802 ret = -ENODEV;
1803 goto err_put_node;
1804 }
1805
1806 priv->mii_bus = devm_mdiobus_alloc(&priv->pdev->dev);
1807 if (!priv->mii_bus) {
1808 ret = -ENOMEM;
1809 goto err_put_node;
1810 }
1811
1812 switch(priv->family_id) {
1813 case RTL8380_FAMILY_ID:
1814 priv->mii_bus->name = "rtl838x-eth-mdio";
1815 priv->mii_bus->read = rtl838x_mdio_read;
1816 priv->mii_bus->write = rtl838x_mdio_write;
1817 priv->mii_bus->reset = rtl838x_mdio_reset;
1818 break;
1819 case RTL8390_FAMILY_ID:
1820 priv->mii_bus->name = "rtl839x-eth-mdio";
1821 priv->mii_bus->read = rtl839x_mdio_read;
1822 priv->mii_bus->write = rtl839x_mdio_write;
1823 priv->mii_bus->reset = rtl839x_mdio_reset;
1824 break;
1825 case RTL9300_FAMILY_ID:
1826 priv->mii_bus->name = "rtl930x-eth-mdio";
1827 priv->mii_bus->read = rtl930x_mdio_read;
1828 priv->mii_bus->write = rtl930x_mdio_write;
1829 priv->mii_bus->reset = rtl930x_mdio_reset;
1830 // priv->mii_bus->probe_capabilities = MDIOBUS_C22_C45; TODO for linux 5.9
1831 break;
1832 case RTL9310_FAMILY_ID:
1833 priv->mii_bus->name = "rtl931x-eth-mdio";
1834 priv->mii_bus->read = rtl931x_mdio_read;
1835 priv->mii_bus->write = rtl931x_mdio_write;
1836 priv->mii_bus->reset = rtl931x_mdio_reset;
1837 // priv->mii_bus->probe_capabilities = MDIOBUS_C22_C45; TODO for linux 5.9
1838 break;
1839 }
1840 priv->mii_bus->priv = priv;
1841 priv->mii_bus->parent = &priv->pdev->dev;
1842
1843 for_each_node_by_name(dn, "ethernet-phy") {
1844 u32 smi_addr[2];
1845
1846 if (of_property_read_u32(dn, "reg", &pn))
1847 continue;
1848
1849 if (of_property_read_u32_array(dn, "rtl9300,smi-address", &smi_addr[0], 2)) {
1850 smi_addr[0] = 0;
1851 smi_addr[1] = pn;
1852 }
1853
1854 if (of_property_read_u32(dn, "sds", &priv->sds_id[pn]))
1855 priv->sds_id[pn] = -1;
1856 else {
1857 pr_info("set sds port %d to %d\n", pn, priv->sds_id[pn]);
1858 }
1859
1860 if (pn < MAX_PORTS) {
1861 priv->smi_bus[pn] = smi_addr[0];
1862 priv->smi_addr[pn] = smi_addr[1];
1863 } else {
1864 pr_err("%s: illegal port number %d\n", __func__, pn);
1865 }
1866
1867 if (of_device_is_compatible(dn, "ethernet-phy-ieee802.3-c45"))
1868 priv->smi_bus_isc45[smi_addr[0]] = true;
1869
1870 if (of_property_read_bool(dn, "phy-is-integrated")) {
1871 priv->phy_is_internal[pn] = true;
1872 }
1873
1874 }
1875
1876 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np);
1877 ret = of_mdiobus_register(priv->mii_bus, mii_np);
1878
1879 err_put_node:
1880 of_node_put(mii_np);
1881 return ret;
1882 }
1883
1884 static int rtl838x_mdio_remove(struct rtl838x_eth_priv *priv)
1885 {
1886 pr_debug("%s called\n", __func__);
1887 if (!priv->mii_bus)
1888 return 0;
1889
1890 mdiobus_unregister(priv->mii_bus);
1891 mdiobus_free(priv->mii_bus);
1892
1893 return 0;
1894 }
1895
1896 static netdev_features_t rtl838x_fix_features(struct net_device *dev,
1897 netdev_features_t features)
1898 {
1899 return features;
1900 }
1901
1902 static int rtl83xx_set_features(struct net_device *dev, netdev_features_t features)
1903 {
1904 struct rtl838x_eth_priv *priv = netdev_priv(dev);
1905
1906 if ((features ^ dev->features) & NETIF_F_RXCSUM) {
1907 if (!(features & NETIF_F_RXCSUM))
1908 sw_w32_mask(BIT(3), 0, priv->r->mac_port_ctrl(priv->cpu_port));
1909 else
1910 sw_w32_mask(0, BIT(4), priv->r->mac_port_ctrl(priv->cpu_port));
1911 }
1912
1913 return 0;
1914 }
1915
1916 static int rtl93xx_set_features(struct net_device *dev, netdev_features_t features)
1917 {
1918 struct rtl838x_eth_priv *priv = netdev_priv(dev);
1919
1920 if ((features ^ dev->features) & NETIF_F_RXCSUM) {
1921 if (!(features & NETIF_F_RXCSUM))
1922 sw_w32_mask(BIT(4), 0, priv->r->mac_port_ctrl(priv->cpu_port));
1923 else
1924 sw_w32_mask(0, BIT(4), priv->r->mac_port_ctrl(priv->cpu_port));
1925 }
1926
1927 return 0;
1928 }
1929
1930 static const struct net_device_ops rtl838x_eth_netdev_ops = {
1931 .ndo_open = rtl838x_eth_open,
1932 .ndo_stop = rtl838x_eth_stop,
1933 .ndo_start_xmit = rtl838x_eth_tx,
1934 .ndo_select_queue = rtl83xx_pick_tx_queue,
1935 .ndo_set_mac_address = rtl838x_set_mac_address,
1936 .ndo_validate_addr = eth_validate_addr,
1937 .ndo_set_rx_mode = rtl838x_eth_set_multicast_list,
1938 .ndo_tx_timeout = rtl838x_eth_tx_timeout,
1939 .ndo_set_features = rtl83xx_set_features,
1940 .ndo_fix_features = rtl838x_fix_features,
1941 .ndo_setup_tc = rtl83xx_setup_tc,
1942 };
1943
1944 static const struct net_device_ops rtl839x_eth_netdev_ops = {
1945 .ndo_open = rtl838x_eth_open,
1946 .ndo_stop = rtl838x_eth_stop,
1947 .ndo_start_xmit = rtl838x_eth_tx,
1948 .ndo_select_queue = rtl83xx_pick_tx_queue,
1949 .ndo_set_mac_address = rtl838x_set_mac_address,
1950 .ndo_validate_addr = eth_validate_addr,
1951 .ndo_set_rx_mode = rtl839x_eth_set_multicast_list,
1952 .ndo_tx_timeout = rtl838x_eth_tx_timeout,
1953 .ndo_set_features = rtl83xx_set_features,
1954 .ndo_fix_features = rtl838x_fix_features,
1955 .ndo_setup_tc = rtl83xx_setup_tc,
1956 };
1957
1958 static const struct net_device_ops rtl930x_eth_netdev_ops = {
1959 .ndo_open = rtl838x_eth_open,
1960 .ndo_stop = rtl838x_eth_stop,
1961 .ndo_start_xmit = rtl838x_eth_tx,
1962 .ndo_select_queue = rtl93xx_pick_tx_queue,
1963 .ndo_set_mac_address = rtl838x_set_mac_address,
1964 .ndo_validate_addr = eth_validate_addr,
1965 .ndo_set_rx_mode = rtl930x_eth_set_multicast_list,
1966 .ndo_tx_timeout = rtl838x_eth_tx_timeout,
1967 .ndo_set_features = rtl93xx_set_features,
1968 .ndo_fix_features = rtl838x_fix_features,
1969 .ndo_setup_tc = rtl83xx_setup_tc,
1970 };
1971
1972 static const struct net_device_ops rtl931x_eth_netdev_ops = {
1973 .ndo_open = rtl838x_eth_open,
1974 .ndo_stop = rtl838x_eth_stop,
1975 .ndo_start_xmit = rtl838x_eth_tx,
1976 .ndo_select_queue = rtl93xx_pick_tx_queue,
1977 .ndo_set_mac_address = rtl838x_set_mac_address,
1978 .ndo_validate_addr = eth_validate_addr,
1979 .ndo_set_rx_mode = rtl931x_eth_set_multicast_list,
1980 .ndo_tx_timeout = rtl838x_eth_tx_timeout,
1981 .ndo_set_features = rtl93xx_set_features,
1982 .ndo_fix_features = rtl838x_fix_features,
1983 };
1984
1985 static const struct phylink_mac_ops rtl838x_phylink_ops = {
1986 .validate = rtl838x_validate,
1987 .mac_pcs_get_state = rtl838x_mac_pcs_get_state,
1988 .mac_an_restart = rtl838x_mac_an_restart,
1989 .mac_config = rtl838x_mac_config,
1990 .mac_link_down = rtl838x_mac_link_down,
1991 .mac_link_up = rtl838x_mac_link_up,
1992 };
1993
1994 static const struct ethtool_ops rtl838x_ethtool_ops = {
1995 .get_link_ksettings = rtl838x_get_link_ksettings,
1996 .set_link_ksettings = rtl838x_set_link_ksettings,
1997 };
1998
1999 static int __init rtl838x_eth_probe(struct platform_device *pdev)
2000 {
2001 struct net_device *dev;
2002 struct device_node *dn = pdev->dev.of_node;
2003 struct rtl838x_eth_priv *priv;
2004 struct resource *res, *mem;
2005 phy_interface_t phy_mode;
2006 struct phylink *phylink;
2007 int err = 0, i, rxrings, rxringlen;
2008 struct ring_b *ring;
2009
2010 pr_info("Probing RTL838X eth device pdev: %x, dev: %x\n",
2011 (u32)pdev, (u32)(&(pdev->dev)));
2012
2013 if (!dn) {
2014 dev_err(&pdev->dev, "No DT found\n");
2015 return -EINVAL;
2016 }
2017
2018 rxrings = (soc_info.family == RTL8380_FAMILY_ID
2019 || soc_info.family == RTL8390_FAMILY_ID) ? 8 : 32;
2020 rxrings = rxrings > MAX_RXRINGS ? MAX_RXRINGS : rxrings;
2021 rxringlen = MAX_ENTRIES / rxrings;
2022 rxringlen = rxringlen > MAX_RXLEN ? MAX_RXLEN : rxringlen;
2023
2024 dev = alloc_etherdev_mqs(sizeof(struct rtl838x_eth_priv), TXRINGS, rxrings);
2025 if (!dev) {
2026 err = -ENOMEM;
2027 goto err_free;
2028 }
2029 SET_NETDEV_DEV(dev, &pdev->dev);
2030 priv = netdev_priv(dev);
2031
2032 /* obtain buffer memory space */
2033 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2034 if (res) {
2035 mem = devm_request_mem_region(&pdev->dev, res->start,
2036 resource_size(res), res->name);
2037 if (!mem) {
2038 dev_err(&pdev->dev, "cannot request memory space\n");
2039 err = -ENXIO;
2040 goto err_free;
2041 }
2042
2043 dev->mem_start = mem->start;
2044 dev->mem_end = mem->end;
2045 } else {
2046 dev_err(&pdev->dev, "cannot request IO resource\n");
2047 err = -ENXIO;
2048 goto err_free;
2049 }
2050
2051 /* Allocate buffer memory */
2052 priv->membase = dmam_alloc_coherent(&pdev->dev, rxrings * rxringlen * RING_BUFFER
2053 + sizeof(struct ring_b) + sizeof(struct notify_b),
2054 (void *)&dev->mem_start, GFP_KERNEL);
2055 if (!priv->membase) {
2056 dev_err(&pdev->dev, "cannot allocate DMA buffer\n");
2057 err = -ENOMEM;
2058 goto err_free;
2059 }
2060
2061 // Allocate ring-buffer space at the end of the allocated memory
2062 ring = priv->membase;
2063 ring->rx_space = priv->membase + sizeof(struct ring_b) + sizeof(struct notify_b);
2064
2065 spin_lock_init(&priv->lock);
2066
2067 /* obtain device IRQ number */
2068 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2069 if (!res) {
2070 dev_err(&pdev->dev, "cannot obtain IRQ, using default 24\n");
2071 dev->irq = 24;
2072 } else {
2073 dev->irq = res->start;
2074 }
2075 dev->ethtool_ops = &rtl838x_ethtool_ops;
2076 dev->min_mtu = ETH_ZLEN;
2077 dev->max_mtu = 1536;
2078 dev->features = NETIF_F_RXCSUM | NETIF_F_HW_CSUM;
2079 dev->hw_features = NETIF_F_RXCSUM;
2080
2081 priv->id = soc_info.id;
2082 priv->family_id = soc_info.family;
2083 if (priv->id) {
2084 pr_info("Found SoC ID: %4x: %s, family %x\n",
2085 priv->id, soc_info.name, priv->family_id);
2086 } else {
2087 pr_err("Unknown chip id (%04x)\n", priv->id);
2088 return -ENODEV;
2089 }
2090
2091 switch (priv->family_id) {
2092 case RTL8380_FAMILY_ID:
2093 priv->cpu_port = RTL838X_CPU_PORT;
2094 priv->r = &rtl838x_reg;
2095 dev->netdev_ops = &rtl838x_eth_netdev_ops;
2096 break;
2097 case RTL8390_FAMILY_ID:
2098 priv->cpu_port = RTL839X_CPU_PORT;
2099 priv->r = &rtl839x_reg;
2100 dev->netdev_ops = &rtl839x_eth_netdev_ops;
2101 break;
2102 case RTL9300_FAMILY_ID:
2103 priv->cpu_port = RTL930X_CPU_PORT;
2104 priv->r = &rtl930x_reg;
2105 dev->netdev_ops = &rtl930x_eth_netdev_ops;
2106 break;
2107 case RTL9310_FAMILY_ID:
2108 priv->cpu_port = RTL931X_CPU_PORT;
2109 priv->r = &rtl931x_reg;
2110 dev->netdev_ops = &rtl931x_eth_netdev_ops;
2111 break;
2112 default:
2113 pr_err("Unknown SoC family\n");
2114 return -ENODEV;
2115 }
2116 priv->rxringlen = rxringlen;
2117 priv->rxrings = rxrings;
2118
2119 rtl8380_init_mac(priv);
2120
2121 /* try to get mac address in the following order:
2122 * 1) from device tree data
2123 * 2) from internal registers set by bootloader
2124 */
2125 of_get_mac_address(pdev->dev.of_node, dev->dev_addr);
2126 if (is_valid_ether_addr(dev->dev_addr)) {
2127 rtl838x_set_mac_hw(dev, (u8 *)dev->dev_addr);
2128 } else {
2129 dev->dev_addr[0] = (sw_r32(priv->r->mac) >> 8) & 0xff;
2130 dev->dev_addr[1] = sw_r32(priv->r->mac) & 0xff;
2131 dev->dev_addr[2] = (sw_r32(priv->r->mac + 4) >> 24) & 0xff;
2132 dev->dev_addr[3] = (sw_r32(priv->r->mac + 4) >> 16) & 0xff;
2133 dev->dev_addr[4] = (sw_r32(priv->r->mac + 4) >> 8) & 0xff;
2134 dev->dev_addr[5] = sw_r32(priv->r->mac + 4) & 0xff;
2135 }
2136 /* if the address is invalid, use a random value */
2137 if (!is_valid_ether_addr(dev->dev_addr)) {
2138 struct sockaddr sa = { AF_UNSPEC };
2139
2140 netdev_warn(dev, "Invalid MAC address, using random\n");
2141 eth_hw_addr_random(dev);
2142 memcpy(sa.sa_data, dev->dev_addr, ETH_ALEN);
2143 if (rtl838x_set_mac_address(dev, &sa))
2144 netdev_warn(dev, "Failed to set MAC address.\n");
2145 }
2146 pr_info("Using MAC %08x%08x\n", sw_r32(priv->r->mac),
2147 sw_r32(priv->r->mac + 4));
2148 strcpy(dev->name, "eth%d");
2149 priv->pdev = pdev;
2150 priv->netdev = dev;
2151
2152 err = rtl838x_mdio_init(priv);
2153 if (err)
2154 goto err_free;
2155
2156 err = register_netdev(dev);
2157 if (err)
2158 goto err_free;
2159
2160 for (i = 0; i < priv->rxrings; i++) {
2161 priv->rx_qs[i].id = i;
2162 priv->rx_qs[i].priv = priv;
2163 netif_napi_add(dev, &priv->rx_qs[i].napi, rtl838x_poll_rx, 64);
2164 }
2165
2166 platform_set_drvdata(pdev, dev);
2167
2168 phy_mode = PHY_INTERFACE_MODE_NA;
2169 err = of_get_phy_mode(dn, &phy_mode);
2170 if (err < 0) {
2171 dev_err(&pdev->dev, "incorrect phy-mode\n");
2172 err = -EINVAL;
2173 goto err_free;
2174 }
2175 priv->phylink_config.dev = &dev->dev;
2176 priv->phylink_config.type = PHYLINK_NETDEV;
2177
2178 phylink = phylink_create(&priv->phylink_config, pdev->dev.fwnode,
2179 phy_mode, &rtl838x_phylink_ops);
2180 if (IS_ERR(phylink)) {
2181 err = PTR_ERR(phylink);
2182 goto err_free;
2183 }
2184 priv->phylink = phylink;
2185
2186 return 0;
2187
2188 err_free:
2189 pr_err("Error setting up netdev, freeing it again.\n");
2190 free_netdev(dev);
2191 return err;
2192 }
2193
2194 static int rtl838x_eth_remove(struct platform_device *pdev)
2195 {
2196 struct net_device *dev = platform_get_drvdata(pdev);
2197 struct rtl838x_eth_priv *priv = netdev_priv(dev);
2198 int i;
2199
2200 if (dev) {
2201 pr_info("Removing platform driver for rtl838x-eth\n");
2202 rtl838x_mdio_remove(priv);
2203 rtl838x_hw_stop(priv);
2204
2205 netif_tx_stop_all_queues(dev);
2206
2207 for (i = 0; i < priv->rxrings; i++)
2208 netif_napi_del(&priv->rx_qs[i].napi);
2209
2210 unregister_netdev(dev);
2211 free_netdev(dev);
2212 }
2213 return 0;
2214 }
2215
2216 static const struct of_device_id rtl838x_eth_of_ids[] = {
2217 { .compatible = "realtek,rtl838x-eth"},
2218 { /* sentinel */ }
2219 };
2220 MODULE_DEVICE_TABLE(of, rtl838x_eth_of_ids);
2221
2222 static struct platform_driver rtl838x_eth_driver = {
2223 .probe = rtl838x_eth_probe,
2224 .remove = rtl838x_eth_remove,
2225 .driver = {
2226 .name = "rtl838x-eth",
2227 .pm = NULL,
2228 .of_match_table = rtl838x_eth_of_ids,
2229 },
2230 };
2231
2232 module_platform_driver(rtl838x_eth_driver);
2233
2234 MODULE_AUTHOR("B. Koblitz");
2235 MODULE_DESCRIPTION("RTL838X SoC Ethernet Driver");
2236 MODULE_LICENSE("GPL");
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