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0e1d64ae691284a6cd0bb888e849dde40ec09e33
[openwrt/openwrt.git] / target / linux / realtek / files-5.15 / drivers / net / dsa / rtl83xx / dsa.c
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <net/dsa.h>
4 #include <linux/etherdevice.h>
5 #include <linux/if_bridge.h>
6 #include <asm/mach-rtl838x/mach-rtl83xx.h>
7
8 #include "rtl83xx.h"
9
10 extern struct rtl83xx_soc_info soc_info;
11
12 static void rtl83xx_init_stats(struct rtl838x_switch_priv *priv)
13 {
14 mutex_lock(&priv->reg_mutex);
15
16 /* Enable statistics module: all counters plus debug.
17 * On RTL839x all counters are enabled by default
18 */
19 if (priv->family_id == RTL8380_FAMILY_ID)
20 sw_w32_mask(0, 3, RTL838X_STAT_CTRL);
21
22 /* Reset statistics counters */
23 sw_w32_mask(0, 1, priv->r->stat_rst);
24
25 mutex_unlock(&priv->reg_mutex);
26 }
27
28 static void rtl83xx_enable_phy_polling(struct rtl838x_switch_priv *priv)
29 {
30 u64 v = 0;
31
32 msleep(1000);
33 /* Enable all ports with a PHY, including the SFP-ports */
34 for (int i = 0; i < priv->cpu_port; i++) {
35 if (priv->ports[i].phy)
36 v |= BIT_ULL(i);
37 }
38
39 pr_info("%s: %16llx\n", __func__, v);
40 priv->r->set_port_reg_le(v, priv->r->smi_poll_ctrl);
41
42 /* PHY update complete, there is no global PHY polling enable bit on the 9300 */
43 if (priv->family_id == RTL8390_FAMILY_ID)
44 sw_w32_mask(0, BIT(7), RTL839X_SMI_GLB_CTRL);
45 else if(priv->family_id == RTL9300_FAMILY_ID)
46 sw_w32_mask(0, 0x8000, RTL838X_SMI_GLB_CTRL);
47 }
48
49 const struct rtl83xx_mib_desc rtl83xx_mib[] = {
50 MIB_DESC(2, 0xf8, "ifInOctets"),
51 MIB_DESC(2, 0xf0, "ifOutOctets"),
52 MIB_DESC(1, 0xec, "dot1dTpPortInDiscards"),
53 MIB_DESC(1, 0xe8, "ifInUcastPkts"),
54 MIB_DESC(1, 0xe4, "ifInMulticastPkts"),
55 MIB_DESC(1, 0xe0, "ifInBroadcastPkts"),
56 MIB_DESC(1, 0xdc, "ifOutUcastPkts"),
57 MIB_DESC(1, 0xd8, "ifOutMulticastPkts"),
58 MIB_DESC(1, 0xd4, "ifOutBroadcastPkts"),
59 MIB_DESC(1, 0xd0, "ifOutDiscards"),
60 MIB_DESC(1, 0xcc, ".3SingleCollisionFrames"),
61 MIB_DESC(1, 0xc8, ".3MultipleCollisionFrames"),
62 MIB_DESC(1, 0xc4, ".3DeferredTransmissions"),
63 MIB_DESC(1, 0xc0, ".3LateCollisions"),
64 MIB_DESC(1, 0xbc, ".3ExcessiveCollisions"),
65 MIB_DESC(1, 0xb8, ".3SymbolErrors"),
66 MIB_DESC(1, 0xb4, ".3ControlInUnknownOpcodes"),
67 MIB_DESC(1, 0xb0, ".3InPauseFrames"),
68 MIB_DESC(1, 0xac, ".3OutPauseFrames"),
69 MIB_DESC(1, 0xa8, "DropEvents"),
70 MIB_DESC(1, 0xa4, "tx_BroadcastPkts"),
71 MIB_DESC(1, 0xa0, "tx_MulticastPkts"),
72 MIB_DESC(1, 0x9c, "CRCAlignErrors"),
73 MIB_DESC(1, 0x98, "tx_UndersizePkts"),
74 MIB_DESC(1, 0x94, "rx_UndersizePkts"),
75 MIB_DESC(1, 0x90, "rx_UndersizedropPkts"),
76 MIB_DESC(1, 0x8c, "tx_OversizePkts"),
77 MIB_DESC(1, 0x88, "rx_OversizePkts"),
78 MIB_DESC(1, 0x84, "Fragments"),
79 MIB_DESC(1, 0x80, "Jabbers"),
80 MIB_DESC(1, 0x7c, "Collisions"),
81 MIB_DESC(1, 0x78, "tx_Pkts64Octets"),
82 MIB_DESC(1, 0x74, "rx_Pkts64Octets"),
83 MIB_DESC(1, 0x70, "tx_Pkts65to127Octets"),
84 MIB_DESC(1, 0x6c, "rx_Pkts65to127Octets"),
85 MIB_DESC(1, 0x68, "tx_Pkts128to255Octets"),
86 MIB_DESC(1, 0x64, "rx_Pkts128to255Octets"),
87 MIB_DESC(1, 0x60, "tx_Pkts256to511Octets"),
88 MIB_DESC(1, 0x5c, "rx_Pkts256to511Octets"),
89 MIB_DESC(1, 0x58, "tx_Pkts512to1023Octets"),
90 MIB_DESC(1, 0x54, "rx_Pkts512to1023Octets"),
91 MIB_DESC(1, 0x50, "tx_Pkts1024to1518Octets"),
92 MIB_DESC(1, 0x4c, "rx_StatsPkts1024to1518Octets"),
93 MIB_DESC(1, 0x48, "tx_Pkts1519toMaxOctets"),
94 MIB_DESC(1, 0x44, "rx_Pkts1519toMaxOctets"),
95 MIB_DESC(1, 0x40, "rxMacDiscards")
96 };
97
98
99 /* DSA callbacks */
100
101
102 static enum dsa_tag_protocol rtl83xx_get_tag_protocol(struct dsa_switch *ds,
103 int port,
104 enum dsa_tag_protocol mprot)
105 {
106 /* The switch does not tag the frames, instead internally the header
107 * structure for each packet is tagged accordingly.
108 */
109 return DSA_TAG_PROTO_TRAILER;
110 }
111
112 /* Initialize all VLANS */
113 static void rtl83xx_vlan_setup(struct rtl838x_switch_priv *priv)
114 {
115 struct rtl838x_vlan_info info;
116
117 pr_info("In %s\n", __func__);
118
119 priv->r->vlan_profile_setup(0);
120 priv->r->vlan_profile_setup(1);
121 pr_info("UNKNOWN_MC_PMASK: %016llx\n", priv->r->read_mcast_pmask(UNKNOWN_MC_PMASK));
122 priv->r->vlan_profile_dump(0);
123
124 info.fid = 0; /* Default Forwarding ID / MSTI */
125 info.hash_uc_fid = false; /* Do not build the L2 lookup hash with FID, but VID */
126 info.hash_mc_fid = false; /* Do the same for Multicast packets */
127 info.profile_id = 0; /* Use default Vlan Profile 0 */
128 info.tagged_ports = 0; /* Initially no port members */
129 if (priv->family_id == RTL9310_FAMILY_ID) {
130 info.if_id = 0;
131 info.multicast_grp_mask = 0;
132 info.l2_tunnel_list_id = -1;
133 }
134
135 /* Initialize all vlans 0-4095 */
136 for (int i = 0; i < MAX_VLANS; i ++)
137 priv->r->vlan_set_tagged(i, &info);
138
139 /* reset PVIDs; defaults to 1 on reset */
140 for (int i = 0; i <= priv->ds->num_ports; i++) {
141 priv->r->vlan_port_pvid_set(i, PBVLAN_TYPE_INNER, 0);
142 priv->r->vlan_port_pvid_set(i, PBVLAN_TYPE_OUTER, 0);
143 priv->r->vlan_port_pvidmode_set(i, PBVLAN_TYPE_INNER, PBVLAN_MODE_UNTAG_AND_PRITAG);
144 priv->r->vlan_port_pvidmode_set(i, PBVLAN_TYPE_OUTER, PBVLAN_MODE_UNTAG_AND_PRITAG);
145 }
146
147 /* Set forwarding action based on inner VLAN tag */
148 for (int i = 0; i < priv->cpu_port; i++)
149 priv->r->vlan_fwd_on_inner(i, true);
150 }
151
152 static void rtl83xx_setup_bpdu_traps(struct rtl838x_switch_priv *priv)
153 {
154 for (int i = 0; i < priv->cpu_port; i++)
155 priv->r->set_receive_management_action(i, BPDU, TRAP2CPU);
156 }
157
158 static void rtl83xx_port_set_salrn(struct rtl838x_switch_priv *priv,
159 int port, bool enable)
160 {
161 int shift = SALRN_PORT_SHIFT(port);
162 int val = enable ? SALRN_MODE_HARDWARE : SALRN_MODE_DISABLED;
163
164 sw_w32_mask(SALRN_MODE_MASK << shift, val << shift,
165 priv->r->l2_port_new_salrn(port));
166 }
167
168 static int rtl83xx_setup(struct dsa_switch *ds)
169 {
170 struct rtl838x_switch_priv *priv = ds->priv;
171
172 pr_debug("%s called\n", __func__);
173
174 /* Disable MAC polling the PHY so that we can start configuration */
175 priv->r->set_port_reg_le(0ULL, priv->r->smi_poll_ctrl);
176
177 for (int i = 0; i < ds->num_ports; i++)
178 priv->ports[i].enable = false;
179 priv->ports[priv->cpu_port].enable = true;
180
181 /* Configure ports so they are disabled by default, but once enabled
182 * they will work in isolated mode (only traffic between port and CPU).
183 */
184 for (int i = 0; i < priv->cpu_port; i++) {
185 if (priv->ports[i].phy) {
186 priv->ports[i].pm = BIT_ULL(priv->cpu_port);
187 priv->r->traffic_set(i, BIT_ULL(i));
188 }
189 }
190 priv->r->traffic_set(priv->cpu_port, BIT_ULL(priv->cpu_port));
191
192 /* For standalone ports, forward packets even if a static fdb
193 * entry for the source address exists on another port.
194 */
195 if (priv->r->set_static_move_action) {
196 for (int i = 0; i <= priv->cpu_port; i++)
197 priv->r->set_static_move_action(i, true);
198 }
199
200 if (priv->family_id == RTL8380_FAMILY_ID)
201 rtl838x_print_matrix();
202 else
203 rtl839x_print_matrix();
204
205 rtl83xx_init_stats(priv);
206
207 rtl83xx_vlan_setup(priv);
208
209 rtl83xx_setup_bpdu_traps(priv);
210
211 ds->configure_vlan_while_not_filtering = true;
212
213 priv->r->l2_learning_setup();
214
215 rtl83xx_port_set_salrn(priv, priv->cpu_port, false);
216 ds->assisted_learning_on_cpu_port = true;
217
218 /* Make sure all frames sent to the switch's MAC are trapped to the CPU-port
219 * 0: FWD, 1: DROP, 2: TRAP2CPU
220 */
221 if (priv->family_id == RTL8380_FAMILY_ID)
222 sw_w32(0x2, RTL838X_SPCL_TRAP_SWITCH_MAC_CTRL);
223 else
224 sw_w32(0x2, RTL839X_SPCL_TRAP_SWITCH_MAC_CTRL);
225
226 /* Enable MAC Polling PHY again */
227 rtl83xx_enable_phy_polling(priv);
228 pr_debug("Please wait until PHY is settled\n");
229 msleep(1000);
230 priv->r->pie_init(priv);
231
232 return 0;
233 }
234
235 static int rtl93xx_setup(struct dsa_switch *ds)
236 {
237 struct rtl838x_switch_priv *priv = ds->priv;
238
239 pr_info("%s called\n", __func__);
240
241 /* Disable MAC polling the PHY so that we can start configuration */
242 if (priv->family_id == RTL9300_FAMILY_ID)
243 sw_w32(0, RTL930X_SMI_POLL_CTRL);
244
245 if (priv->family_id == RTL9310_FAMILY_ID) {
246 sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL);
247 sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL + 4);
248 }
249
250 /* Disable all ports except CPU port */
251 for (int i = 0; i < ds->num_ports; i++)
252 priv->ports[i].enable = false;
253 priv->ports[priv->cpu_port].enable = true;
254
255 /* Configure ports so they are disabled by default, but once enabled
256 * they will work in isolated mode (only traffic between port and CPU).
257 */
258 for (int i = 0; i < priv->cpu_port; i++) {
259 if (priv->ports[i].phy) {
260 priv->ports[i].pm = BIT_ULL(priv->cpu_port);
261 priv->r->traffic_set(i, BIT_ULL(i));
262 }
263 }
264 priv->r->traffic_set(priv->cpu_port, BIT_ULL(priv->cpu_port));
265
266 rtl930x_print_matrix();
267
268 /* TODO: Initialize statistics */
269
270 rtl83xx_vlan_setup(priv);
271
272 ds->configure_vlan_while_not_filtering = true;
273
274 priv->r->l2_learning_setup();
275
276 rtl83xx_port_set_salrn(priv, priv->cpu_port, false);
277 ds->assisted_learning_on_cpu_port = true;
278
279 rtl83xx_enable_phy_polling(priv);
280
281 priv->r->pie_init(priv);
282
283 priv->r->led_init(priv);
284
285 return 0;
286 }
287
288 static int rtl93xx_get_sds(struct phy_device *phydev)
289 {
290 struct device *dev = &phydev->mdio.dev;
291 struct device_node *dn;
292 u32 sds_num;
293
294 if (!dev)
295 return -1;
296 if (dev->of_node) {
297 dn = dev->of_node;
298 if (of_property_read_u32(dn, "sds", &sds_num))
299 sds_num = -1;
300 } else {
301 dev_err(dev, "No DT node.\n");
302 return -1;
303 }
304
305 return sds_num;
306 }
307
308 static void rtl83xx_phylink_validate(struct dsa_switch *ds, int port,
309 unsigned long *supported,
310 struct phylink_link_state *state)
311 {
312 struct rtl838x_switch_priv *priv = ds->priv;
313 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
314
315 pr_debug("In %s port %d, state is %d", __func__, port, state->interface);
316
317 if (!phy_interface_mode_is_rgmii(state->interface) &&
318 state->interface != PHY_INTERFACE_MODE_NA &&
319 state->interface != PHY_INTERFACE_MODE_1000BASEX &&
320 state->interface != PHY_INTERFACE_MODE_MII &&
321 state->interface != PHY_INTERFACE_MODE_REVMII &&
322 state->interface != PHY_INTERFACE_MODE_GMII &&
323 state->interface != PHY_INTERFACE_MODE_QSGMII &&
324 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
325 state->interface != PHY_INTERFACE_MODE_SGMII) {
326 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
327 dev_err(ds->dev,
328 "Unsupported interface: %d for port %d\n",
329 state->interface, port);
330 return;
331 }
332
333 /* Allow all the expected bits */
334 phylink_set(mask, Autoneg);
335 phylink_set_port_modes(mask);
336 phylink_set(mask, Pause);
337 phylink_set(mask, Asym_Pause);
338
339 /* With the exclusion of MII and Reverse MII, we support Gigabit,
340 * including Half duplex
341 */
342 if (state->interface != PHY_INTERFACE_MODE_MII &&
343 state->interface != PHY_INTERFACE_MODE_REVMII) {
344 phylink_set(mask, 1000baseT_Full);
345 phylink_set(mask, 1000baseT_Half);
346 }
347
348 /* On both the 8380 and 8382, ports 24-27 are SFP ports */
349 if (port >= 24 && port <= 27 && priv->family_id == RTL8380_FAMILY_ID)
350 phylink_set(mask, 1000baseX_Full);
351
352 /* On the RTL839x family of SoCs, ports 48 to 51 are SFP ports */
353 if (port >= 48 && port <= 51 && priv->family_id == RTL8390_FAMILY_ID)
354 phylink_set(mask, 1000baseX_Full);
355
356 phylink_set(mask, 10baseT_Half);
357 phylink_set(mask, 10baseT_Full);
358 phylink_set(mask, 100baseT_Half);
359 phylink_set(mask, 100baseT_Full);
360
361 bitmap_and(supported, supported, mask,
362 __ETHTOOL_LINK_MODE_MASK_NBITS);
363 bitmap_and(state->advertising, state->advertising, mask,
364 __ETHTOOL_LINK_MODE_MASK_NBITS);
365 }
366
367 static void rtl93xx_phylink_validate(struct dsa_switch *ds, int port,
368 unsigned long *supported,
369 struct phylink_link_state *state)
370 {
371 struct rtl838x_switch_priv *priv = ds->priv;
372 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
373
374 pr_debug("In %s port %d, state is %d (%s)", __func__, port, state->interface,
375 phy_modes(state->interface));
376
377 if (!phy_interface_mode_is_rgmii(state->interface) &&
378 state->interface != PHY_INTERFACE_MODE_NA &&
379 state->interface != PHY_INTERFACE_MODE_1000BASEX &&
380 state->interface != PHY_INTERFACE_MODE_MII &&
381 state->interface != PHY_INTERFACE_MODE_REVMII &&
382 state->interface != PHY_INTERFACE_MODE_GMII &&
383 state->interface != PHY_INTERFACE_MODE_QSGMII &&
384 state->interface != PHY_INTERFACE_MODE_XGMII &&
385 state->interface != PHY_INTERFACE_MODE_HSGMII &&
386 state->interface != PHY_INTERFACE_MODE_10GBASER &&
387 state->interface != PHY_INTERFACE_MODE_10GKR &&
388 state->interface != PHY_INTERFACE_MODE_USXGMII &&
389 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
390 state->interface != PHY_INTERFACE_MODE_SGMII) {
391 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
392 dev_err(ds->dev,
393 "Unsupported interface: %d for port %d\n",
394 state->interface, port);
395 return;
396 }
397
398 /* Allow all the expected bits */
399 phylink_set(mask, Autoneg);
400 phylink_set_port_modes(mask);
401 phylink_set(mask, Pause);
402 phylink_set(mask, Asym_Pause);
403
404 /* With the exclusion of MII and Reverse MII, we support Gigabit,
405 * including Half duplex
406 */
407 if (state->interface != PHY_INTERFACE_MODE_MII &&
408 state->interface != PHY_INTERFACE_MODE_REVMII) {
409 phylink_set(mask, 1000baseT_Full);
410 phylink_set(mask, 1000baseT_Half);
411 }
412
413 /* Internal phys of the RTL93xx family provide 10G */
414 if (priv->ports[port].phy_is_integrated &&
415 state->interface == PHY_INTERFACE_MODE_1000BASEX) {
416 phylink_set(mask, 1000baseX_Full);
417 } else if (priv->ports[port].phy_is_integrated) {
418 phylink_set(mask, 1000baseX_Full);
419 phylink_set(mask, 10000baseKR_Full);
420 phylink_set(mask, 10000baseSR_Full);
421 phylink_set(mask, 10000baseCR_Full);
422 }
423 if (state->interface == PHY_INTERFACE_MODE_INTERNAL) {
424 phylink_set(mask, 1000baseX_Full);
425 phylink_set(mask, 1000baseT_Full);
426 phylink_set(mask, 10000baseKR_Full);
427 phylink_set(mask, 10000baseT_Full);
428 phylink_set(mask, 10000baseSR_Full);
429 phylink_set(mask, 10000baseCR_Full);
430 }
431
432 if (state->interface == PHY_INTERFACE_MODE_USXGMII) {
433 phylink_set(mask, 2500baseT_Full);
434 phylink_set(mask, 5000baseT_Full);
435 phylink_set(mask, 10000baseT_Full);
436 }
437
438 phylink_set(mask, 10baseT_Half);
439 phylink_set(mask, 10baseT_Full);
440 phylink_set(mask, 100baseT_Half);
441 phylink_set(mask, 100baseT_Full);
442
443 bitmap_and(supported, supported, mask,
444 __ETHTOOL_LINK_MODE_MASK_NBITS);
445 bitmap_and(state->advertising, state->advertising, mask,
446 __ETHTOOL_LINK_MODE_MASK_NBITS);
447 pr_debug("%s leaving supported: %*pb", __func__, __ETHTOOL_LINK_MODE_MASK_NBITS, supported);
448 }
449
450 static int rtl83xx_phylink_mac_link_state(struct dsa_switch *ds, int port,
451 struct phylink_link_state *state)
452 {
453 struct rtl838x_switch_priv *priv = ds->priv;
454 u64 speed;
455 u64 link;
456
457 if (port < 0 || port > priv->cpu_port)
458 return -EINVAL;
459
460 state->link = 0;
461 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
462 if (link & BIT_ULL(port))
463 state->link = 1;
464 pr_debug("%s: link state port %d: %llx\n", __func__, port, link & BIT_ULL(port));
465
466 state->duplex = 0;
467 if (priv->r->get_port_reg_le(priv->r->mac_link_dup_sts) & BIT_ULL(port))
468 state->duplex = 1;
469
470 speed = priv->r->get_port_reg_le(priv->r->mac_link_spd_sts(port));
471 speed >>= (port % 16) << 1;
472 switch (speed & 0x3) {
473 case 0:
474 state->speed = SPEED_10;
475 break;
476 case 1:
477 state->speed = SPEED_100;
478 break;
479 case 2:
480 state->speed = SPEED_1000;
481 break;
482 case 3:
483 if (priv->family_id == RTL9300_FAMILY_ID
484 && (port == 24 || port == 26)) /* Internal serdes */
485 state->speed = SPEED_2500;
486 else
487 state->speed = SPEED_100; /* Is in fact 500Mbit */
488 }
489
490 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
491 if (priv->r->get_port_reg_le(priv->r->mac_rx_pause_sts) & BIT_ULL(port))
492 state->pause |= MLO_PAUSE_RX;
493 if (priv->r->get_port_reg_le(priv->r->mac_tx_pause_sts) & BIT_ULL(port))
494 state->pause |= MLO_PAUSE_TX;
495
496 return 1;
497 }
498
499 static int rtl93xx_phylink_mac_link_state(struct dsa_switch *ds, int port,
500 struct phylink_link_state *state)
501 {
502 struct rtl838x_switch_priv *priv = ds->priv;
503 u64 speed;
504 u64 link;
505 u64 media;
506
507 if (port < 0 || port > priv->cpu_port)
508 return -EINVAL;
509
510 /* On the RTL9300 for at least the RTL8226B PHY, the MAC-side link
511 * state needs to be read twice in order to read a correct result.
512 * This would not be necessary for ports connected e.g. to RTL8218D
513 * PHYs.
514 */
515 state->link = 0;
516 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
517 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
518 if (link & BIT_ULL(port))
519 state->link = 1;
520
521 if (priv->family_id == RTL9310_FAMILY_ID)
522 media = priv->r->get_port_reg_le(RTL931X_MAC_LINK_MEDIA_STS);
523
524 if (priv->family_id == RTL9300_FAMILY_ID)
525 media = sw_r32(RTL930X_MAC_LINK_MEDIA_STS);
526
527 if (media & BIT_ULL(port))
528 state->link = 1;
529
530 pr_debug("%s: link state port %d: %llx, media %llx\n", __func__, port,
531 link & BIT_ULL(port), media);
532
533 state->duplex = 0;
534 if (priv->r->get_port_reg_le(priv->r->mac_link_dup_sts) & BIT_ULL(port))
535 state->duplex = 1;
536
537 speed = priv->r->get_port_reg_le(priv->r->mac_link_spd_sts(port));
538 speed >>= (port % 8) << 2;
539 switch (speed & 0xf) {
540 case 0:
541 state->speed = SPEED_10;
542 break;
543 case 1:
544 state->speed = SPEED_100;
545 break;
546 case 2:
547 case 7:
548 state->speed = SPEED_1000;
549 break;
550 case 4:
551 state->speed = SPEED_10000;
552 break;
553 case 5:
554 case 8:
555 state->speed = SPEED_2500;
556 break;
557 case 6:
558 state->speed = SPEED_5000;
559 break;
560 default:
561 pr_err("%s: unknown speed: %d\n", __func__, (u32)speed & 0xf);
562 }
563
564 if (priv->family_id == RTL9310_FAMILY_ID
565 && (port >= 52 && port <= 55)) { /* Internal serdes */
566 state->speed = SPEED_10000;
567 state->link = 1;
568 state->duplex = 1;
569 }
570
571 pr_debug("%s: speed is: %d %d\n", __func__, (u32)speed & 0xf, state->speed);
572 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
573 if (priv->r->get_port_reg_le(priv->r->mac_rx_pause_sts) & BIT_ULL(port))
574 state->pause |= MLO_PAUSE_RX;
575 if (priv->r->get_port_reg_le(priv->r->mac_tx_pause_sts) & BIT_ULL(port))
576 state->pause |= MLO_PAUSE_TX;
577
578 return 1;
579 }
580
581 static void rtl83xx_config_interface(int port, phy_interface_t interface)
582 {
583 u32 old, int_shift, sds_shift;
584
585 switch (port) {
586 case 24:
587 int_shift = 0;
588 sds_shift = 5;
589 break;
590 case 26:
591 int_shift = 3;
592 sds_shift = 0;
593 break;
594 default:
595 return;
596 }
597
598 old = sw_r32(RTL838X_SDS_MODE_SEL);
599 switch (interface) {
600 case PHY_INTERFACE_MODE_1000BASEX:
601 if ((old >> sds_shift & 0x1f) == 4)
602 return;
603 sw_w32_mask(0x7 << int_shift, 1 << int_shift, RTL838X_INT_MODE_CTRL);
604 sw_w32_mask(0x1f << sds_shift, 4 << sds_shift, RTL838X_SDS_MODE_SEL);
605 break;
606 case PHY_INTERFACE_MODE_SGMII:
607 if ((old >> sds_shift & 0x1f) == 2)
608 return;
609 sw_w32_mask(0x7 << int_shift, 2 << int_shift, RTL838X_INT_MODE_CTRL);
610 sw_w32_mask(0x1f << sds_shift, 2 << sds_shift, RTL838X_SDS_MODE_SEL);
611 break;
612 default:
613 return;
614 }
615 pr_debug("configured port %d for interface %s\n", port, phy_modes(interface));
616 }
617
618 static void rtl83xx_phylink_mac_config(struct dsa_switch *ds, int port,
619 unsigned int mode,
620 const struct phylink_link_state *state)
621 {
622 struct rtl838x_switch_priv *priv = ds->priv;
623 u32 reg;
624 int speed_bit = priv->family_id == RTL8380_FAMILY_ID ? 4 : 3;
625
626 pr_debug("%s port %d, mode %x\n", __func__, port, mode);
627
628 if (port == priv->cpu_port) {
629 /* Set Speed, duplex, flow control
630 * FORCE_EN | LINK_EN | NWAY_EN | DUP_SEL
631 * | SPD_SEL = 0b10 | FORCE_FC_EN | PHY_MASTER_SLV_MANUAL_EN
632 * | MEDIA_SEL
633 */
634 if (priv->family_id == RTL8380_FAMILY_ID) {
635 sw_w32(0x6192F, priv->r->mac_force_mode_ctrl(priv->cpu_port));
636 /* allow CRC errors on CPU-port */
637 sw_w32_mask(0, 0x8, RTL838X_MAC_PORT_CTRL(priv->cpu_port));
638 } else {
639 sw_w32_mask(0, 3, priv->r->mac_force_mode_ctrl(priv->cpu_port));
640 }
641 return;
642 }
643
644 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
645 /* Auto-Negotiation does not work for MAC in RTL8390 */
646 if (priv->family_id == RTL8380_FAMILY_ID) {
647 if (mode == MLO_AN_PHY || phylink_autoneg_inband(mode)) {
648 pr_debug("PHY autonegotiates\n");
649 reg |= RTL838X_NWAY_EN;
650 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
651 rtl83xx_config_interface(port, state->interface);
652 return;
653 }
654 }
655
656 if (mode != MLO_AN_FIXED)
657 pr_debug("Fixed state.\n");
658
659 /* Clear id_mode_dis bit, and the existing port mode, let
660 * RGMII_MODE_EN bet set by mac_link_{up,down} */
661 if (priv->family_id == RTL8380_FAMILY_ID) {
662 reg &= ~(RTL838X_RX_PAUSE_EN | RTL838X_TX_PAUSE_EN);
663 if (state->pause & MLO_PAUSE_TXRX_MASK) {
664 if (state->pause & MLO_PAUSE_TX)
665 reg |= RTL838X_TX_PAUSE_EN;
666 reg |= RTL838X_RX_PAUSE_EN;
667 }
668 } else if (priv->family_id == RTL8390_FAMILY_ID) {
669 reg &= ~(RTL839X_RX_PAUSE_EN | RTL839X_TX_PAUSE_EN);
670 if (state->pause & MLO_PAUSE_TXRX_MASK) {
671 if (state->pause & MLO_PAUSE_TX)
672 reg |= RTL839X_TX_PAUSE_EN;
673 reg |= RTL839X_RX_PAUSE_EN;
674 }
675 }
676
677
678 reg &= ~(3 << speed_bit);
679 switch (state->speed) {
680 case SPEED_1000:
681 reg |= 2 << speed_bit;
682 break;
683 case SPEED_100:
684 reg |= 1 << speed_bit;
685 break;
686 default:
687 break; /* Ignore, including 10MBit which has a speed value of 0 */
688 }
689
690 if (priv->family_id == RTL8380_FAMILY_ID) {
691 reg &= ~(RTL838X_DUPLEX_MODE | RTL838X_FORCE_LINK_EN);
692 if (state->link)
693 reg |= RTL838X_FORCE_LINK_EN;
694 if (state->duplex == RTL838X_DUPLEX_MODE)
695 reg |= RTL838X_DUPLEX_MODE;
696 } else if (priv->family_id == RTL8390_FAMILY_ID) {
697 reg &= ~(RTL839X_DUPLEX_MODE | RTL839X_FORCE_LINK_EN);
698 if (state->link)
699 reg |= RTL839X_FORCE_LINK_EN;
700 if (state->duplex == RTL839X_DUPLEX_MODE)
701 reg |= RTL839X_DUPLEX_MODE;
702 }
703
704 /* LAG members must use DUPLEX and we need to enable the link */
705 if (priv->lagmembers & BIT_ULL(port)) {
706 switch(priv->family_id) {
707 case RTL8380_FAMILY_ID:
708 reg |= (RTL838X_DUPLEX_MODE | RTL838X_FORCE_LINK_EN);
709 break;
710 case RTL8390_FAMILY_ID:
711 reg |= (RTL839X_DUPLEX_MODE | RTL839X_FORCE_LINK_EN);
712 break;
713 }
714 }
715
716 /* Disable AN */
717 if (priv->family_id == RTL8380_FAMILY_ID)
718 reg &= ~RTL838X_NWAY_EN;
719 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
720 }
721
722 static void rtl931x_phylink_mac_config(struct dsa_switch *ds, int port,
723 unsigned int mode,
724 const struct phylink_link_state *state)
725 {
726 struct rtl838x_switch_priv *priv = ds->priv;
727 int sds_num;
728 u32 reg, band;
729
730 sds_num = priv->ports[port].sds_num;
731 pr_info("%s: speed %d sds_num %d\n", __func__, state->speed, sds_num);
732
733 switch (state->interface) {
734 case PHY_INTERFACE_MODE_HSGMII:
735 pr_info("%s setting mode PHY_INTERFACE_MODE_HSGMII\n", __func__);
736 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_HSGMII);
737 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_HSGMII);
738 band = rtl931x_sds_cmu_band_set(sds_num, true, 62, PHY_INTERFACE_MODE_HSGMII);
739 break;
740 case PHY_INTERFACE_MODE_1000BASEX:
741 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_1000BASEX);
742 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_1000BASEX);
743 break;
744 case PHY_INTERFACE_MODE_XGMII:
745 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_XGMII);
746 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_XGMII);
747 break;
748 case PHY_INTERFACE_MODE_10GBASER:
749 case PHY_INTERFACE_MODE_10GKR:
750 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_10GBASER);
751 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_10GBASER);
752 break;
753 case PHY_INTERFACE_MODE_USXGMII:
754 /* Translates to MII_USXGMII_10GSXGMII */
755 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_USXGMII);
756 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_USXGMII);
757 break;
758 case PHY_INTERFACE_MODE_SGMII:
759 pr_info("%s setting mode PHY_INTERFACE_MODE_SGMII\n", __func__);
760 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_SGMII);
761 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_SGMII);
762 band = rtl931x_sds_cmu_band_set(sds_num, true, 62, PHY_INTERFACE_MODE_SGMII);
763 break;
764 case PHY_INTERFACE_MODE_QSGMII:
765 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_QSGMII);
766 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_QSGMII);
767 break;
768 default:
769 pr_err("%s: unknown serdes mode: %s\n",
770 __func__, phy_modes(state->interface));
771 return;
772 }
773
774 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
775 pr_info("%s reading FORCE_MODE_CTRL: %08x\n", __func__, reg);
776
777 reg &= ~(RTL931X_DUPLEX_MODE | RTL931X_FORCE_EN | RTL931X_FORCE_LINK_EN);
778
779 reg &= ~(0xf << 12);
780 reg |= 0x2 << 12; /* Set SMI speed to 0x2 */
781
782 reg |= RTL931X_TX_PAUSE_EN | RTL931X_RX_PAUSE_EN;
783
784 if (priv->lagmembers & BIT_ULL(port))
785 reg |= RTL931X_DUPLEX_MODE;
786
787 if (state->duplex == DUPLEX_FULL)
788 reg |= RTL931X_DUPLEX_MODE;
789
790 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
791
792 }
793
794 static void rtl93xx_phylink_mac_config(struct dsa_switch *ds, int port,
795 unsigned int mode,
796 const struct phylink_link_state *state)
797 {
798 struct rtl838x_switch_priv *priv = ds->priv;
799 int sds_num, sds_mode;
800 u32 reg;
801
802 pr_info("%s port %d, mode %x, phy-mode: %s, speed %d, link %d\n", __func__,
803 port, mode, phy_modes(state->interface), state->speed, state->link);
804
805 /* Nothing to be done for the CPU-port */
806 if (port == priv->cpu_port)
807 return;
808
809 if (priv->family_id == RTL9310_FAMILY_ID)
810 return rtl931x_phylink_mac_config(ds, port, mode, state);
811
812 sds_num = priv->ports[port].sds_num;
813 pr_info("%s SDS is %d\n", __func__, sds_num);
814 if (sds_num >= 0) {
815 switch (state->interface) {
816 case PHY_INTERFACE_MODE_HSGMII:
817 sds_mode = 0x12;
818 break;
819 case PHY_INTERFACE_MODE_1000BASEX:
820 sds_mode = 0x04;
821 break;
822 case PHY_INTERFACE_MODE_XGMII:
823 sds_mode = 0x10;
824 break;
825 case PHY_INTERFACE_MODE_10GBASER:
826 case PHY_INTERFACE_MODE_10GKR:
827 sds_mode = 0x1b; /* 10G 1000X Auto */
828 break;
829 case PHY_INTERFACE_MODE_USXGMII:
830 sds_mode = 0x0d;
831 break;
832 default:
833 pr_err("%s: unknown serdes mode: %s\n",
834 __func__, phy_modes(state->interface));
835 return;
836 }
837 if (state->interface == PHY_INTERFACE_MODE_10GBASER)
838 rtl9300_serdes_setup(sds_num, state->interface);
839 }
840
841 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
842 reg &= ~(0xf << 3);
843
844 switch (state->speed) {
845 case SPEED_10000:
846 reg |= 4 << 3;
847 break;
848 case SPEED_5000:
849 reg |= 6 << 3;
850 break;
851 case SPEED_2500:
852 reg |= 5 << 3;
853 break;
854 case SPEED_1000:
855 reg |= 2 << 3;
856 break;
857 case SPEED_100:
858 reg |= 1 << 3;
859 break;
860 default:
861 /* Also covers 10M */
862 break;
863 }
864
865 if (state->link)
866 reg |= RTL930X_FORCE_LINK_EN;
867
868 if (priv->lagmembers & BIT_ULL(port))
869 reg |= RTL930X_DUPLEX_MODE | RTL930X_FORCE_LINK_EN;
870
871 if (state->duplex == DUPLEX_FULL)
872 reg |= RTL930X_DUPLEX_MODE;
873 else
874 reg &= ~RTL930X_DUPLEX_MODE; /* Clear duplex bit otherwise */
875
876 if (priv->ports[port].phy_is_integrated)
877 reg &= ~RTL930X_FORCE_EN; /* Clear MAC_FORCE_EN to allow SDS-MAC link */
878 else
879 reg |= RTL930X_FORCE_EN;
880
881 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
882 }
883
884 static void rtl83xx_phylink_mac_link_down(struct dsa_switch *ds, int port,
885 unsigned int mode,
886 phy_interface_t interface)
887 {
888 struct rtl838x_switch_priv *priv = ds->priv;
889
890 /* Stop TX/RX to port */
891 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(port));
892
893 /* No longer force link */
894 sw_w32_mask(0x3, 0, priv->r->mac_force_mode_ctrl(port));
895 }
896
897 static void rtl93xx_phylink_mac_link_down(struct dsa_switch *ds, int port,
898 unsigned int mode,
899 phy_interface_t interface)
900 {
901 struct rtl838x_switch_priv *priv = ds->priv;
902 u32 v = 0;
903
904 /* Stop TX/RX to port */
905 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(port));
906
907 /* No longer force link */
908 if (priv->family_id == RTL9300_FAMILY_ID)
909 v = RTL930X_FORCE_EN | RTL930X_FORCE_LINK_EN;
910 else if (priv->family_id == RTL9310_FAMILY_ID)
911 v = RTL931X_FORCE_EN | RTL931X_FORCE_LINK_EN;
912 sw_w32_mask(v, 0, priv->r->mac_force_mode_ctrl(port));
913 }
914
915 static void rtl83xx_phylink_mac_link_up(struct dsa_switch *ds, int port,
916 unsigned int mode,
917 phy_interface_t interface,
918 struct phy_device *phydev,
919 int speed, int duplex,
920 bool tx_pause, bool rx_pause)
921 {
922 struct rtl838x_switch_priv *priv = ds->priv;
923 /* Restart TX/RX to port */
924 sw_w32_mask(0, 0x3, priv->r->mac_port_ctrl(port));
925 /* TODO: Set speed/duplex/pauses */
926 }
927
928 static void rtl93xx_phylink_mac_link_up(struct dsa_switch *ds, int port,
929 unsigned int mode,
930 phy_interface_t interface,
931 struct phy_device *phydev,
932 int speed, int duplex,
933 bool tx_pause, bool rx_pause)
934 {
935 struct rtl838x_switch_priv *priv = ds->priv;
936
937 /* Restart TX/RX to port */
938 sw_w32_mask(0, 0x3, priv->r->mac_port_ctrl(port));
939 /* TODO: Set speed/duplex/pauses */
940 }
941
942 static void rtl83xx_get_strings(struct dsa_switch *ds,
943 int port, u32 stringset, u8 *data)
944 {
945 if (stringset != ETH_SS_STATS)
946 return;
947
948 for (int i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++)
949 ethtool_puts(&data, rtl83xx_mib[i].name);
950 }
951
952 static void rtl83xx_get_ethtool_stats(struct dsa_switch *ds, int port,
953 uint64_t *data)
954 {
955 struct rtl838x_switch_priv *priv = ds->priv;
956 const struct rtl83xx_mib_desc *mib;
957 u64 h;
958
959 for (int i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++) {
960 mib = &rtl83xx_mib[i];
961
962 data[i] = sw_r32(priv->r->stat_port_std_mib + (port << 8) + 252 - mib->offset);
963 if (mib->size == 2) {
964 h = sw_r32(priv->r->stat_port_std_mib + (port << 8) + 248 - mib->offset);
965 data[i] |= h << 32;
966 }
967 }
968 }
969
970 static int rtl83xx_get_sset_count(struct dsa_switch *ds, int port, int sset)
971 {
972 if (sset != ETH_SS_STATS)
973 return 0;
974
975 return ARRAY_SIZE(rtl83xx_mib);
976 }
977
978 static int rtl83xx_mc_group_alloc(struct rtl838x_switch_priv *priv, int port)
979 {
980 int mc_group = find_first_zero_bit(priv->mc_group_bm, MAX_MC_GROUPS - 1);
981 u64 portmask;
982
983 if (mc_group >= MAX_MC_GROUPS - 1)
984 return -1;
985
986 set_bit(mc_group, priv->mc_group_bm);
987 portmask = BIT_ULL(port);
988 priv->r->write_mcast_pmask(mc_group, portmask);
989
990 return mc_group;
991 }
992
993 static u64 rtl83xx_mc_group_add_port(struct rtl838x_switch_priv *priv, int mc_group, int port)
994 {
995 u64 portmask = priv->r->read_mcast_pmask(mc_group);
996
997 pr_debug("%s: %d\n", __func__, port);
998
999 portmask |= BIT_ULL(port);
1000 priv->r->write_mcast_pmask(mc_group, portmask);
1001
1002 return portmask;
1003 }
1004
1005 static u64 rtl83xx_mc_group_del_port(struct rtl838x_switch_priv *priv, int mc_group, int port)
1006 {
1007 u64 portmask = priv->r->read_mcast_pmask(mc_group);
1008
1009 pr_debug("%s: %d\n", __func__, port);
1010
1011 portmask &= ~BIT_ULL(port);
1012 priv->r->write_mcast_pmask(mc_group, portmask);
1013 if (!portmask)
1014 clear_bit(mc_group, priv->mc_group_bm);
1015
1016 return portmask;
1017 }
1018
1019 static int rtl83xx_port_enable(struct dsa_switch *ds, int port,
1020 struct phy_device *phydev)
1021 {
1022 struct rtl838x_switch_priv *priv = ds->priv;
1023 u64 v;
1024
1025 pr_debug("%s: %x %d", __func__, (u32) priv, port);
1026 priv->ports[port].enable = true;
1027
1028 /* enable inner tagging on egress, do not keep any tags */
1029 priv->r->vlan_port_keep_tag_set(port, 0, 1);
1030
1031 if (dsa_is_cpu_port(ds, port))
1032 return 0;
1033
1034 /* add port to switch mask of CPU_PORT */
1035 priv->r->traffic_enable(priv->cpu_port, port);
1036
1037 if (priv->is_lagmember[port]) {
1038 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1039 return 0;
1040 }
1041
1042 /* add all other ports in the same bridge to switch mask of port */
1043 v = priv->r->traffic_get(port);
1044 v |= priv->ports[port].pm;
1045 priv->r->traffic_set(port, v);
1046
1047 /* TODO: Figure out if this is necessary */
1048 if (priv->family_id == RTL9300_FAMILY_ID) {
1049 sw_w32_mask(0, BIT(port), RTL930X_L2_PORT_SABLK_CTRL);
1050 sw_w32_mask(0, BIT(port), RTL930X_L2_PORT_DABLK_CTRL);
1051 }
1052
1053 if (priv->ports[port].sds_num < 0)
1054 priv->ports[port].sds_num = rtl93xx_get_sds(phydev);
1055
1056 return 0;
1057 }
1058
1059 static void rtl83xx_port_disable(struct dsa_switch *ds, int port)
1060 {
1061 struct rtl838x_switch_priv *priv = ds->priv;
1062 u64 v;
1063
1064 pr_debug("%s %x: %d", __func__, (u32)priv, port);
1065 /* you can only disable user ports */
1066 if (!dsa_is_user_port(ds, port))
1067 return;
1068
1069 /* BUG: This does not work on RTL931X */
1070 /* remove port from switch mask of CPU_PORT */
1071 priv->r->traffic_disable(priv->cpu_port, port);
1072
1073 /* remove all other ports in the same bridge from switch mask of port */
1074 v = priv->r->traffic_get(port);
1075 v &= ~priv->ports[port].pm;
1076 priv->r->traffic_set(port, v);
1077
1078 priv->ports[port].enable = false;
1079 }
1080
1081 static int rtl83xx_set_mac_eee(struct dsa_switch *ds, int port,
1082 struct ethtool_eee *e)
1083 {
1084 struct rtl838x_switch_priv *priv = ds->priv;
1085
1086 if (e->eee_enabled && !priv->eee_enabled) {
1087 pr_info("Globally enabling EEE\n");
1088 priv->r->init_eee(priv, true);
1089 }
1090
1091 priv->r->port_eee_set(priv, port, e->eee_enabled);
1092
1093 if (e->eee_enabled)
1094 pr_info("Enabled EEE for port %d\n", port);
1095 else
1096 pr_info("Disabled EEE for port %d\n", port);
1097
1098 return 0;
1099 }
1100
1101 static int rtl83xx_get_mac_eee(struct dsa_switch *ds, int port,
1102 struct ethtool_eee *e)
1103 {
1104 struct rtl838x_switch_priv *priv = ds->priv;
1105
1106 e->supported = SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full;
1107
1108 priv->r->eee_port_ability(priv, e, port);
1109
1110 e->eee_enabled = priv->ports[port].eee_enabled;
1111
1112 e->eee_active = !!(e->advertised & e->lp_advertised);
1113
1114 return 0;
1115 }
1116
1117 static int rtl93xx_get_mac_eee(struct dsa_switch *ds, int port,
1118 struct ethtool_eee *e)
1119 {
1120 struct rtl838x_switch_priv *priv = ds->priv;
1121
1122 e->supported = SUPPORTED_100baseT_Full |
1123 SUPPORTED_1000baseT_Full |
1124 SUPPORTED_2500baseX_Full;
1125
1126 priv->r->eee_port_ability(priv, e, port);
1127
1128 e->eee_enabled = priv->ports[port].eee_enabled;
1129
1130 e->eee_active = !!(e->advertised & e->lp_advertised);
1131
1132 return 0;
1133 }
1134
1135 static int rtl83xx_set_ageing_time(struct dsa_switch *ds, unsigned int msec)
1136 {
1137 struct rtl838x_switch_priv *priv = ds->priv;
1138
1139 priv->r->set_ageing_time(msec);
1140
1141 return 0;
1142 }
1143
1144 static int rtl83xx_port_bridge_join(struct dsa_switch *ds, int port,
1145 struct net_device *bridge)
1146 {
1147 struct rtl838x_switch_priv *priv = ds->priv;
1148 u64 port_bitmap = BIT_ULL(priv->cpu_port), v;
1149
1150 pr_debug("%s %x: %d %llx", __func__, (u32)priv, port, port_bitmap);
1151
1152 if (priv->is_lagmember[port]) {
1153 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1154 return 0;
1155 }
1156
1157 mutex_lock(&priv->reg_mutex);
1158 for (int i = 0; i < ds->num_ports; i++) {
1159 /* Add this port to the port matrix of the other ports in the
1160 * same bridge. If the port is disabled, port matrix is kept
1161 * and not being setup until the port becomes enabled.
1162 */
1163 if (dsa_is_user_port(ds, i) && !priv->is_lagmember[i] && i != port) {
1164 if (dsa_to_port(ds, i)->bridge_dev != bridge)
1165 continue;
1166 if (priv->ports[i].enable)
1167 priv->r->traffic_enable(i, port);
1168
1169 priv->ports[i].pm |= BIT_ULL(port);
1170 port_bitmap |= BIT_ULL(i);
1171 }
1172 }
1173
1174 /* Add all other ports to this port matrix. */
1175 if (priv->ports[port].enable) {
1176 priv->r->traffic_enable(priv->cpu_port, port);
1177 v = priv->r->traffic_get(port);
1178 v |= port_bitmap;
1179 priv->r->traffic_set(port, v);
1180 }
1181 priv->ports[port].pm |= port_bitmap;
1182
1183 if (priv->r->set_static_move_action)
1184 priv->r->set_static_move_action(port, false);
1185
1186 mutex_unlock(&priv->reg_mutex);
1187
1188 return 0;
1189 }
1190
1191 static void rtl83xx_port_bridge_leave(struct dsa_switch *ds, int port,
1192 struct net_device *bridge)
1193 {
1194 struct rtl838x_switch_priv *priv = ds->priv;
1195 u64 port_bitmap = 0, v;
1196
1197 pr_debug("%s %x: %d", __func__, (u32)priv, port);
1198 mutex_lock(&priv->reg_mutex);
1199 for (int i = 0; i < ds->num_ports; i++) {
1200 /* Remove this port from the port matrix of the other ports
1201 * in the same bridge. If the port is disabled, port matrix
1202 * is kept and not being setup until the port becomes enabled.
1203 * And the other port's port matrix cannot be broken when the
1204 * other port is still a VLAN-aware port.
1205 */
1206 if (dsa_is_user_port(ds, i) && i != port) {
1207 if (dsa_to_port(ds, i)->bridge_dev != bridge)
1208 continue;
1209 if (priv->ports[i].enable)
1210 priv->r->traffic_disable(i, port);
1211
1212 priv->ports[i].pm &= ~BIT_ULL(port);
1213 port_bitmap |= BIT_ULL(i);
1214 }
1215 }
1216
1217 /* Remove all other ports from this port matrix. */
1218 if (priv->ports[port].enable) {
1219 v = priv->r->traffic_get(port);
1220 v &= ~port_bitmap;
1221 priv->r->traffic_set(port, v);
1222 }
1223 priv->ports[port].pm &= ~port_bitmap;
1224
1225 if (priv->r->set_static_move_action)
1226 priv->r->set_static_move_action(port, true);
1227
1228 mutex_unlock(&priv->reg_mutex);
1229 }
1230
1231 void rtl83xx_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1232 {
1233 u32 msti = 0;
1234 u32 port_state[4];
1235 int index, bit;
1236 int pos = port;
1237 struct rtl838x_switch_priv *priv = ds->priv;
1238 int n = priv->port_width << 1;
1239
1240 /* Ports above or equal CPU port can never be configured */
1241 if (port >= priv->cpu_port)
1242 return;
1243
1244 mutex_lock(&priv->reg_mutex);
1245
1246 /* For the RTL839x and following, the bits are left-aligned, 838x and 930x
1247 * have 64 bit fields, 839x and 931x have 128 bit fields
1248 */
1249 if (priv->family_id == RTL8390_FAMILY_ID)
1250 pos += 12;
1251 if (priv->family_id == RTL9300_FAMILY_ID)
1252 pos += 3;
1253 if (priv->family_id == RTL9310_FAMILY_ID)
1254 pos += 8;
1255
1256 index = n - (pos >> 4) - 1;
1257 bit = (pos << 1) % 32;
1258
1259 priv->r->stp_get(priv, msti, port_state);
1260
1261 pr_debug("Current state, port %d: %d\n", port, (port_state[index] >> bit) & 3);
1262 port_state[index] &= ~(3 << bit);
1263
1264 switch (state) {
1265 case BR_STATE_DISABLED: /* 0 */
1266 port_state[index] |= (0 << bit);
1267 break;
1268 case BR_STATE_BLOCKING: /* 4 */
1269 case BR_STATE_LISTENING: /* 1 */
1270 port_state[index] |= (1 << bit);
1271 break;
1272 case BR_STATE_LEARNING: /* 2 */
1273 port_state[index] |= (2 << bit);
1274 break;
1275 case BR_STATE_FORWARDING: /* 3 */
1276 port_state[index] |= (3 << bit);
1277 default:
1278 break;
1279 }
1280
1281 priv->r->stp_set(priv, msti, port_state);
1282
1283 mutex_unlock(&priv->reg_mutex);
1284 }
1285
1286 void rtl83xx_fast_age(struct dsa_switch *ds, int port)
1287 {
1288 struct rtl838x_switch_priv *priv = ds->priv;
1289 int s = priv->family_id == RTL8390_FAMILY_ID ? 2 : 0;
1290
1291 pr_debug("FAST AGE port %d\n", port);
1292 mutex_lock(&priv->reg_mutex);
1293 /* RTL838X_L2_TBL_FLUSH_CTRL register bits, 839x has 1 bit larger
1294 * port fields:
1295 * 0-4: Replacing port
1296 * 5-9: Flushed/replaced port
1297 * 10-21: FVID
1298 * 22: Entry types: 1: dynamic, 0: also static
1299 * 23: Match flush port
1300 * 24: Match FVID
1301 * 25: Flush (0) or replace (1) L2 entries
1302 * 26: Status of action (1: Start, 0: Done)
1303 */
1304 sw_w32(1 << (26 + s) | 1 << (23 + s) | port << (5 + (s / 2)), priv->r->l2_tbl_flush_ctrl);
1305
1306 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(26 + s));
1307
1308 mutex_unlock(&priv->reg_mutex);
1309 }
1310
1311 void rtl931x_fast_age(struct dsa_switch *ds, int port)
1312 {
1313 struct rtl838x_switch_priv *priv = ds->priv;
1314
1315 pr_info("%s port %d\n", __func__, port);
1316 mutex_lock(&priv->reg_mutex);
1317 sw_w32(port << 11, RTL931X_L2_TBL_FLUSH_CTRL + 4);
1318
1319 sw_w32(BIT(24) | BIT(28), RTL931X_L2_TBL_FLUSH_CTRL);
1320
1321 do { } while (sw_r32(RTL931X_L2_TBL_FLUSH_CTRL) & BIT (28));
1322
1323 mutex_unlock(&priv->reg_mutex);
1324 }
1325
1326 void rtl930x_fast_age(struct dsa_switch *ds, int port)
1327 {
1328 struct rtl838x_switch_priv *priv = ds->priv;
1329
1330 if (priv->family_id == RTL9310_FAMILY_ID)
1331 return rtl931x_fast_age(ds, port);
1332
1333 pr_debug("FAST AGE port %d\n", port);
1334 mutex_lock(&priv->reg_mutex);
1335 sw_w32(port << 11, RTL930X_L2_TBL_FLUSH_CTRL + 4);
1336
1337 sw_w32(BIT(26) | BIT(30), RTL930X_L2_TBL_FLUSH_CTRL);
1338
1339 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(30));
1340
1341 mutex_unlock(&priv->reg_mutex);
1342 }
1343
1344 static int rtl83xx_vlan_filtering(struct dsa_switch *ds, int port,
1345 bool vlan_filtering,
1346 struct netlink_ext_ack *extack)
1347 {
1348 struct rtl838x_switch_priv *priv = ds->priv;
1349
1350 pr_debug("%s: port %d\n", __func__, port);
1351 mutex_lock(&priv->reg_mutex);
1352
1353 if (vlan_filtering) {
1354 /* Enable ingress and egress filtering
1355 * The VLAN_PORT_IGR_FILTER register uses 2 bits for each port to define
1356 * the filter action:
1357 * 0: Always Forward
1358 * 1: Drop packet
1359 * 2: Trap packet to CPU port
1360 * The Egress filter used 1 bit per state (0: DISABLED, 1: ENABLED)
1361 */
1362 if (port != priv->cpu_port) {
1363 priv->r->set_vlan_igr_filter(port, IGR_DROP);
1364 priv->r->set_vlan_egr_filter(port, EGR_ENABLE);
1365 }
1366 else {
1367 priv->r->set_vlan_igr_filter(port, IGR_TRAP);
1368 priv->r->set_vlan_egr_filter(port, EGR_DISABLE);
1369 }
1370
1371 } else {
1372 /* Disable ingress and egress filtering */
1373 if (port != priv->cpu_port)
1374 priv->r->set_vlan_igr_filter(port, IGR_FORWARD);
1375
1376 priv->r->set_vlan_egr_filter(port, EGR_DISABLE);
1377 }
1378
1379 /* Do we need to do something to the CPU-Port, too? */
1380 mutex_unlock(&priv->reg_mutex);
1381
1382 return 0;
1383 }
1384
1385 static int rtl83xx_vlan_prepare(struct dsa_switch *ds, int port,
1386 const struct switchdev_obj_port_vlan *vlan)
1387 {
1388 struct rtl838x_vlan_info info;
1389 struct rtl838x_switch_priv *priv = ds->priv;
1390
1391 priv->r->vlan_tables_read(0, &info);
1392
1393 pr_debug("VLAN 0: Tagged ports %llx, untag %llx, profile %d, MC# %d, UC# %d, FID %x\n",
1394 info.tagged_ports, info.untagged_ports, info.profile_id,
1395 info.hash_mc_fid, info.hash_uc_fid, info.fid);
1396
1397 priv->r->vlan_tables_read(1, &info);
1398 pr_debug("VLAN 1: Tagged ports %llx, untag %llx, profile %d, MC# %d, UC# %d, FID %x\n",
1399 info.tagged_ports, info.untagged_ports, info.profile_id,
1400 info.hash_mc_fid, info.hash_uc_fid, info.fid);
1401 priv->r->vlan_set_untagged(1, info.untagged_ports);
1402 pr_debug("SET: Untagged ports, VLAN %d: %llx\n", 1, info.untagged_ports);
1403
1404 priv->r->vlan_set_tagged(1, &info);
1405 pr_debug("SET: Tagged ports, VLAN %d: %llx\n", 1, info.tagged_ports);
1406
1407 return 0;
1408 }
1409
1410 static void rtl83xx_vlan_set_pvid(struct rtl838x_switch_priv *priv,
1411 int port, int pvid)
1412 {
1413 /* Set both inner and outer PVID of the port */
1414 priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_INNER, pvid);
1415 priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_OUTER, pvid);
1416 priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_INNER,
1417 PBVLAN_MODE_UNTAG_AND_PRITAG);
1418 priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_OUTER,
1419 PBVLAN_MODE_UNTAG_AND_PRITAG);
1420
1421 priv->ports[port].pvid = pvid;
1422 }
1423
1424 static int rtl83xx_vlan_add(struct dsa_switch *ds, int port,
1425 const struct switchdev_obj_port_vlan *vlan,
1426 struct netlink_ext_ack *extack)
1427 {
1428 struct rtl838x_vlan_info info;
1429 struct rtl838x_switch_priv *priv = ds->priv;
1430 int err;
1431
1432 pr_debug("%s port %d, vid %d, flags %x\n",
1433 __func__, port, vlan->vid, vlan->flags);
1434
1435 if(!vlan->vid) return 0;
1436
1437 if (vlan->vid > 4095) {
1438 dev_err(priv->dev, "VLAN out of range: %d", vlan->vid);
1439 return -ENOTSUPP;
1440 }
1441
1442 err = rtl83xx_vlan_prepare(ds, port, vlan);
1443 if (err)
1444 return err;
1445
1446 mutex_lock(&priv->reg_mutex);
1447
1448 if (vlan->flags & BRIDGE_VLAN_INFO_PVID)
1449 rtl83xx_vlan_set_pvid(priv, port, vlan->vid);
1450 else if (priv->ports[port].pvid == vlan->vid)
1451 rtl83xx_vlan_set_pvid(priv, port, 0);
1452
1453 /* Get port memberships of this vlan */
1454 priv->r->vlan_tables_read(vlan->vid, &info);
1455
1456 /* new VLAN? */
1457 if (!info.tagged_ports) {
1458 info.fid = 0;
1459 info.hash_mc_fid = false;
1460 info.hash_uc_fid = false;
1461 info.profile_id = 0;
1462 }
1463
1464 /* sanitize untagged_ports - must be a subset */
1465 if (info.untagged_ports & ~info.tagged_ports)
1466 info.untagged_ports = 0;
1467
1468 info.tagged_ports |= BIT_ULL(port);
1469 if (vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED)
1470 info.untagged_ports |= BIT_ULL(port);
1471 else
1472 info.untagged_ports &= ~BIT_ULL(port);
1473
1474 priv->r->vlan_set_untagged(vlan->vid, info.untagged_ports);
1475 pr_debug("Untagged ports, VLAN %d: %llx\n", vlan->vid, info.untagged_ports);
1476
1477 priv->r->vlan_set_tagged(vlan->vid, &info);
1478 pr_debug("Tagged ports, VLAN %d: %llx\n", vlan->vid, info.tagged_ports);
1479
1480 mutex_unlock(&priv->reg_mutex);
1481
1482 return 0;
1483 }
1484
1485 static int rtl83xx_vlan_del(struct dsa_switch *ds, int port,
1486 const struct switchdev_obj_port_vlan *vlan)
1487 {
1488 struct rtl838x_vlan_info info;
1489 struct rtl838x_switch_priv *priv = ds->priv;
1490 u16 pvid;
1491
1492 pr_debug("%s: port %d, vid %d, flags %x\n",
1493 __func__, port, vlan->vid, vlan->flags);
1494
1495 if (vlan->vid > 4095) {
1496 dev_err(priv->dev, "VLAN out of range: %d", vlan->vid);
1497 return -ENOTSUPP;
1498 }
1499
1500 mutex_lock(&priv->reg_mutex);
1501 pvid = priv->ports[port].pvid;
1502
1503 /* Reset to default if removing the current PVID */
1504 if (vlan->vid == pvid) {
1505 rtl83xx_vlan_set_pvid(priv, port, 0);
1506 }
1507 /* Get port memberships of this vlan */
1508 priv->r->vlan_tables_read(vlan->vid, &info);
1509
1510 /* remove port from both tables */
1511 info.untagged_ports &= (~BIT_ULL(port));
1512 info.tagged_ports &= (~BIT_ULL(port));
1513
1514 priv->r->vlan_set_untagged(vlan->vid, info.untagged_ports);
1515 pr_debug("Untagged ports, VLAN %d: %llx\n", vlan->vid, info.untagged_ports);
1516
1517 priv->r->vlan_set_tagged(vlan->vid, &info);
1518 pr_debug("Tagged ports, VLAN %d: %llx\n", vlan->vid, info.tagged_ports);
1519
1520 mutex_unlock(&priv->reg_mutex);
1521
1522 return 0;
1523 }
1524
1525 static void rtl83xx_setup_l2_uc_entry(struct rtl838x_l2_entry *e, int port, int vid, u64 mac)
1526 {
1527 memset(e, 0, sizeof(*e));
1528
1529 e->type = L2_UNICAST;
1530 e->valid = true;
1531
1532 e->age = 3;
1533 e->is_static = true;
1534
1535 e->port = port;
1536
1537 e->rvid = e->vid = vid;
1538 e->is_ip_mc = e->is_ipv6_mc = false;
1539 u64_to_ether_addr(mac, e->mac);
1540 }
1541
1542 static void rtl83xx_setup_l2_mc_entry(struct rtl838x_l2_entry *e, int vid, u64 mac, int mc_group)
1543 {
1544 memset(e, 0, sizeof(*e));
1545
1546 e->type = L2_MULTICAST;
1547 e->valid = true;
1548
1549 e->mc_portmask_index = mc_group;
1550
1551 e->rvid = e->vid = vid;
1552 e->is_ip_mc = e->is_ipv6_mc = false;
1553 u64_to_ether_addr(mac, e->mac);
1554 }
1555
1556 /* Uses the seed to identify a hash bucket in the L2 using the derived hash key and then loops
1557 * over the entries in the bucket until either a matching entry is found or an empty slot
1558 * Returns the filled in rtl838x_l2_entry and the index in the bucket when an entry was found
1559 * when an empty slot was found and must exist is false, the index of the slot is returned
1560 * when no slots are available returns -1
1561 */
1562 static int rtl83xx_find_l2_hash_entry(struct rtl838x_switch_priv *priv, u64 seed,
1563 bool must_exist, struct rtl838x_l2_entry *e)
1564 {
1565 int idx = -1;
1566 u32 key = priv->r->l2_hash_key(priv, seed);
1567 u64 entry;
1568
1569 pr_debug("%s: using key %x, for seed %016llx\n", __func__, key, seed);
1570 /* Loop over all entries in the hash-bucket and over the second block on 93xx SoCs */
1571 for (int i = 0; i < priv->l2_bucket_size; i++) {
1572 entry = priv->r->read_l2_entry_using_hash(key, i, e);
1573 pr_debug("valid %d, mac %016llx\n", e->valid, ether_addr_to_u64(&e->mac[0]));
1574 if (must_exist && !e->valid)
1575 continue;
1576 if (!e->valid || ((entry & 0x0fffffffffffffffULL) == seed)) {
1577 idx = i > 3 ? ((key >> 14) & 0xffff) | i >> 1 : ((key << 2) | i) & 0xffff;
1578 break;
1579 }
1580 }
1581
1582 return idx;
1583 }
1584
1585 /* Uses the seed to identify an entry in the CAM by looping over all its entries
1586 * Returns the filled in rtl838x_l2_entry and the index in the CAM when an entry was found
1587 * when an empty slot was found the index of the slot is returned
1588 * when no slots are available returns -1
1589 */
1590 static int rtl83xx_find_l2_cam_entry(struct rtl838x_switch_priv *priv, u64 seed,
1591 bool must_exist, struct rtl838x_l2_entry *e)
1592 {
1593 int idx = -1;
1594 u64 entry;
1595
1596 for (int i = 0; i < 64; i++) {
1597 entry = priv->r->read_cam(i, e);
1598 if (!must_exist && !e->valid) {
1599 if (idx < 0) /* First empty entry? */
1600 idx = i;
1601 break;
1602 } else if ((entry & 0x0fffffffffffffffULL) == seed) {
1603 pr_debug("Found entry in CAM\n");
1604 idx = i;
1605 break;
1606 }
1607 }
1608
1609 return idx;
1610 }
1611
1612 static int rtl83xx_port_fdb_add(struct dsa_switch *ds, int port,
1613 const unsigned char *addr, u16 vid)
1614 {
1615 struct rtl838x_switch_priv *priv = ds->priv;
1616 u64 mac = ether_addr_to_u64(addr);
1617 struct rtl838x_l2_entry e;
1618 int err = 0, idx;
1619 u64 seed = priv->r->l2_hash_seed(mac, vid);
1620
1621 if (priv->is_lagmember[port]) {
1622 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1623 return 0;
1624 }
1625
1626 mutex_lock(&priv->reg_mutex);
1627
1628 idx = rtl83xx_find_l2_hash_entry(priv, seed, false, &e);
1629
1630 /* Found an existing or empty entry */
1631 if (idx >= 0) {
1632 rtl83xx_setup_l2_uc_entry(&e, port, vid, mac);
1633 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1634 goto out;
1635 }
1636
1637 /* Hash buckets full, try CAM */
1638 idx = rtl83xx_find_l2_cam_entry(priv, seed, false, &e);
1639
1640 if (idx >= 0) {
1641 rtl83xx_setup_l2_uc_entry(&e, port, vid, mac);
1642 priv->r->write_cam(idx, &e);
1643 goto out;
1644 }
1645
1646 err = -ENOTSUPP;
1647
1648 out:
1649 mutex_unlock(&priv->reg_mutex);
1650
1651 return err;
1652 }
1653
1654 static int rtl83xx_port_fdb_del(struct dsa_switch *ds, int port,
1655 const unsigned char *addr, u16 vid)
1656 {
1657 struct rtl838x_switch_priv *priv = ds->priv;
1658 u64 mac = ether_addr_to_u64(addr);
1659 struct rtl838x_l2_entry e;
1660 int err = 0, idx;
1661 u64 seed = priv->r->l2_hash_seed(mac, vid);
1662
1663 pr_debug("In %s, mac %llx, vid: %d\n", __func__, mac, vid);
1664 mutex_lock(&priv->reg_mutex);
1665
1666 idx = rtl83xx_find_l2_hash_entry(priv, seed, true, &e);
1667
1668 if (idx >= 0) {
1669 pr_debug("Found entry index %d, key %d and bucket %d\n", idx, idx >> 2, idx & 3);
1670 e.valid = false;
1671 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1672 goto out;
1673 }
1674
1675 /* Check CAM for spillover from hash buckets */
1676 idx = rtl83xx_find_l2_cam_entry(priv, seed, true, &e);
1677
1678 if (idx >= 0) {
1679 e.valid = false;
1680 priv->r->write_cam(idx, &e);
1681 goto out;
1682 }
1683 err = -ENOENT;
1684
1685 out:
1686 mutex_unlock(&priv->reg_mutex);
1687
1688 return err;
1689 }
1690
1691 static int rtl83xx_port_fdb_dump(struct dsa_switch *ds, int port,
1692 dsa_fdb_dump_cb_t *cb, void *data)
1693 {
1694 struct rtl838x_l2_entry e;
1695 struct rtl838x_switch_priv *priv = ds->priv;
1696
1697 mutex_lock(&priv->reg_mutex);
1698
1699 for (int i = 0; i < priv->fib_entries; i++) {
1700 priv->r->read_l2_entry_using_hash(i >> 2, i & 0x3, &e);
1701
1702 if (!e.valid)
1703 continue;
1704
1705 if (e.port == port || e.port == RTL930X_PORT_IGNORE)
1706 cb(e.mac, e.vid, e.is_static, data);
1707
1708 if (!((i + 1) % 64))
1709 cond_resched();
1710 }
1711
1712 for (int i = 0; i < 64; i++) {
1713 priv->r->read_cam(i, &e);
1714
1715 if (!e.valid)
1716 continue;
1717
1718 if (e.port == port)
1719 cb(e.mac, e.vid, e.is_static, data);
1720 }
1721
1722 mutex_unlock(&priv->reg_mutex);
1723
1724 return 0;
1725 }
1726
1727 static int rtl83xx_port_mdb_add(struct dsa_switch *ds, int port,
1728 const struct switchdev_obj_port_mdb *mdb)
1729 {
1730 struct rtl838x_switch_priv *priv = ds->priv;
1731 u64 mac = ether_addr_to_u64(mdb->addr);
1732 struct rtl838x_l2_entry e;
1733 int err = 0, idx;
1734 int vid = mdb->vid;
1735 u64 seed = priv->r->l2_hash_seed(mac, vid);
1736 int mc_group;
1737
1738 if (priv->id >= 0x9300)
1739 return -EOPNOTSUPP;
1740
1741 pr_debug("In %s port %d, mac %llx, vid: %d\n", __func__, port, mac, vid);
1742
1743 if (priv->is_lagmember[port]) {
1744 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1745 return -EINVAL;
1746 }
1747
1748 mutex_lock(&priv->reg_mutex);
1749
1750 idx = rtl83xx_find_l2_hash_entry(priv, seed, false, &e);
1751
1752 /* Found an existing or empty entry */
1753 if (idx >= 0) {
1754 if (e.valid) {
1755 pr_debug("Found an existing entry %016llx, mc_group %d\n",
1756 ether_addr_to_u64(e.mac), e.mc_portmask_index);
1757 rtl83xx_mc_group_add_port(priv, e.mc_portmask_index, port);
1758 } else {
1759 pr_debug("New entry for seed %016llx\n", seed);
1760 mc_group = rtl83xx_mc_group_alloc(priv, port);
1761 if (mc_group < 0) {
1762 err = -ENOTSUPP;
1763 goto out;
1764 }
1765 rtl83xx_setup_l2_mc_entry(&e, vid, mac, mc_group);
1766 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1767 }
1768 goto out;
1769 }
1770
1771 /* Hash buckets full, try CAM */
1772 idx = rtl83xx_find_l2_cam_entry(priv, seed, false, &e);
1773
1774 if (idx >= 0) {
1775 if (e.valid) {
1776 pr_debug("Found existing CAM entry %016llx, mc_group %d\n",
1777 ether_addr_to_u64(e.mac), e.mc_portmask_index);
1778 rtl83xx_mc_group_add_port(priv, e.mc_portmask_index, port);
1779 } else {
1780 pr_debug("New entry\n");
1781 mc_group = rtl83xx_mc_group_alloc(priv, port);
1782 if (mc_group < 0) {
1783 err = -ENOTSUPP;
1784 goto out;
1785 }
1786 rtl83xx_setup_l2_mc_entry(&e, vid, mac, mc_group);
1787 priv->r->write_cam(idx, &e);
1788 }
1789 goto out;
1790 }
1791
1792 err = -ENOTSUPP;
1793
1794 out:
1795 mutex_unlock(&priv->reg_mutex);
1796 if (err)
1797 dev_err(ds->dev, "failed to add MDB entry\n");
1798
1799 return err;
1800 }
1801
1802 int rtl83xx_port_mdb_del(struct dsa_switch *ds, int port,
1803 const struct switchdev_obj_port_mdb *mdb)
1804 {
1805 struct rtl838x_switch_priv *priv = ds->priv;
1806 u64 mac = ether_addr_to_u64(mdb->addr);
1807 struct rtl838x_l2_entry e;
1808 int err = 0, idx;
1809 int vid = mdb->vid;
1810 u64 seed = priv->r->l2_hash_seed(mac, vid);
1811 u64 portmask;
1812
1813 pr_debug("In %s, port %d, mac %llx, vid: %d\n", __func__, port, mac, vid);
1814
1815 if (priv->is_lagmember[port]) {
1816 pr_info("%s: %d is lag slave. ignore\n", __func__, port);
1817 return 0;
1818 }
1819
1820 mutex_lock(&priv->reg_mutex);
1821
1822 idx = rtl83xx_find_l2_hash_entry(priv, seed, true, &e);
1823
1824 if (idx >= 0) {
1825 pr_debug("Found entry index %d, key %d and bucket %d\n", idx, idx >> 2, idx & 3);
1826 portmask = rtl83xx_mc_group_del_port(priv, e.mc_portmask_index, port);
1827 if (!portmask) {
1828 e.valid = false;
1829 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1830 }
1831 goto out;
1832 }
1833
1834 /* Check CAM for spillover from hash buckets */
1835 idx = rtl83xx_find_l2_cam_entry(priv, seed, true, &e);
1836
1837 if (idx >= 0) {
1838 portmask = rtl83xx_mc_group_del_port(priv, e.mc_portmask_index, port);
1839 if (!portmask) {
1840 e.valid = false;
1841 priv->r->write_cam(idx, &e);
1842 }
1843 goto out;
1844 }
1845 /* TODO: Re-enable with a newer kernel: err = -ENOENT; */
1846
1847 out:
1848 mutex_unlock(&priv->reg_mutex);
1849
1850 return err;
1851 }
1852
1853 static int rtl83xx_port_mirror_add(struct dsa_switch *ds, int port,
1854 struct dsa_mall_mirror_tc_entry *mirror,
1855 bool ingress)
1856 {
1857 /* We support 4 mirror groups, one destination port per group */
1858 int group;
1859 struct rtl838x_switch_priv *priv = ds->priv;
1860 int ctrl_reg, dpm_reg, spm_reg;
1861
1862 pr_debug("In %s\n", __func__);
1863
1864 for (group = 0; group < 4; group++) {
1865 if (priv->mirror_group_ports[group] == mirror->to_local_port)
1866 break;
1867 }
1868 if (group >= 4) {
1869 for (group = 0; group < 4; group++) {
1870 if (priv->mirror_group_ports[group] < 0)
1871 break;
1872 }
1873 }
1874
1875 if (group >= 4)
1876 return -ENOSPC;
1877
1878 ctrl_reg = priv->r->mir_ctrl + group * 4;
1879 dpm_reg = priv->r->mir_dpm + group * 4 * priv->port_width;
1880 spm_reg = priv->r->mir_spm + group * 4 * priv->port_width;
1881
1882 pr_debug("Using group %d\n", group);
1883 mutex_lock(&priv->reg_mutex);
1884
1885 if (priv->family_id == RTL8380_FAMILY_ID) {
1886 /* Enable mirroring to port across VLANs (bit 11) */
1887 sw_w32(1 << 11 | (mirror->to_local_port << 4) | 1, ctrl_reg);
1888 } else {
1889 /* Enable mirroring to destination port */
1890 sw_w32((mirror->to_local_port << 4) | 1, ctrl_reg);
1891 }
1892
1893 if (ingress && (priv->r->get_port_reg_be(spm_reg) & (1ULL << port))) {
1894 mutex_unlock(&priv->reg_mutex);
1895 return -EEXIST;
1896 }
1897 if ((!ingress) && (priv->r->get_port_reg_be(dpm_reg) & (1ULL << port))) {
1898 mutex_unlock(&priv->reg_mutex);
1899 return -EEXIST;
1900 }
1901
1902 if (ingress)
1903 priv->r->mask_port_reg_be(0, 1ULL << port, spm_reg);
1904 else
1905 priv->r->mask_port_reg_be(0, 1ULL << port, dpm_reg);
1906
1907 priv->mirror_group_ports[group] = mirror->to_local_port;
1908 mutex_unlock(&priv->reg_mutex);
1909
1910 return 0;
1911 }
1912
1913 static void rtl83xx_port_mirror_del(struct dsa_switch *ds, int port,
1914 struct dsa_mall_mirror_tc_entry *mirror)
1915 {
1916 int group = 0;
1917 struct rtl838x_switch_priv *priv = ds->priv;
1918 int ctrl_reg, dpm_reg, spm_reg;
1919
1920 pr_debug("In %s\n", __func__);
1921 for (group = 0; group < 4; group++) {
1922 if (priv->mirror_group_ports[group] == mirror->to_local_port)
1923 break;
1924 }
1925 if (group >= 4)
1926 return;
1927
1928 ctrl_reg = priv->r->mir_ctrl + group * 4;
1929 dpm_reg = priv->r->mir_dpm + group * 4 * priv->port_width;
1930 spm_reg = priv->r->mir_spm + group * 4 * priv->port_width;
1931
1932 mutex_lock(&priv->reg_mutex);
1933 if (mirror->ingress) {
1934 /* Ingress, clear source port matrix */
1935 priv->r->mask_port_reg_be(1ULL << port, 0, spm_reg);
1936 } else {
1937 /* Egress, clear destination port matrix */
1938 priv->r->mask_port_reg_be(1ULL << port, 0, dpm_reg);
1939 }
1940
1941 if (!(sw_r32(spm_reg) || sw_r32(dpm_reg))) {
1942 priv->mirror_group_ports[group] = -1;
1943 sw_w32(0, ctrl_reg);
1944 }
1945
1946 mutex_unlock(&priv->reg_mutex);
1947 }
1948
1949 static int rtl83xx_port_pre_bridge_flags(struct dsa_switch *ds, int port, struct switchdev_brport_flags flags, struct netlink_ext_ack *extack)
1950 {
1951 struct rtl838x_switch_priv *priv = ds->priv;
1952 unsigned long features = 0;
1953 pr_debug("%s: %d %lX\n", __func__, port, flags.val);
1954 if (priv->r->enable_learning)
1955 features |= BR_LEARNING;
1956 if (priv->r->enable_flood)
1957 features |= BR_FLOOD;
1958 if (priv->r->enable_mcast_flood)
1959 features |= BR_MCAST_FLOOD;
1960 if (priv->r->enable_bcast_flood)
1961 features |= BR_BCAST_FLOOD;
1962 if (flags.mask & ~(features))
1963 return -EINVAL;
1964
1965 return 0;
1966 }
1967
1968 static int rtl83xx_port_bridge_flags(struct dsa_switch *ds, int port, struct switchdev_brport_flags flags, struct netlink_ext_ack *extack)
1969 {
1970 struct rtl838x_switch_priv *priv = ds->priv;
1971
1972 pr_debug("%s: %d %lX\n", __func__, port, flags.val);
1973 if (priv->r->enable_learning && (flags.mask & BR_LEARNING))
1974 priv->r->enable_learning(port, !!(flags.val & BR_LEARNING));
1975
1976 if (priv->r->enable_flood && (flags.mask & BR_FLOOD))
1977 priv->r->enable_flood(port, !!(flags.val & BR_FLOOD));
1978
1979 if (priv->r->enable_mcast_flood && (flags.mask & BR_MCAST_FLOOD))
1980 priv->r->enable_mcast_flood(port, !!(flags.val & BR_MCAST_FLOOD));
1981
1982 if (priv->r->enable_bcast_flood && (flags.mask & BR_BCAST_FLOOD))
1983 priv->r->enable_bcast_flood(port, !!(flags.val & BR_BCAST_FLOOD));
1984
1985 return 0;
1986 }
1987
1988 static bool rtl83xx_lag_can_offload(struct dsa_switch *ds,
1989 struct net_device *lag,
1990 struct netdev_lag_upper_info *info)
1991 {
1992 int id;
1993
1994 id = dsa_lag_id(ds->dst, lag);
1995 if (id < 0 || id >= ds->num_lag_ids)
1996 return false;
1997
1998 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
1999 return false;
2000 }
2001 if (info->hash_type != NETDEV_LAG_HASH_L2 && info->hash_type != NETDEV_LAG_HASH_L23)
2002 return false;
2003
2004 return true;
2005 }
2006
2007 static int rtl83xx_port_lag_change(struct dsa_switch *ds, int port)
2008 {
2009 pr_debug("%s: %d\n", __func__, port);
2010 /* Nothing to be done... */
2011
2012 return 0;
2013 }
2014
2015 static int rtl83xx_port_lag_join(struct dsa_switch *ds, int port,
2016 struct net_device *lag,
2017 struct netdev_lag_upper_info *info)
2018 {
2019 struct rtl838x_switch_priv *priv = ds->priv;
2020 int i, err = 0;
2021
2022 if (!rtl83xx_lag_can_offload(ds, lag, info))
2023 return -EOPNOTSUPP;
2024
2025 mutex_lock(&priv->reg_mutex);
2026
2027 for (i = 0; i < priv->n_lags; i++) {
2028 if ((!priv->lag_devs[i]) || (priv->lag_devs[i] == lag))
2029 break;
2030 }
2031 if (port >= priv->cpu_port) {
2032 err = -EINVAL;
2033 goto out;
2034 }
2035 pr_info("port_lag_join: group %d, port %d\n",i, port);
2036 if (!priv->lag_devs[i])
2037 priv->lag_devs[i] = lag;
2038
2039 if (priv->lag_primary[i] == -1) {
2040 priv->lag_primary[i] = port;
2041 } else
2042 priv->is_lagmember[port] = 1;
2043
2044 priv->lagmembers |= (1ULL << port);
2045
2046 pr_debug("lag_members = %llX\n", priv->lagmembers);
2047 err = rtl83xx_lag_add(priv->ds, i, port, info);
2048 if (err) {
2049 err = -EINVAL;
2050 goto out;
2051 }
2052
2053 out:
2054 mutex_unlock(&priv->reg_mutex);
2055
2056 return err;
2057 }
2058
2059 static int rtl83xx_port_lag_leave(struct dsa_switch *ds, int port,
2060 struct net_device *lag)
2061 {
2062 int i, group = -1, err;
2063 struct rtl838x_switch_priv *priv = ds->priv;
2064
2065 mutex_lock(&priv->reg_mutex);
2066 for (i = 0; i < priv->n_lags; i++) {
2067 if (priv->lags_port_members[i] & BIT_ULL(port)) {
2068 group = i;
2069 break;
2070 }
2071 }
2072
2073 if (group == -1) {
2074 pr_info("port_lag_leave: port %d is not a member\n", port);
2075 err = -EINVAL;
2076 goto out;
2077 }
2078
2079 if (port >= priv->cpu_port) {
2080 err = -EINVAL;
2081 goto out;
2082 }
2083 pr_info("port_lag_del: group %d, port %d\n",group, port);
2084 priv->lagmembers &=~ (1ULL << port);
2085 priv->lag_primary[i] = -1;
2086 priv->is_lagmember[port] = 0;
2087 pr_debug("lag_members = %llX\n", priv->lagmembers);
2088 err = rtl83xx_lag_del(priv->ds, group, port);
2089 if (err) {
2090 err = -EINVAL;
2091 goto out;
2092 }
2093 if (!priv->lags_port_members[i])
2094 priv->lag_devs[i] = NULL;
2095
2096 out:
2097 mutex_unlock(&priv->reg_mutex);
2098 return 0;
2099 }
2100
2101 int dsa_phy_read(struct dsa_switch *ds, int phy_addr, int phy_reg)
2102 {
2103 u32 val;
2104 u32 offset = 0;
2105 struct rtl838x_switch_priv *priv = ds->priv;
2106
2107 if ((phy_addr >= 24) &&
2108 (phy_addr <= 27) &&
2109 (priv->ports[24].phy == PHY_RTL838X_SDS)) {
2110 if (phy_addr == 26)
2111 offset = 0x100;
2112 val = sw_r32(RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2)) & 0xffff;
2113 return val;
2114 }
2115
2116 read_phy(phy_addr, 0, phy_reg, &val);
2117 return val;
2118 }
2119
2120 int dsa_phy_write(struct dsa_switch *ds, int phy_addr, int phy_reg, u16 val)
2121 {
2122 u32 offset = 0;
2123 struct rtl838x_switch_priv *priv = ds->priv;
2124
2125 if ((phy_addr >= 24) &&
2126 (phy_addr <= 27) &&
2127 (priv->ports[24].phy == PHY_RTL838X_SDS)) {
2128 if (phy_addr == 26)
2129 offset = 0x100;
2130 sw_w32(val, RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2));
2131 return 0;
2132 }
2133 return write_phy(phy_addr, 0, phy_reg, val);
2134 }
2135
2136 const struct dsa_switch_ops rtl83xx_switch_ops = {
2137 .get_tag_protocol = rtl83xx_get_tag_protocol,
2138 .setup = rtl83xx_setup,
2139
2140 .phy_read = dsa_phy_read,
2141 .phy_write = dsa_phy_write,
2142
2143 .phylink_validate = rtl83xx_phylink_validate,
2144 .phylink_mac_link_state = rtl83xx_phylink_mac_link_state,
2145 .phylink_mac_config = rtl83xx_phylink_mac_config,
2146 .phylink_mac_link_down = rtl83xx_phylink_mac_link_down,
2147 .phylink_mac_link_up = rtl83xx_phylink_mac_link_up,
2148
2149 .get_strings = rtl83xx_get_strings,
2150 .get_ethtool_stats = rtl83xx_get_ethtool_stats,
2151 .get_sset_count = rtl83xx_get_sset_count,
2152
2153 .port_enable = rtl83xx_port_enable,
2154 .port_disable = rtl83xx_port_disable,
2155
2156 .get_mac_eee = rtl83xx_get_mac_eee,
2157 .set_mac_eee = rtl83xx_set_mac_eee,
2158
2159 .set_ageing_time = rtl83xx_set_ageing_time,
2160 .port_bridge_join = rtl83xx_port_bridge_join,
2161 .port_bridge_leave = rtl83xx_port_bridge_leave,
2162 .port_stp_state_set = rtl83xx_port_stp_state_set,
2163 .port_fast_age = rtl83xx_fast_age,
2164
2165 .port_vlan_filtering = rtl83xx_vlan_filtering,
2166 .port_vlan_add = rtl83xx_vlan_add,
2167 .port_vlan_del = rtl83xx_vlan_del,
2168
2169 .port_fdb_add = rtl83xx_port_fdb_add,
2170 .port_fdb_del = rtl83xx_port_fdb_del,
2171 .port_fdb_dump = rtl83xx_port_fdb_dump,
2172
2173 .port_mdb_add = rtl83xx_port_mdb_add,
2174 .port_mdb_del = rtl83xx_port_mdb_del,
2175
2176 .port_mirror_add = rtl83xx_port_mirror_add,
2177 .port_mirror_del = rtl83xx_port_mirror_del,
2178
2179 .port_lag_change = rtl83xx_port_lag_change,
2180 .port_lag_join = rtl83xx_port_lag_join,
2181 .port_lag_leave = rtl83xx_port_lag_leave,
2182
2183 .port_pre_bridge_flags = rtl83xx_port_pre_bridge_flags,
2184 .port_bridge_flags = rtl83xx_port_bridge_flags,
2185 };
2186
2187 const struct dsa_switch_ops rtl930x_switch_ops = {
2188 .get_tag_protocol = rtl83xx_get_tag_protocol,
2189 .setup = rtl93xx_setup,
2190
2191 .phy_read = dsa_phy_read,
2192 .phy_write = dsa_phy_write,
2193
2194 .phylink_validate = rtl93xx_phylink_validate,
2195 .phylink_mac_link_state = rtl93xx_phylink_mac_link_state,
2196 .phylink_mac_config = rtl93xx_phylink_mac_config,
2197 .phylink_mac_link_down = rtl93xx_phylink_mac_link_down,
2198 .phylink_mac_link_up = rtl93xx_phylink_mac_link_up,
2199
2200 .get_strings = rtl83xx_get_strings,
2201 .get_ethtool_stats = rtl83xx_get_ethtool_stats,
2202 .get_sset_count = rtl83xx_get_sset_count,
2203
2204 .port_enable = rtl83xx_port_enable,
2205 .port_disable = rtl83xx_port_disable,
2206
2207 .get_mac_eee = rtl93xx_get_mac_eee,
2208 .set_mac_eee = rtl83xx_set_mac_eee,
2209
2210 .set_ageing_time = rtl83xx_set_ageing_time,
2211 .port_bridge_join = rtl83xx_port_bridge_join,
2212 .port_bridge_leave = rtl83xx_port_bridge_leave,
2213 .port_stp_state_set = rtl83xx_port_stp_state_set,
2214 .port_fast_age = rtl930x_fast_age,
2215
2216 .port_vlan_filtering = rtl83xx_vlan_filtering,
2217 .port_vlan_add = rtl83xx_vlan_add,
2218 .port_vlan_del = rtl83xx_vlan_del,
2219
2220 .port_fdb_add = rtl83xx_port_fdb_add,
2221 .port_fdb_del = rtl83xx_port_fdb_del,
2222 .port_fdb_dump = rtl83xx_port_fdb_dump,
2223
2224 .port_mdb_add = rtl83xx_port_mdb_add,
2225 .port_mdb_del = rtl83xx_port_mdb_del,
2226
2227 .port_lag_change = rtl83xx_port_lag_change,
2228 .port_lag_join = rtl83xx_port_lag_join,
2229 .port_lag_leave = rtl83xx_port_lag_leave,
2230
2231 .port_pre_bridge_flags = rtl83xx_port_pre_bridge_flags,
2232 .port_bridge_flags = rtl83xx_port_bridge_flags,
2233 };
OpenWrt Source Repository