1 // SPDX-License-Identifier: GPL-2.0-only
3 #ifndef _RTL83XX_IRQ_H_
4 #define _RTL83XX_IRQ_H_
9 /* Global Interrupt Mask Register */
10 #define RTL83XX_ICTL_GIMR 0x00
11 /* Global Interrupt Status Register */
12 #define RTL83XX_ICTL_GISR 0x04
14 #define RTL83XX_IRQ_CPU_BASE 0
15 #define RTL83XX_IRQ_CPU_NUM 8
16 #define RTL83XX_IRQ_ICTL_BASE (RTL83XX_IRQ_CPU_BASE + RTL83XX_IRQ_CPU_NUM)
17 #define RTL83XX_IRQ_ICTL_NUM 32
19 /* Cascaded interrupts */
20 #define RTL83XX_ICTL1_IRQ (RTL83XX_IRQ_CPU_BASE + 2)
21 #define RTL83XX_ICTL2_IRQ (RTL83XX_IRQ_CPU_BASE + 3)
22 #define RTL83XX_ICTL3_IRQ (RTL83XX_IRQ_CPU_BASE + 4)
23 #define RTL83XX_ICTL4_IRQ (RTL83XX_IRQ_CPU_BASE + 5)
24 #define RTL83XX_ICTL5_IRQ (RTL83XX_IRQ_CPU_BASE + 6)
26 /* Interrupt routing register */
27 #define RTL83XX_IRR0 0x08
28 #define RTL83XX_IRR1 0x0c
29 #define RTL83XX_IRR2 0x10
30 #define RTL83XX_IRR3 0x14
33 #define UART0_CASCADE 2
34 #define UART1_CASCADE 1
37 #define OCPTO_CASCADE 1
38 #define HLXTO_CASCADE 1
39 #define SLXTO_CASCADE 1
41 #define GPIO_ABCD_CASCADE 4
42 #define GPIO_EFGH_CASCADE 4
44 #define SWCORE_CASCADE 3
45 #define WDT_IP1_CASCADE 4
46 #define WDT_IP2_CASCADE 5
48 /* Pack cascade map into interrupt routing registers */
49 #define RTL83XX_IRR0_SETTING (\
50 (UART0_CASCADE << 28) | \
51 (UART1_CASCADE << 24) | \
52 (TC0_CASCADE << 20) | \
53 (TC1_CASCADE << 16) | \
54 (OCPTO_CASCADE << 12) | \
55 (HLXTO_CASCADE << 8) | \
56 (SLXTO_CASCADE << 4) | \
58 #define RTL83XX_IRR1_SETTING (\
59 (GPIO_ABCD_CASCADE << 28) | \
60 (GPIO_EFGH_CASCADE << 24) | \
61 (RTC_CASCADE << 20) | \
62 (SWCORE_CASCADE << 16))
63 #define RTL83XX_IRR2_SETTING 0
64 #define RTL83XX_IRR3_SETTING 0
66 #endif /* _RTL83XX_IRQ_H_ */