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[openwrt/staging/mkresin.git] / target / linux / realtek / files-5.4 / drivers / net / dsa / rtl83xx / rtl839x.c
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <asm/mach-rtl838x/mach-rtl83xx.h>
4 #include "rtl83xx.h"
5
6 extern struct mutex smi_lock;
7 extern struct rtl83xx_soc_info soc_info;
8
9 void rtl839x_print_matrix(void)
10 {
11 volatile u64 *ptr9;
12 int i;
13
14 ptr9 = RTL838X_SW_BASE + RTL839X_PORT_ISO_CTRL(0);
15 for (i = 0; i < 52; i += 4)
16 pr_debug("> %16llx %16llx %16llx %16llx\n",
17 ptr9[i + 0], ptr9[i + 1], ptr9[i + 2], ptr9[i + 3]);
18 pr_debug("CPU_PORT> %16llx\n", ptr9[52]);
19 }
20
21 static inline int rtl839x_port_iso_ctrl(int p)
22 {
23 return RTL839X_PORT_ISO_CTRL(p);
24 }
25
26 static inline void rtl839x_exec_tbl0_cmd(u32 cmd)
27 {
28 sw_w32(cmd, RTL839X_TBL_ACCESS_CTRL_0);
29 do { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_0) & BIT(16));
30 }
31
32 static inline void rtl839x_exec_tbl1_cmd(u32 cmd)
33 {
34 sw_w32(cmd, RTL839X_TBL_ACCESS_CTRL_1);
35 do { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_1) & BIT(16));
36 }
37
38 inline void rtl839x_exec_tbl2_cmd(u32 cmd)
39 {
40 sw_w32(cmd, RTL839X_TBL_ACCESS_CTRL_2);
41 do { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_2) & (1 << 9));
42 }
43
44 static inline int rtl839x_tbl_access_data_0(int i)
45 {
46 return RTL839X_TBL_ACCESS_DATA_0(i);
47 }
48
49 static void rtl839x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info)
50 {
51 u32 u, v, w;
52 // Read VLAN table (0) via register 0
53 struct table_reg *r = rtl_table_get(RTL8390_TBL_0, 0);
54
55 rtl_table_read(r, vlan);
56 u = sw_r32(rtl_table_data(r, 0));
57 v = sw_r32(rtl_table_data(r, 1));
58 w = sw_r32(rtl_table_data(r, 2));
59 rtl_table_release(r);
60
61 info->tagged_ports = u;
62 info->tagged_ports = (info->tagged_ports << 21) | ((v >> 11) & 0x1fffff);
63 info->profile_id = w >> 30 | ((v & 1) << 2);
64 info->hash_mc_fid = !!(w & BIT(2));
65 info->hash_uc_fid = !!(w & BIT(3));
66 info->fid = (v >> 3) & 0xff;
67
68 // Read UNTAG table (0) via table register 1
69 r = rtl_table_get(RTL8390_TBL_1, 0);
70 rtl_table_read(r, vlan);
71 u = sw_r32(rtl_table_data(r, 0));
72 v = sw_r32(rtl_table_data(r, 1));
73 rtl_table_release(r);
74
75 info->untagged_ports = u;
76 info->untagged_ports = (info->untagged_ports << 21) | ((v >> 11) & 0x1fffff);
77 }
78
79 static void rtl839x_vlan_set_tagged(u32 vlan, struct rtl838x_vlan_info *info)
80 {
81 u32 u, v, w;
82 // Access VLAN table (0) via register 0
83 struct table_reg *r = rtl_table_get(RTL8390_TBL_0, 0);
84
85 u = info->tagged_ports >> 21;
86 v = info->tagged_ports << 11;
87 v |= ((u32)info->fid) << 3;
88 v |= info->hash_uc_fid ? BIT(2) : 0;
89 v |= info->hash_mc_fid ? BIT(1) : 0;
90 v |= (info->profile_id & 0x4) ? 1 : 0;
91 w = ((u32)(info->profile_id & 3)) << 30;
92
93 sw_w32(u, rtl_table_data(r, 0));
94 sw_w32(v, rtl_table_data(r, 1));
95 sw_w32(w, rtl_table_data(r, 2));
96
97 rtl_table_write(r, vlan);
98 rtl_table_release(r);
99 }
100
101 static void rtl839x_vlan_set_untagged(u32 vlan, u64 portmask)
102 {
103 u32 u, v;
104
105 // Access UNTAG table (0) via table register 1
106 struct table_reg *r = rtl_table_get(RTL8390_TBL_1, 0);
107
108 u = portmask >> 21;
109 v = portmask << 11;
110
111 sw_w32(u, rtl_table_data(r, 0));
112 sw_w32(v, rtl_table_data(r, 1));
113 rtl_table_write(r, vlan);
114
115 rtl_table_release(r);
116 }
117
118 /* Sets the L2 forwarding to be based on either the inner VLAN tag or the outer
119 */
120 static void rtl839x_vlan_fwd_on_inner(int port, bool is_set)
121 {
122 if (is_set)
123 rtl839x_mask_port_reg_be(BIT_ULL(port), 0ULL, RTL839X_VLAN_PORT_FWD);
124 else
125 rtl839x_mask_port_reg_be(0ULL, BIT_ULL(port), RTL839X_VLAN_PORT_FWD);
126 }
127
128 static inline int rtl839x_mac_force_mode_ctrl(int p)
129 {
130 return RTL839X_MAC_FORCE_MODE_CTRL + (p << 2);
131 }
132
133 static inline int rtl839x_mac_port_ctrl(int p)
134 {
135 return RTL839X_MAC_PORT_CTRL(p);
136 }
137
138 static inline int rtl839x_l2_port_new_salrn(int p)
139 {
140 return RTL839X_L2_PORT_NEW_SALRN(p);
141 }
142
143 static inline int rtl839x_l2_port_new_sa_fwd(int p)
144 {
145 return RTL839X_L2_PORT_NEW_SA_FWD(p);
146 }
147
148 static inline int rtl839x_mac_link_spd_sts(int p)
149 {
150 return RTL839X_MAC_LINK_SPD_STS(p);
151 }
152
153 static inline int rtl839x_trk_mbr_ctr(int group)
154 {
155 return RTL839X_TRK_MBR_CTR + (group << 3);
156 }
157
158 static void rtl839x_fill_l2_entry(u32 r[], struct rtl838x_l2_entry *e)
159 {
160 /* Table contains different entry types, we need to identify the right one:
161 * Check for MC entries, first
162 */
163 e->is_ip_mc = !!(r[2] & BIT(31));
164 e->is_ipv6_mc = !!(r[2] & BIT(30));
165 e->type = L2_INVALID;
166 if (!e->is_ip_mc) {
167 e->mac[0] = (r[0] >> 12);
168 e->mac[1] = (r[0] >> 4);
169 e->mac[2] = ((r[1] >> 28) | (r[0] << 4));
170 e->mac[3] = (r[1] >> 20);
171 e->mac[4] = (r[1] >> 12);
172 e->mac[5] = (r[1] >> 4);
173
174 /* Is it a unicast entry? check multicast bit */
175 if (!(e->mac[0] & 1)) {
176 e->is_static = !!((r[2] >> 18) & 1);
177 e->vid = (r[2] >> 4) & 0xfff;
178 e->rvid = (r[0] >> 20) & 0xfff;
179 e->port = (r[2] >> 24) & 0x3f;
180 e->block_da = !!(r[2] & (1 << 19));
181 e->block_sa = !!(r[2] & (1 << 20));
182 e->suspended = !!(r[2] & (1 << 17));
183 e->next_hop = !!(r[2] & (1 << 16));
184 if (e->next_hop)
185 pr_info("Found next hop entry, need to read data\n");
186 e->age = (r[2] >> 21) & 3;
187 e->valid = true;
188 if (!(r[2] & 0xc0fd0000)) /* Check for valid entry */
189 e->valid = false;
190 else
191 e->type = L2_UNICAST;
192 } else {
193 e->valid = true;
194 e->type = L2_MULTICAST;
195 e->mc_portmask_index = (r[2]>>6) & 0xfff;
196 }
197 }
198 if (e->is_ip_mc) {
199 e->valid = true;
200 e->type = IP4_MULTICAST;
201 }
202 if (e->is_ipv6_mc) {
203 e->valid = true;
204 e->type = IP6_MULTICAST;
205 }
206 }
207
208 static u64 rtl839x_read_l2_entry_using_hash(u32 hash, u32 position, struct rtl838x_l2_entry *e)
209 {
210 u64 entry;
211 u32 r[3];
212
213 /* Search in SRAM, with hash and at position in hash bucket (0-3) */
214 u32 idx = (0 << 14) | (hash << 2) | position;
215
216 u32 cmd = 1 << 17 /* Execute cmd */
217 | 0 << 16 /* Read */
218 | 0 << 14 /* Table type 0b00 */
219 | (idx & 0x3fff);
220
221 sw_w32(cmd, RTL839X_TBL_ACCESS_L2_CTRL);
222 do { } while (sw_r32(RTL839X_TBL_ACCESS_L2_CTRL) & (1 << 17));
223 r[0] = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(0));
224 r[1] = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(1));
225 r[2] = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(2));
226
227 rtl839x_fill_l2_entry(r, e);
228
229 entry = (((u64) r[0]) << 12) | ((r[1] & 0xfffffff0) << 12) | ((r[2] >> 4) & 0xfff);
230 return entry;
231 }
232
233 static u64 rtl839x_read_cam(int idx, struct rtl838x_l2_entry *e)
234 {
235 u64 entry;
236 u32 r[3];
237
238 u32 cmd = 1 << 17 /* Execute cmd */
239 | 0 << 16 /* Read */
240 | 1 << 14 /* Table type 0b01 */
241 | (idx & 0x3f);
242 sw_w32(cmd, RTL839X_TBL_ACCESS_L2_CTRL);
243 do { } while (sw_r32(RTL839X_TBL_ACCESS_L2_CTRL) & (1 << 17));
244 r[0] = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(0));
245 r[1] = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(1));
246 r[2] = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(2));
247
248
249 rtl839x_fill_l2_entry(r, e);
250 if (e->valid)
251 pr_info("Found in CAM: R1 %x R2 %x R3 %x\n", r[0], r[1], r[2]);
252 else
253 return 0;
254
255 entry = (((u64) r[0]) << 12) | ((r[1] & 0xfffffff0) << 12) | ((r[2] >> 4) & 0xfff);
256 return entry;
257 }
258
259 static u64 rtl839x_read_mcast_pmask(int idx)
260 {
261 u64 portmask;
262 // Read MC_PMSK (2) via register RTL8390_TBL_L2
263 struct table_reg *q = rtl_table_get(RTL8390_TBL_L2, 2);
264
265 rtl_table_read(q, idx);
266 portmask = sw_r32(rtl_table_data(q, 0));
267 portmask <<= 32;
268 portmask |= sw_r32(rtl_table_data(q, 1));
269 portmask >>= 11; // LSB is bit 11 in data registers
270 rtl_table_release(q);
271
272 return portmask;
273 }
274
275 static void rtl839x_write_mcast_pmask(int idx, u64 portmask)
276 {
277 // Access MC_PMSK (2) via register RTL8380_TBL_L2
278 struct table_reg *q = rtl_table_get(RTL8390_TBL_L2, 2);
279
280 portmask <<= 11; // LSB is bit 11 in data registers
281 sw_w32((u32)(portmask >> 32), rtl_table_data(q, 0));
282 sw_w32((u32)((portmask & 0xfffff800)), rtl_table_data(q, 1));
283 rtl_table_write(q, idx);
284 rtl_table_release(q);
285 }
286
287 static void rtl839x_vlan_profile_setup(int profile)
288 {
289 u32 p[2];
290 u32 pmask_id = UNKNOWN_MC_PMASK;
291
292 p[0] = pmask_id; // Use portmaks 0xfff for unknown IPv6 MC flooding
293 // Enable L2 Learning BIT 0, portmask UNKNOWN_MC_PMASK for IP/L2-MC traffic flooding
294 p[1] = 1 | pmask_id << 1 | pmask_id << 13;
295
296 sw_w32(p[0], RTL839X_VLAN_PROFILE(profile));
297 sw_w32(p[1], RTL839X_VLAN_PROFILE(profile) + 4);
298
299 rtl839x_write_mcast_pmask(UNKNOWN_MC_PMASK, 0x000fffffffffffff);
300 }
301
302 static inline int rtl839x_vlan_port_egr_filter(int port)
303 {
304 return RTL839X_VLAN_PORT_EGR_FLTR(port);
305 }
306
307 static inline int rtl839x_vlan_port_igr_filter(int port)
308 {
309 return RTL839X_VLAN_PORT_IGR_FLTR(port);
310 }
311
312 u64 rtl839x_traffic_get(int source)
313 {
314 return rtl839x_get_port_reg_be(rtl839x_port_iso_ctrl(source));
315 }
316
317 void rtl839x_traffic_set(int source, u64 dest_matrix)
318 {
319 rtl839x_set_port_reg_be(dest_matrix, rtl839x_port_iso_ctrl(source));
320 }
321
322 void rtl839x_traffic_enable(int source, int dest)
323 {
324 rtl839x_mask_port_reg_be(0, BIT_ULL(dest), rtl839x_port_iso_ctrl(source));
325 }
326
327 void rtl839x_traffic_disable(int source, int dest)
328 {
329 rtl839x_mask_port_reg_be(BIT(dest), 0, rtl839x_port_iso_ctrl(source));
330 }
331
332 irqreturn_t rtl839x_switch_irq(int irq, void *dev_id)
333 {
334 struct dsa_switch *ds = dev_id;
335 u32 status = sw_r32(RTL839X_ISR_GLB_SRC);
336 u64 ports = rtl839x_get_port_reg_le(RTL839X_ISR_PORT_LINK_STS_CHG);
337 u64 link;
338 int i;
339
340 /* Clear status */
341 rtl839x_set_port_reg_le(ports, RTL839X_ISR_PORT_LINK_STS_CHG);
342 pr_debug("RTL8390 Link change: status: %x, ports %llx\n", status, ports);
343
344 for (i = 0; i < 52; i++) {
345 if (ports & (1ULL << i)) {
346 link = rtl839x_get_port_reg_le(RTL839X_MAC_LINK_STS);
347 if (link & (1ULL << i))
348 dsa_port_phylink_mac_change(ds, i, true);
349 else
350 dsa_port_phylink_mac_change(ds, i, false);
351 }
352 }
353 return IRQ_HANDLED;
354 }
355
356 // TODO: unused
357 int rtl8390_sds_power(int mac, int val)
358 {
359 u32 offset = (mac == 48) ? 0x0 : 0x100;
360 u32 mode = val ? 0 : 1;
361
362 pr_debug("In %s: mac %d, set %d\n", __func__, mac, val);
363
364 if ((mac != 48) && (mac != 49)) {
365 pr_err("%s: not an SFP port: %d\n", __func__, mac);
366 return -1;
367 }
368
369 // Set bit 1003. 1000 starts at 7c
370 sw_w32_mask(BIT(11), mode << 11, RTL839X_SDS12_13_PWR0 + offset);
371
372 return 0;
373 }
374
375
376 int rtl839x_read_phy(u32 port, u32 page, u32 reg, u32 *val)
377 {
378 u32 v;
379
380 if (port > 63 || page > 4095 || reg > 31)
381 return -ENOTSUPP;
382
383 mutex_lock(&smi_lock);
384
385 sw_w32_mask(0xffff0000, port << 16, RTL839X_PHYREG_DATA_CTRL);
386 v = reg << 5 | page << 10 | ((page == 0x1fff) ? 0x1f : 0) << 23;
387 sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
388
389 sw_w32(0x1ff, RTL839X_PHYREG_CTRL);
390
391 v |= 1;
392 sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
393
394 do {
395 } while (sw_r32(RTL839X_PHYREG_ACCESS_CTRL) & 0x1);
396
397 *val = sw_r32(RTL839X_PHYREG_DATA_CTRL) & 0xffff;
398
399 mutex_unlock(&smi_lock);
400 return 0;
401 }
402
403 int rtl839x_write_phy(u32 port, u32 page, u32 reg, u32 val)
404 {
405 u32 v;
406 int err = 0;
407
408 val &= 0xffff;
409 if (port > 63 || page > 4095 || reg > 31)
410 return -ENOTSUPP;
411
412 mutex_lock(&smi_lock);
413
414 // Set PHY to access
415 rtl839x_set_port_reg_le(BIT_ULL(port), RTL839X_PHYREG_PORT_CTRL);
416
417 sw_w32_mask(0xffff0000, val << 16, RTL839X_PHYREG_DATA_CTRL);
418
419 v = reg << 5 | page << 10 | ((page == 0x1fff) ? 0x1f : 0) << 23;
420 sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
421
422 sw_w32(0x1ff, RTL839X_PHYREG_CTRL);
423
424 v |= BIT(3) | 1; /* Write operation and execute */
425 sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
426
427 do {
428 } while (sw_r32(RTL839X_PHYREG_ACCESS_CTRL) & 0x1);
429
430 if (sw_r32(RTL839X_PHYREG_ACCESS_CTRL) & 0x2)
431 err = -EIO;
432
433 mutex_unlock(&smi_lock);
434 return err;
435 }
436
437 /*
438 * Read an mmd register of the PHY
439 */
440 int rtl839x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val)
441 {
442 int err = 0;
443 u32 v;
444
445 mutex_lock(&smi_lock);
446
447 // Set PHY to access
448 sw_w32_mask(0xffff << 16, port << 16, RTL839X_PHYREG_DATA_CTRL);
449
450 // Set MMD device number and register to write to
451 sw_w32(devnum << 16 | (regnum & 0xffff), RTL839X_PHYREG_MMD_CTRL);
452
453 v = BIT(2) | BIT(0); // MMD-access | EXEC
454 sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
455
456 do {
457 v = sw_r32(RTL839X_PHYREG_ACCESS_CTRL);
458 } while (v & BIT(0));
459 // There is no error-checking via BIT 1 of v, as it does not seem to be set correctly
460 *val = (sw_r32(RTL839X_PHYREG_DATA_CTRL) & 0xffff);
461 pr_debug("%s: port %d, regnum: %x, val: %x (err %d)\n", __func__, port, regnum, *val, err);
462
463 mutex_unlock(&smi_lock);
464
465 return err;
466 }
467
468 /*
469 * Write to an mmd register of the PHY
470 */
471 int rtl839x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val)
472 {
473 int err = 0;
474 u32 v;
475
476 mutex_lock(&smi_lock);
477
478 // Set PHY to access
479 rtl839x_set_port_reg_le(BIT_ULL(port), RTL839X_PHYREG_PORT_CTRL);
480
481 // Set data to write
482 sw_w32_mask(0xffff << 16, val << 16, RTL839X_PHYREG_DATA_CTRL);
483
484 // Set MMD device number and register to write to
485 sw_w32(devnum << 16 | (regnum & 0xffff), RTL839X_PHYREG_MMD_CTRL);
486
487 v = BIT(3) | BIT(2) | BIT(0); // WRITE | MMD-access | EXEC
488 sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
489
490 do {
491 v = sw_r32(RTL839X_PHYREG_ACCESS_CTRL);
492 } while (v & BIT(0));
493
494 pr_debug("%s: port %d, regnum: %x, val: %x (err %d)\n", __func__, port, regnum, val, err);
495 mutex_unlock(&smi_lock);
496 return err;
497 }
498
499 void rtl8390_get_version(struct rtl838x_switch_priv *priv)
500 {
501 u32 info;
502
503 sw_w32_mask(0xf << 28, 0xa << 28, RTL839X_CHIP_INFO);
504 info = sw_r32(RTL839X_CHIP_INFO);
505 pr_debug("Chip-Info: %x\n", info);
506 priv->version = RTL8390_VERSION_A;
507 }
508
509 u32 rtl839x_hash(struct rtl838x_switch_priv *priv, u64 seed)
510 {
511 u32 h1, h2, h;
512
513 if (sw_r32(priv->r->l2_ctrl_0) & 1) {
514 h1 = (u32) (((seed >> 60) & 0x3f) ^ ((seed >> 54) & 0x3f)
515 ^ ((seed >> 36) & 0x3f) ^ ((seed >> 30) & 0x3f)
516 ^ ((seed >> 12) & 0x3f) ^ ((seed >> 6) & 0x3f));
517 h2 = (u32) (((seed >> 48) & 0x3f) ^ ((seed >> 42) & 0x3f)
518 ^ ((seed >> 24) & 0x3f) ^ ((seed >> 18) & 0x3f)
519 ^ (seed & 0x3f));
520 h = (h1 << 6) | h2;
521 } else {
522 h = (seed >> 60)
523 ^ ((((seed >> 48) & 0x3f) << 6) | ((seed >> 54) & 0x3f))
524 ^ ((seed >> 36) & 0xfff) ^ ((seed >> 24) & 0xfff)
525 ^ ((seed >> 12) & 0xfff) ^ (seed & 0xfff);
526 }
527
528 return h;
529 }
530
531 void rtl839x_vlan_profile_dump(int profile)
532 {
533 u32 p[2];
534
535 if (profile < 0 || profile > 7)
536 return;
537
538 p[0] = sw_r32(RTL839X_VLAN_PROFILE(profile));
539 p[1] = sw_r32(RTL839X_VLAN_PROFILE(profile) + 4);
540
541 pr_info("VLAN profile %d: L2 learning: %d, UNKN L2MC FLD PMSK %d, \
542 UNKN IPMC FLD PMSK %d, UNKN IPv6MC FLD PMSK: %d",
543 profile, p[1] & 1, (p[1] >> 1) & 0xfff, (p[1] >> 13) & 0xfff,
544 (p[0]) & 0xfff);
545 pr_info("VLAN profile %d: raw %08x, %08x\n", profile, p[0], p[1]);
546 }
547
548 static void rtl839x_stp_get(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])
549 {
550 int i;
551 u32 cmd = 1 << 16 /* Execute cmd */
552 | 0 << 15 /* Read */
553 | 5 << 12 /* Table type 0b101 */
554 | (msti & 0xfff);
555 priv->r->exec_tbl0_cmd(cmd);
556
557 for (i = 0; i < 4; i++)
558 port_state[i] = sw_r32(priv->r->tbl_access_data_0(i));
559 }
560
561 static void rtl839x_stp_set(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])
562 {
563 int i;
564 u32 cmd = 1 << 16 /* Execute cmd */
565 | 1 << 15 /* Write */
566 | 5 << 12 /* Table type 0b101 */
567 | (msti & 0xfff);
568 for (i = 0; i < 4; i++)
569 sw_w32(port_state[i], priv->r->tbl_access_data_0(i));
570 priv->r->exec_tbl0_cmd(cmd);
571 }
572
573 /*
574 * Enables or disables the EEE/EEEP capability of a port
575 */
576 void rtl839x_port_eee_set(struct rtl838x_switch_priv *priv, int port, bool enable)
577 {
578 u32 v;
579
580 // This works only for Ethernet ports, and on the RTL839X, ports above 47 are SFP
581 if (port >= 48)
582 return;
583
584 enable = true;
585 pr_debug("In %s: setting port %d to %d\n", __func__, port, enable);
586 v = enable ? 0xf : 0x0;
587
588 // Set EEE for 100, 500, 1000MBit and 10GBit
589 sw_w32_mask(0xf << 8, v << 8, rtl839x_mac_force_mode_ctrl(port));
590
591 // Set TX/RX EEE state
592 v = enable ? 0x3 : 0x0;
593 sw_w32(v, RTL839X_EEE_CTRL(port));
594
595 priv->ports[port].eee_enabled = enable;
596 }
597
598 /*
599 * Get EEE own capabilities and negotiation result
600 */
601 int rtl839x_eee_port_ability(struct rtl838x_switch_priv *priv, struct ethtool_eee *e, int port)
602 {
603 u64 link, a;
604
605 if (port >= 48)
606 return 0;
607
608 link = rtl839x_get_port_reg_le(RTL839X_MAC_LINK_STS);
609 if (!(link & BIT_ULL(port)))
610 return 0;
611
612 if (sw_r32(rtl839x_mac_force_mode_ctrl(port)) & BIT(8))
613 e->advertised |= ADVERTISED_100baseT_Full;
614
615 if (sw_r32(rtl839x_mac_force_mode_ctrl(port)) & BIT(10))
616 e->advertised |= ADVERTISED_1000baseT_Full;
617
618 a = rtl839x_get_port_reg_le(RTL839X_MAC_EEE_ABLTY);
619 pr_info("Link partner: %016llx\n", a);
620 if (rtl839x_get_port_reg_le(RTL839X_MAC_EEE_ABLTY) & BIT_ULL(port)) {
621 e->lp_advertised = ADVERTISED_100baseT_Full;
622 e->lp_advertised |= ADVERTISED_1000baseT_Full;
623 return 1;
624 }
625
626 return 0;
627 }
628
629 static void rtl839x_init_eee(struct rtl838x_switch_priv *priv, bool enable)
630 {
631 int i;
632
633 pr_info("Setting up EEE, state: %d\n", enable);
634
635 // Set wake timer for TX and pause timer both to 0x21
636 sw_w32_mask(0xff << 20| 0xff, 0x21 << 20| 0x21, RTL839X_EEE_TX_TIMER_GELITE_CTRL);
637 // Set pause wake timer for GIGA-EEE to 0x11
638 sw_w32_mask(0xff << 20, 0x11 << 20, RTL839X_EEE_TX_TIMER_GIGA_CTRL);
639 // Set pause wake timer for 10GBit ports to 0x11
640 sw_w32_mask(0xff << 20, 0x11 << 20, RTL839X_EEE_TX_TIMER_10G_CTRL);
641
642 // Setup EEE on all ports
643 for (i = 0; i < priv->cpu_port; i++) {
644 if (priv->ports[i].phy)
645 rtl839x_port_eee_set(priv, i, enable);
646 }
647 priv->eee_enabled = enable;
648 }
649
650 const struct rtl838x_reg rtl839x_reg = {
651 .mask_port_reg_be = rtl839x_mask_port_reg_be,
652 .set_port_reg_be = rtl839x_set_port_reg_be,
653 .get_port_reg_be = rtl839x_get_port_reg_be,
654 .mask_port_reg_le = rtl839x_mask_port_reg_le,
655 .set_port_reg_le = rtl839x_set_port_reg_le,
656 .get_port_reg_le = rtl839x_get_port_reg_le,
657 .stat_port_rst = RTL839X_STAT_PORT_RST,
658 .stat_rst = RTL839X_STAT_RST,
659 .stat_port_std_mib = RTL839X_STAT_PORT_STD_MIB,
660 .traffic_enable = rtl839x_traffic_enable,
661 .traffic_disable = rtl839x_traffic_disable,
662 .traffic_get = rtl839x_traffic_get,
663 .traffic_set = rtl839x_traffic_set,
664 .port_iso_ctrl = rtl839x_port_iso_ctrl,
665 .l2_ctrl_0 = RTL839X_L2_CTRL_0,
666 .l2_ctrl_1 = RTL839X_L2_CTRL_1,
667 .l2_port_aging_out = RTL839X_L2_PORT_AGING_OUT,
668 .smi_poll_ctrl = RTL839X_SMI_PORT_POLLING_CTRL,
669 .l2_tbl_flush_ctrl = RTL839X_L2_TBL_FLUSH_CTRL,
670 .exec_tbl0_cmd = rtl839x_exec_tbl0_cmd,
671 .exec_tbl1_cmd = rtl839x_exec_tbl1_cmd,
672 .tbl_access_data_0 = rtl839x_tbl_access_data_0,
673 .isr_glb_src = RTL839X_ISR_GLB_SRC,
674 .isr_port_link_sts_chg = RTL839X_ISR_PORT_LINK_STS_CHG,
675 .imr_port_link_sts_chg = RTL839X_IMR_PORT_LINK_STS_CHG,
676 .imr_glb = RTL839X_IMR_GLB,
677 .vlan_tables_read = rtl839x_vlan_tables_read,
678 .vlan_set_tagged = rtl839x_vlan_set_tagged,
679 .vlan_set_untagged = rtl839x_vlan_set_untagged,
680 .vlan_profile_dump = rtl839x_vlan_profile_dump,
681 .vlan_profile_setup = rtl839x_vlan_profile_setup,
682 .vlan_fwd_on_inner = rtl839x_vlan_fwd_on_inner,
683 .stp_get = rtl839x_stp_get,
684 .stp_set = rtl839x_stp_set,
685 .mac_force_mode_ctrl = rtl839x_mac_force_mode_ctrl,
686 .mac_port_ctrl = rtl839x_mac_port_ctrl,
687 .l2_port_new_salrn = rtl839x_l2_port_new_salrn,
688 .l2_port_new_sa_fwd = rtl839x_l2_port_new_sa_fwd,
689 .mir_ctrl = RTL839X_MIR_CTRL,
690 .mir_dpm = RTL839X_MIR_DPM_CTRL,
691 .mir_spm = RTL839X_MIR_SPM_CTRL,
692 .mac_link_sts = RTL839X_MAC_LINK_STS,
693 .mac_link_dup_sts = RTL839X_MAC_LINK_DUP_STS,
694 .mac_link_spd_sts = rtl839x_mac_link_spd_sts,
695 .mac_rx_pause_sts = RTL839X_MAC_RX_PAUSE_STS,
696 .mac_tx_pause_sts = RTL839X_MAC_TX_PAUSE_STS,
697 .read_l2_entry_using_hash = rtl839x_read_l2_entry_using_hash,
698 .read_cam = rtl839x_read_cam,
699 .vlan_port_egr_filter = RTL839X_VLAN_PORT_EGR_FLTR(0),
700 .vlan_port_igr_filter = RTL839X_VLAN_PORT_IGR_FLTR(0),
701 .vlan_port_pb = RTL839X_VLAN_PORT_PB_VLAN,
702 .vlan_port_tag_sts_ctrl = RTL839X_VLAN_PORT_TAG_STS_CTRL,
703 .trk_mbr_ctr = rtl839x_trk_mbr_ctr,
704 .rma_bpdu_fld_pmask = RTL839X_RMA_BPDU_FLD_PMSK,
705 .spcl_trap_eapol_ctrl = RTL839X_SPCL_TRAP_EAPOL_CTRL,
706 .init_eee = rtl839x_init_eee,
707 .port_eee_set = rtl839x_port_eee_set,
708 .eee_port_ability = rtl839x_eee_port_ability,
709 .read_mcast_pmask = rtl839x_read_mcast_pmask,
710 .write_mcast_pmask = rtl839x_write_mcast_pmask,
711 };
Staging tree of Mathias Kresin