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realtek: Add support for clause45 PHYs
[openwrt/openwrt.git] / target / linux / realtek / files-5.4 / drivers / net / phy / rtl83xx-phy.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Realtek RTL838X Ethernet MDIO interface driver
3 *
4 * Copyright (C) 2020 B. Koblitz
5 */
6
7 #include <linux/module.h>
8 #include <linux/delay.h>
9 #include <linux/phy.h>
10 #include <linux/netdevice.h>
11 #include <linux/firmware.h>
12 #include <linux/crc32.h>
13
14 #include <asm/mach-rtl838x/mach-rtl83xx.h>
15 #include "rtl83xx-phy.h"
16
17
18 extern struct rtl83xx_soc_info soc_info;
19 extern struct mutex smi_lock;
20
21 /*
22 * This lock protects the state of the SoC automatically polling the PHYs over the SMI
23 * bus to detect e.g. link and media changes. For operations on the PHYs such as
24 * patching or other configuration changes such as EEE, polling needs to be disabled
25 * since otherwise these operations may fails or lead to unpredictable results.
26 */
27 DEFINE_MUTEX(poll_lock);
28
29 static const struct firmware rtl838x_8380_fw;
30 static const struct firmware rtl838x_8214fc_fw;
31 static const struct firmware rtl838x_8218b_fw;
32
33 int rtl838x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val);
34 int rtl838x_write_mmd_phy(u32 port, u32 devnum, u32 reg, u32 val);
35 int rtl839x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val);
36 int rtl839x_write_mmd_phy(u32 port, u32 devnum, u32 reg, u32 val);
37 int rtl930x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val);
38 int rtl930x_write_mmd_phy(u32 port, u32 devnum, u32 reg, u32 val);
39 int rtl931x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val);
40 int rtl931x_write_mmd_phy(u32 port, u32 devnum, u32 reg, u32 val);
41
42 static int read_phy(u32 port, u32 page, u32 reg, u32 *val)
43 { switch (soc_info.family) {
44 case RTL8380_FAMILY_ID:
45 return rtl838x_read_phy(port, page, reg, val);
46 case RTL8390_FAMILY_ID:
47 return rtl839x_read_phy(port, page, reg, val);
48 case RTL9300_FAMILY_ID:
49 return rtl930x_read_phy(port, page, reg, val);
50 case RTL9310_FAMILY_ID:
51 return rtl931x_read_phy(port, page, reg, val);
52 }
53 return -1;
54 }
55
56 static int write_phy(u32 port, u32 page, u32 reg, u32 val)
57 {
58 switch (soc_info.family) {
59 case RTL8380_FAMILY_ID:
60 return rtl838x_write_phy(port, page, reg, val);
61 case RTL8390_FAMILY_ID:
62 return rtl839x_write_phy(port, page, reg, val);
63 case RTL9300_FAMILY_ID:
64 return rtl930x_write_phy(port, page, reg, val);
65 case RTL9310_FAMILY_ID:
66 return rtl931x_write_phy(port, page, reg, val);
67 }
68 return -1;
69 }
70
71 static int read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val)
72 {
73 switch (soc_info.family) {
74 case RTL8380_FAMILY_ID:
75 return rtl838x_read_mmd_phy(port, devnum, regnum, val);
76 case RTL8390_FAMILY_ID:
77 return rtl839x_read_mmd_phy(port, devnum, regnum, val);
78 case RTL9300_FAMILY_ID:
79 return rtl930x_read_mmd_phy(port, devnum, regnum, val);
80 case RTL9310_FAMILY_ID:
81 return rtl931x_read_mmd_phy(port, devnum, regnum, val);
82 }
83 return -1;
84 }
85
86 int write_mmd_phy(u32 port, u32 devnum, u32 reg, u32 val)
87 {
88 switch (soc_info.family) {
89 case RTL8380_FAMILY_ID:
90 return rtl838x_write_mmd_phy(port, devnum, reg, val);
91 case RTL8390_FAMILY_ID:
92 return rtl839x_write_mmd_phy(port, devnum, reg, val);
93 case RTL9300_FAMILY_ID:
94 return rtl930x_write_mmd_phy(port, devnum, reg, val);
95 case RTL9310_FAMILY_ID:
96 return rtl931x_write_mmd_phy(port, devnum, reg, val);
97 }
98 return -1;
99 }
100
101 static u64 disable_polling(int port)
102 {
103 u64 saved_state;
104
105 mutex_lock(&poll_lock);
106
107 switch (soc_info.family) {
108 case RTL8380_FAMILY_ID:
109 saved_state = sw_r32(RTL838X_SMI_POLL_CTRL);
110 sw_w32_mask(BIT(port), 0, RTL838X_SMI_POLL_CTRL);
111 break;
112 case RTL8390_FAMILY_ID:
113 saved_state = sw_r32(RTL839X_SMI_PORT_POLLING_CTRL + 4);
114 saved_state <<= 32;
115 saved_state |= sw_r32(RTL839X_SMI_PORT_POLLING_CTRL);
116 sw_w32_mask(BIT(port % 32), 0,
117 RTL839X_SMI_PORT_POLLING_CTRL + ((port >> 5) << 2));
118 break;
119 case RTL9300_FAMILY_ID:
120 saved_state = sw_r32(RTL930X_SMI_POLL_CTRL);
121 sw_w32_mask(BIT(port), 0, RTL930X_SMI_POLL_CTRL);
122 break;
123 case RTL9310_FAMILY_ID:
124 pr_warn("%s not implemented for RTL931X\n", __func__);
125 break;
126 }
127
128 mutex_unlock(&poll_lock);
129
130 return saved_state;
131 }
132
133 static int resume_polling(u64 saved_state)
134 {
135 mutex_lock(&poll_lock);
136
137 switch (soc_info.family) {
138 case RTL8380_FAMILY_ID:
139 sw_w32(saved_state, RTL838X_SMI_POLL_CTRL);
140 break;
141 case RTL8390_FAMILY_ID:
142 sw_w32(saved_state >> 32, RTL839X_SMI_PORT_POLLING_CTRL + 4);
143 sw_w32(saved_state, RTL839X_SMI_PORT_POLLING_CTRL);
144 break;
145 case RTL9300_FAMILY_ID:
146 sw_w32(saved_state, RTL930X_SMI_POLL_CTRL);
147 break;
148 case RTL9310_FAMILY_ID:
149 pr_warn("%s not implemented for RTL931X\n", __func__);
150 break;
151 }
152
153 mutex_unlock(&poll_lock);
154
155 return 0;
156 }
157
158 static void rtl8380_int_phy_on_off(int mac, bool on)
159 {
160 u32 val;
161
162 read_phy(mac, 0, 0, &val);
163 if (on)
164 write_phy(mac, 0, 0, val & ~BIT(11));
165 else
166 write_phy(mac, 0, 0, val | BIT(11));
167 }
168
169 static void rtl8380_rtl8214fc_on_off(int mac, bool on)
170 {
171 u32 val;
172
173 /* fiber ports */
174 write_phy(mac, 4095, 30, 3);
175 read_phy(mac, 0, 16, &val);
176 if (on)
177 write_phy(mac, 0, 16, val & ~BIT(11));
178 else
179 write_phy(mac, 0, 16, val | BIT(11));
180
181 /* copper ports */
182 write_phy(mac, 4095, 30, 1);
183 read_phy(mac, 0, 16, &val);
184 if (on)
185 write_phy(mac, 0xa40, 16, val & ~BIT(11));
186 else
187 write_phy(mac, 0xa40, 16, val | BIT(11));
188 }
189
190 static void rtl8380_phy_reset(int mac)
191 {
192 u32 val;
193
194 read_phy(mac, 0, 0, &val);
195 write_phy(mac, 0, 0, val | BIT(15));
196 }
197
198 /*
199 * Reset the SerDes by powering it off and set a new operations mode
200 * of the SerDes. 0x1f is off. Other modes are
201 * 0x01: QSGMII 0x04: 1000BX_FIBER 0x05: FIBER100
202 * 0x06: QSGMII 0x09: RSGMII 0x0d: USXGMII
203 * 0x10: XSGMII 0x12: HISGMII 0x16: 2500Base_X
204 * 0x17: RXAUI_LITE 0x19: RXAUI_PLUS 0x1a: 10G Base-R
205 * 0x1b: 10GR1000BX_AUTO 0x1f: OFF
206 */
207 void rtl9300_sds_rst(int sds_num, u32 mode)
208 {
209 // The access registers for SDS_MODE_SEL and the LSB for each SDS within
210 u16 regs[] = { 0x0194, 0x0194, 0x0194, 0x0194, 0x02a0, 0x02a0, 0x02a0, 0x02a0,
211 0x02A4, 0x02A4, 0x0198, 0x0198 };
212 u8 lsb[] = { 0, 6, 12, 18, 0, 6, 12, 18, 0, 6, 0, 6};
213
214 pr_info("SerDes: %s %d\n", __func__, mode);
215 if (sds_num < 0 || sds_num > 11) {
216 pr_err("Wrong SerDes number: %d\n", sds_num);
217 return;
218 }
219
220 sw_w32_mask(0x1f << lsb[sds_num], 0x1f << lsb[sds_num], regs[sds_num]);
221 mdelay(10);
222
223 sw_w32_mask(0x1f << lsb[sds_num], mode << lsb[sds_num], regs[sds_num]);
224 mdelay(10);
225
226 pr_info("SDS: 194:%08x 198:%08x 2a0:%08x 2a4:%08x\n",
227 sw_r32(0x194), sw_r32(0x198), sw_r32(0x2a0), sw_r32(0x2a4));
228 }
229
230 /*
231 * On the RTL839x family of SoCs with inbuilt SerDes, these SerDes are accessed through
232 * a 2048 bit register that holds the contents of the PHY being simulated by the SoC.
233 */
234 int rtl839x_read_sds_phy(int phy_addr, int phy_reg)
235 {
236 int offset = 0;
237 int reg;
238 u32 val;
239
240 if (phy_addr == 49)
241 offset = 0x100;
242
243 /*
244 * For the RTL8393 internal SerDes, we simulate a PHY ID in registers 2/3
245 * which would otherwise read as 0.
246 */
247 if (soc_info.id == 0x8393) {
248 if (phy_reg == 2)
249 return 0x1c;
250 if (phy_reg == 3)
251 return 0x8393;
252 }
253
254 /*
255 * Register RTL839X_SDS12_13_XSG0 is 2048 bit broad, the MSB (bit 15) of the
256 * 0th PHY register is bit 1023 (in byte 0x80). Because PHY-registers are 16
257 * bit broad, we offset by reg << 1. In the SoC 2 registers are stored in
258 * one 32 bit register.
259 */
260 reg = (phy_reg << 1) & 0xfc;
261 val = sw_r32(RTL839X_SDS12_13_XSG0 + offset + 0x80 + reg);
262
263 if (phy_reg & 1)
264 val = (val >> 16) & 0xffff;
265 else
266 val &= 0xffff;
267 return val;
268 }
269
270 /*
271 * On the RTL930x family of SoCs, the internal SerDes are accessed through an IO
272 * register which simulates commands to an internal MDIO bus.
273 */
274 int rtl930x_read_sds_phy(int phy_addr, int page, int phy_reg)
275 {
276 int i;
277 u32 cmd = phy_addr << 2 | page << 7 | phy_reg << 13 | 1;
278
279 pr_info("%s: phy_addr %d, phy_reg: %d\n", __func__, phy_addr, phy_reg);
280 sw_w32(cmd, RTL930X_SDS_INDACS_CMD);
281
282 for (i = 0; i < 100; i++) {
283 if (!(sw_r32(RTL930X_SDS_INDACS_CMD) & 0x1))
284 break;
285 mdelay(1);
286 }
287
288 if (i >= 100)
289 return -EIO;
290
291 pr_info("%s: returning %04x\n", __func__, sw_r32(RTL930X_SDS_INDACS_DATA) & 0xffff);
292 return sw_r32(RTL930X_SDS_INDACS_DATA) & 0xffff;
293 }
294
295 int rtl930x_write_sds_phy(int phy_addr, int page, int phy_reg, u16 v)
296 {
297 int i;
298 u32 cmd;
299
300 sw_w32(v, RTL930X_SDS_INDACS_DATA);
301 cmd = phy_addr << 2 | page << 7 | phy_reg << 13 | 0x3;
302
303 for (i = 0; i < 100; i++) {
304 if (!(sw_r32(RTL930X_SDS_INDACS_CMD) & 0x1))
305 break;
306 mdelay(1);
307 }
308
309 if (i >= 100)
310 return -EIO;
311
312 return 0;
313 }
314
315 /*
316 * On the RTL838x SoCs, the internal SerDes is accessed through direct access to
317 * standard PHY registers, where a 32 bit register holds a 16 bit word as found
318 * in a standard page 0 of a PHY
319 */
320 int rtl838x_read_sds_phy(int phy_addr, int phy_reg)
321 {
322 int offset = 0;
323 u32 val;
324
325 if (phy_addr == 26)
326 offset = 0x100;
327 val = sw_r32(RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2)) & 0xffff;
328
329 return val;
330 }
331
332 int rtl839x_write_sds_phy(int phy_addr, int phy_reg, u16 v)
333 {
334 int offset = 0;
335 int reg;
336 u32 val;
337
338 if (phy_addr == 49)
339 offset = 0x100;
340
341 reg = (phy_reg << 1) & 0xfc;
342 val = v;
343 if (phy_reg & 1) {
344 val = val << 16;
345 sw_w32_mask(0xffff0000, val,
346 RTL839X_SDS12_13_XSG0 + offset + 0x80 + reg);
347 } else {
348 sw_w32_mask(0xffff, val,
349 RTL839X_SDS12_13_XSG0 + offset + 0x80 + reg);
350 }
351
352 return 0;
353 }
354
355 /* Read the link and speed status of the 2 internal SGMII/1000Base-X
356 * ports of the RTL838x SoCs
357 */
358 static int rtl8380_read_status(struct phy_device *phydev)
359 {
360 int err;
361
362 err = genphy_read_status(phydev);
363
364 if (phydev->link) {
365 phydev->speed = SPEED_1000;
366 phydev->duplex = DUPLEX_FULL;
367 }
368
369 return err;
370 }
371
372 /* Read the link and speed status of the 2 internal SGMII/1000Base-X
373 * ports of the RTL8393 SoC
374 */
375 static int rtl8393_read_status(struct phy_device *phydev)
376 {
377 int offset = 0;
378 int err;
379 int phy_addr = phydev->mdio.addr;
380 u32 v;
381
382 err = genphy_read_status(phydev);
383 if (phy_addr == 49)
384 offset = 0x100;
385
386 if (phydev->link) {
387 phydev->speed = SPEED_100;
388 /* Read SPD_RD_00 (bit 13) and SPD_RD_01 (bit 6) out of the internal
389 * PHY registers
390 */
391 v = sw_r32(RTL839X_SDS12_13_XSG0 + offset + 0x80);
392 if (!(v & (1 << 13)) && (v & (1 << 6)))
393 phydev->speed = SPEED_1000;
394 phydev->duplex = DUPLEX_FULL;
395 }
396
397 return err;
398 }
399
400 static int rtl8226_read_page(struct phy_device *phydev)
401 {
402 return __phy_read(phydev, 0x1f);
403 }
404
405 static int rtl8226_write_page(struct phy_device *phydev, int page)
406 {
407 return __phy_write(phydev, 0x1f, page);
408 }
409
410 static int rtl8226_read_status(struct phy_device *phydev)
411 {
412 int ret = 0, i;
413 u32 val;
414 int port = phydev->mdio.addr;
415
416 // TODO: ret = genphy_read_status(phydev);
417 // if (ret < 0) {
418 // pr_info("%s: genphy_read_status failed\n", __func__);
419 // return ret;
420 // }
421
422 // Link status must be read twice
423 for (i = 0; i < 2; i++) {
424 read_mmd_phy(port, MMD_VEND2, 0xA402, &val);
425 }
426 phydev->link = val & BIT(2) ? 1 : 0;
427 if (!phydev->link)
428 goto out;
429
430 // Read duplex status
431 ret = read_mmd_phy(port, MMD_VEND2, 0xA434, &val);
432 if (ret)
433 goto out;
434 phydev->duplex = !!(val & BIT(3));
435
436 // Read speed
437 ret = read_mmd_phy(port, MMD_VEND2, 0xA434, &val);
438 switch (val & 0x0630) {
439 case 0x0000:
440 phydev->speed = SPEED_10;
441 break;
442 case 0x0010:
443 phydev->speed = SPEED_100;
444 break;
445 case 0x0020:
446 phydev->speed = SPEED_1000;
447 break;
448 case 0x0200:
449 phydev->speed = SPEED_10000;
450 break;
451 case 0x0210:
452 phydev->speed = SPEED_2500;
453 break;
454 case 0x0220:
455 phydev->speed = SPEED_5000;
456 break;
457 default:
458 break;
459 }
460 out:
461 return ret;
462 }
463
464 static int rtl8226_advertise_aneg(struct phy_device *phydev)
465 {
466 int ret = 0;
467 u32 v;
468 int port = phydev->mdio.addr;
469
470 pr_info("In %s\n", __func__);
471
472 ret = read_mmd_phy(port, MMD_AN, 16, &v);
473 if (ret)
474 goto out;
475
476 v |= BIT(5); // HD 10M
477 v |= BIT(6); // FD 10M
478 v |= BIT(7); // HD 100M
479 v |= BIT(8); // FD 100M
480
481 ret = write_mmd_phy(port, MMD_AN, 16, v);
482
483 // Allow 1GBit
484 ret = read_mmd_phy(port, MMD_VEND2, 0xA412, &v);
485 if (ret)
486 goto out;
487 v |= BIT(9); // FD 1000M
488
489 ret = write_mmd_phy(port, MMD_VEND2, 0xA412, v);
490 if (ret)
491 goto out;
492
493 // Allow 2.5G
494 ret = read_mmd_phy(port, MMD_AN, 32, &v);
495 if (ret)
496 goto out;
497
498 v |= BIT(7);
499 ret = write_mmd_phy(port, MMD_AN, 32, v);
500
501 out:
502 return ret;
503 }
504
505 static int rtl8226_config_aneg(struct phy_device *phydev)
506 {
507 int ret = 0;
508 u32 v;
509 int port = phydev->mdio.addr;
510
511 pr_info("In %s\n", __func__);
512 if (phydev->autoneg == AUTONEG_ENABLE) {
513 ret = rtl8226_advertise_aneg(phydev);
514 if (ret)
515 goto out;
516 // AutoNegotiationEnable
517 ret = read_mmd_phy(port, MMD_AN, 0, &v);
518 if (ret)
519 goto out;
520
521 v |= BIT(12); // Enable AN
522 ret = write_mmd_phy(port, MMD_AN, 0, v);
523 if (ret)
524 goto out;
525
526 // RestartAutoNegotiation
527 ret = read_mmd_phy(port, MMD_VEND2, 0xA400, &v);
528 if (ret)
529 goto out;
530 v |= BIT(9);
531
532 ret = write_mmd_phy(port, MMD_VEND2, 0xA400, v);
533 }
534
535 pr_info("%s: Ret is already: %d\n", __func__, ret);
536 // TODO: ret = __genphy_config_aneg(phydev, ret);
537
538 out:
539 pr_info("%s: And ret is now: %d\n", __func__, ret);
540 return ret;
541 }
542
543 static int rtl8226_get_eee(struct phy_device *phydev,
544 struct ethtool_eee *e)
545 {
546 u32 val;
547 int addr = phydev->mdio.addr;
548
549 pr_debug("In %s, port %d, was enabled: %d\n", __func__, addr, e->eee_enabled);
550
551 read_mmd_phy(addr, MMD_AN, 60, &val);
552 if (e->eee_enabled) {
553 e->eee_enabled = !!(val & BIT(1));
554 if (!e->eee_enabled) {
555 read_mmd_phy(addr, MMD_AN, 62, &val);
556 e->eee_enabled = !!(val & BIT(0));
557 }
558 }
559 pr_debug("%s: enabled: %d\n", __func__, e->eee_enabled);
560
561 return 0;
562 }
563
564 static int rtl8226_set_eee(struct phy_device *phydev, struct ethtool_eee *e)
565 {
566 int port = phydev->mdio.addr;
567 u64 poll_state;
568 bool an_enabled;
569 u32 val;
570
571 pr_info("In %s, port %d, enabled %d\n", __func__, port, e->eee_enabled);
572
573 poll_state = disable_polling(port);
574
575 // Remember aneg state
576 read_mmd_phy(port, MMD_AN, 0, &val);
577 an_enabled = !!(val & BIT(12));
578
579 // Setup 100/1000MBit
580 read_mmd_phy(port, MMD_AN, 60, &val);
581 if (e->eee_enabled)
582 val |= 0x6;
583 else
584 val &= 0x6;
585 write_mmd_phy(port, MMD_AN, 60, val);
586
587 // Setup 2.5GBit
588 read_mmd_phy(port, MMD_AN, 62, &val);
589 if (e->eee_enabled)
590 val |= 0x1;
591 else
592 val &= 0x1;
593 write_mmd_phy(port, MMD_AN, 62, val);
594
595 // RestartAutoNegotiation
596 read_mmd_phy(port, MMD_VEND2, 0xA400, &val);
597 val |= BIT(9);
598 write_mmd_phy(port, MMD_VEND2, 0xA400, val);
599
600 resume_polling(poll_state);
601
602 return 0;
603 }
604
605 static struct fw_header *rtl838x_request_fw(struct phy_device *phydev,
606 const struct firmware *fw,
607 const char *name)
608 {
609 struct device *dev = &phydev->mdio.dev;
610 int err;
611 struct fw_header *h;
612 uint32_t checksum, my_checksum;
613
614 err = request_firmware(&fw, name, dev);
615 if (err < 0)
616 goto out;
617
618 if (fw->size < sizeof(struct fw_header)) {
619 pr_err("Firmware size too small.\n");
620 err = -EINVAL;
621 goto out;
622 }
623
624 h = (struct fw_header *) fw->data;
625 pr_info("Firmware loaded. Size %d, magic: %08x\n", fw->size, h->magic);
626
627 if (h->magic != 0x83808380) {
628 pr_err("Wrong firmware file: MAGIC mismatch.\n");
629 goto out;
630 }
631
632 checksum = h->checksum;
633 h->checksum = 0;
634 my_checksum = ~crc32(0xFFFFFFFFU, fw->data, fw->size);
635 if (checksum != my_checksum) {
636 pr_err("Firmware checksum mismatch.\n");
637 err = -EINVAL;
638 goto out;
639 }
640 h->checksum = checksum;
641
642 return h;
643 out:
644 dev_err(dev, "Unable to load firmware %s (%d)\n", name, err);
645 return NULL;
646 }
647
648 static int rtl8390_configure_generic(struct phy_device *phydev)
649 {
650 u32 val, phy_id;
651 int mac = phydev->mdio.addr;
652
653 read_phy(mac, 0, 2, &val);
654 phy_id = val << 16;
655 read_phy(mac, 0, 3, &val);
656 phy_id |= val;
657 pr_debug("Phy on MAC %d: %x\n", mac, phy_id);
658
659 /* Read internal PHY ID */
660 write_phy(mac, 31, 27, 0x0002);
661 read_phy(mac, 31, 28, &val);
662
663 /* Internal RTL8218B, version 2 */
664 phydev_info(phydev, "Detected unknown %x\n", val);
665 return 0;
666 }
667
668 static int rtl8380_configure_int_rtl8218b(struct phy_device *phydev)
669 {
670 u32 val, phy_id;
671 int i, p, ipd_flag;
672 int mac = phydev->mdio.addr;
673 struct fw_header *h;
674 u32 *rtl838x_6275B_intPhy_perport;
675 u32 *rtl8218b_6276B_hwEsd_perport;
676
677
678 read_phy(mac, 0, 2, &val);
679 phy_id = val << 16;
680 read_phy(mac, 0, 3, &val);
681 phy_id |= val;
682 pr_debug("Phy on MAC %d: %x\n", mac, phy_id);
683
684 /* Read internal PHY ID */
685 write_phy(mac, 31, 27, 0x0002);
686 read_phy(mac, 31, 28, &val);
687 if (val != 0x6275) {
688 phydev_err(phydev, "Expected internal RTL8218B, found PHY-ID %x\n", val);
689 return -1;
690 }
691
692 /* Internal RTL8218B, version 2 */
693 phydev_info(phydev, "Detected internal RTL8218B\n");
694
695 h = rtl838x_request_fw(phydev, &rtl838x_8380_fw, FIRMWARE_838X_8380_1);
696 if (!h)
697 return -1;
698
699 if (h->phy != 0x83800000) {
700 phydev_err(phydev, "Wrong firmware file: PHY mismatch.\n");
701 return -1;
702 }
703
704 rtl838x_6275B_intPhy_perport = (void *)h + sizeof(struct fw_header)
705 + h->parts[8].start;
706
707 rtl8218b_6276B_hwEsd_perport = (void *)h + sizeof(struct fw_header)
708 + h->parts[9].start;
709
710 if (sw_r32(RTL838X_DMY_REG31) == 0x1)
711 ipd_flag = 1;
712
713 read_phy(mac, 0, 0, &val);
714 if (val & (1 << 11))
715 rtl8380_int_phy_on_off(mac, true);
716 else
717 rtl8380_phy_reset(mac);
718 msleep(100);
719
720 /* Ready PHY for patch */
721 for (p = 0; p < 8; p++) {
722 write_phy(mac + p, 0xfff, 0x1f, 0x0b82);
723 write_phy(mac + p, 0xfff, 0x10, 0x0010);
724 }
725 msleep(500);
726 for (p = 0; p < 8; p++) {
727 for (i = 0; i < 100 ; i++) {
728 read_phy(mac + p, 0x0b80, 0x10, &val);
729 if (val & 0x40)
730 break;
731 }
732 if (i >= 100) {
733 phydev_err(phydev,
734 "ERROR: Port %d not ready for patch.\n",
735 mac + p);
736 return -1;
737 }
738 }
739 for (p = 0; p < 8; p++) {
740 i = 0;
741 while (rtl838x_6275B_intPhy_perport[i * 2]) {
742 write_phy(mac + p, 0xfff,
743 rtl838x_6275B_intPhy_perport[i * 2],
744 rtl838x_6275B_intPhy_perport[i * 2 + 1]);
745 i++;
746 }
747 i = 0;
748 while (rtl8218b_6276B_hwEsd_perport[i * 2]) {
749 write_phy(mac + p, 0xfff,
750 rtl8218b_6276B_hwEsd_perport[i * 2],
751 rtl8218b_6276B_hwEsd_perport[i * 2 + 1]);
752 i++;
753 }
754 }
755 return 0;
756 }
757
758 static int rtl8380_configure_ext_rtl8218b(struct phy_device *phydev)
759 {
760 u32 val, ipd, phy_id;
761 int i, l;
762 int mac = phydev->mdio.addr;
763 struct fw_header *h;
764 u32 *rtl8380_rtl8218b_perchip;
765 u32 *rtl8218B_6276B_rtl8380_perport;
766 u32 *rtl8380_rtl8218b_perport;
767
768 if (soc_info.family == RTL8380_FAMILY_ID && mac != 0 && mac != 16) {
769 phydev_err(phydev, "External RTL8218B must have PHY-IDs 0 or 16!\n");
770 return -1;
771 }
772 read_phy(mac, 0, 2, &val);
773 phy_id = val << 16;
774 read_phy(mac, 0, 3, &val);
775 phy_id |= val;
776 pr_info("Phy on MAC %d: %x\n", mac, phy_id);
777
778 /* Read internal PHY ID */
779 write_phy(mac, 31, 27, 0x0002);
780 read_phy(mac, 31, 28, &val);
781 if (val != 0x6276) {
782 phydev_err(phydev, "Expected external RTL8218B, found PHY-ID %x\n", val);
783 return -1;
784 }
785 phydev_info(phydev, "Detected external RTL8218B\n");
786
787 h = rtl838x_request_fw(phydev, &rtl838x_8218b_fw, FIRMWARE_838X_8218b_1);
788 if (!h)
789 return -1;
790
791 if (h->phy != 0x8218b000) {
792 phydev_err(phydev, "Wrong firmware file: PHY mismatch.\n");
793 return -1;
794 }
795
796 rtl8380_rtl8218b_perchip = (void *)h + sizeof(struct fw_header)
797 + h->parts[0].start;
798
799 rtl8218B_6276B_rtl8380_perport = (void *)h + sizeof(struct fw_header)
800 + h->parts[1].start;
801
802 rtl8380_rtl8218b_perport = (void *)h + sizeof(struct fw_header)
803 + h->parts[2].start;
804
805 read_phy(mac, 0, 0, &val);
806 if (val & (1 << 11))
807 rtl8380_int_phy_on_off(mac, true);
808 else
809 rtl8380_phy_reset(mac);
810 msleep(100);
811
812 /* Get Chip revision */
813 write_phy(mac, 0xfff, 0x1f, 0x0);
814 write_phy(mac, 0xfff, 0x1b, 0x4);
815 read_phy(mac, 0xfff, 0x1c, &val);
816
817 i = 0;
818 while (rtl8380_rtl8218b_perchip[i * 3]
819 && rtl8380_rtl8218b_perchip[i * 3 + 1]) {
820 write_phy(mac + rtl8380_rtl8218b_perchip[i * 3],
821 0xfff, rtl8380_rtl8218b_perchip[i * 3 + 1],
822 rtl8380_rtl8218b_perchip[i * 3 + 2]);
823 i++;
824 }
825
826 /* Enable PHY */
827 for (i = 0; i < 8; i++) {
828 write_phy(mac + i, 0xfff, 0x1f, 0x0000);
829 write_phy(mac + i, 0xfff, 0x00, 0x1140);
830 }
831 mdelay(100);
832
833 /* Request patch */
834 for (i = 0; i < 8; i++) {
835 write_phy(mac + i, 0xfff, 0x1f, 0x0b82);
836 write_phy(mac + i, 0xfff, 0x10, 0x0010);
837 }
838 mdelay(300);
839
840 /* Verify patch readiness */
841 for (i = 0; i < 8; i++) {
842 for (l = 0; l < 100; l++) {
843 read_phy(mac + i, 0xb80, 0x10, &val);
844 if (val & 0x40)
845 break;
846 }
847 if (l >= 100) {
848 phydev_err(phydev, "Could not patch PHY\n");
849 return -1;
850 }
851 }
852
853 /* Use Broadcast ID method for patching */
854 write_phy(mac, 0xfff, 0x1f, 0x0000);
855 write_phy(mac, 0xfff, 0x1d, 0x0008);
856 write_phy(mac, 0xfff, 0x1f, 0x0266);
857 write_phy(mac, 0xfff, 0x16, 0xff00 + mac);
858 write_phy(mac, 0xfff, 0x1f, 0x0000);
859 write_phy(mac, 0xfff, 0x1d, 0x0000);
860 mdelay(1);
861
862 write_phy(mac, 0xfff, 30, 8);
863 write_phy(mac, 0x26e, 17, 0xb);
864 write_phy(mac, 0x26e, 16, 0x2);
865 mdelay(1);
866 read_phy(mac, 0x26e, 19, &ipd);
867 write_phy(mac, 0, 30, 0);
868 ipd = (ipd >> 4) & 0xf;
869
870 i = 0;
871 while (rtl8218B_6276B_rtl8380_perport[i * 2]) {
872 write_phy(mac, 0xfff, rtl8218B_6276B_rtl8380_perport[i * 2],
873 rtl8218B_6276B_rtl8380_perport[i * 2 + 1]);
874 i++;
875 }
876
877 /*Disable broadcast ID*/
878 write_phy(mac, 0xfff, 0x1f, 0x0000);
879 write_phy(mac, 0xfff, 0x1d, 0x0008);
880 write_phy(mac, 0xfff, 0x1f, 0x0266);
881 write_phy(mac, 0xfff, 0x16, 0x00 + mac);
882 write_phy(mac, 0xfff, 0x1f, 0x0000);
883 write_phy(mac, 0xfff, 0x1d, 0x0000);
884 mdelay(1);
885
886 return 0;
887 }
888
889 static int rtl8218b_ext_match_phy_device(struct phy_device *phydev)
890 {
891 int addr = phydev->mdio.addr;
892
893 /* Both the RTL8214FC and the external RTL8218B have the same
894 * PHY ID. On the RTL838x, the RTL8218B can only be attached_dev
895 * at PHY IDs 0-7, while the RTL8214FC must be attached via
896 * the pair of SGMII/1000Base-X with higher PHY-IDs
897 */
898 if (soc_info.family == RTL8380_FAMILY_ID)
899 return phydev->phy_id == PHY_ID_RTL8218B_E && addr < 8;
900 else
901 return phydev->phy_id == PHY_ID_RTL8218B_E;
902 }
903
904 static int rtl8218b_read_mmd(struct phy_device *phydev,
905 int devnum, u16 regnum)
906 {
907 int ret;
908 u32 val;
909 int addr = phydev->mdio.addr;
910
911 ret = read_mmd_phy(addr, devnum, regnum, &val);
912 if (ret)
913 return ret;
914 return val;
915 }
916
917 static int rtl8218b_write_mmd(struct phy_device *phydev,
918 int devnum, u16 regnum, u16 val)
919 {
920 int addr = phydev->mdio.addr;
921
922 return rtl838x_write_mmd_phy(addr, devnum, regnum, val);
923 }
924
925 static int rtl8226_read_mmd(struct phy_device *phydev, int devnum, u16 regnum)
926 {
927 int port = phydev->mdio.addr; // the SoC translates port addresses to PHY addr
928 int err;
929 u32 val;
930
931 err = read_mmd_phy(port, devnum, regnum, &val);
932 if (err)
933 return err;
934 return val;
935 }
936
937 static int rtl8226_write_mmd(struct phy_device *phydev, int devnum, u16 regnum, u16 val)
938 {
939 int port = phydev->mdio.addr; // the SoC translates port addresses to PHY addr
940
941 return write_mmd_phy(port, devnum, regnum, val);
942 }
943
944 static void rtl8380_rtl8214fc_media_set(int mac, bool set_fibre)
945 {
946 int base = mac - (mac % 4);
947 static int reg[] = {16, 19, 20, 21};
948 int val, media, power;
949
950 pr_info("%s: port %d, set_fibre: %d\n", __func__, mac, set_fibre);
951 write_phy(base, 0xfff, 29, 8);
952 read_phy(base, 0x266, reg[mac % 4], &val);
953
954 media = (val >> 10) & 0x3;
955 pr_info("Current media %x\n", media);
956 if (media & 0x2) {
957 pr_info("Powering off COPPER\n");
958 write_phy(base, 0xfff, 29, 1);
959 /* Ensure power is off */
960 read_phy(base, 0xa40, 16, &power);
961 if (!(power & (1 << 11)))
962 write_phy(base, 0xa40, 16, power | (1 << 11));
963 } else {
964 pr_info("Powering off FIBRE");
965 write_phy(base, 0xfff, 29, 3);
966 /* Ensure power is off */
967 read_phy(base, 0xa40, 16, &power);
968 if (!(power & (1 << 11)))
969 write_phy(base, 0xa40, 16, power | (1 << 11));
970 }
971
972 if (set_fibre) {
973 val |= 1 << 10;
974 val &= ~(1 << 11);
975 } else {
976 val |= 1 << 10;
977 val |= 1 << 11;
978 }
979 write_phy(base, 0xfff, 29, 8);
980 write_phy(base, 0x266, reg[mac % 4], val);
981 write_phy(base, 0xfff, 29, 0);
982
983 if (set_fibre) {
984 pr_info("Powering on FIBRE");
985 write_phy(base, 0xfff, 29, 3);
986 /* Ensure power is off */
987 read_phy(base, 0xa40, 16, &power);
988 if (power & (1 << 11))
989 write_phy(base, 0xa40, 16, power & ~(1 << 11));
990 } else {
991 pr_info("Powering on COPPER\n");
992 write_phy(base, 0xfff, 29, 1);
993 /* Ensure power is off */
994 read_phy(base, 0xa40, 16, &power);
995 if (power & (1 << 11))
996 write_phy(base, 0xa40, 16, power & ~(1 << 11));
997 }
998
999 write_phy(base, 0xfff, 29, 0);
1000 }
1001
1002 static bool rtl8380_rtl8214fc_media_is_fibre(int mac)
1003 {
1004 int base = mac - (mac % 4);
1005 static int reg[] = {16, 19, 20, 21};
1006 u32 val;
1007
1008 write_phy(base, 0xfff, 29, 8);
1009 read_phy(base, 0x266, reg[mac % 4], &val);
1010 write_phy(base, 0xfff, 29, 0);
1011 if (val & (1 << 11))
1012 return false;
1013 return true;
1014 }
1015
1016 static int rtl8214fc_set_port(struct phy_device *phydev, int port)
1017 {
1018 bool is_fibre = (port == PORT_FIBRE ? true : false);
1019 int addr = phydev->mdio.addr;
1020
1021 pr_debug("%s port %d to %d\n", __func__, addr, port);
1022
1023 rtl8380_rtl8214fc_media_set(addr, is_fibre);
1024 return 0;
1025 }
1026
1027 static int rtl8214fc_get_port(struct phy_device *phydev)
1028 {
1029 int addr = phydev->mdio.addr;
1030
1031 pr_debug("%s: port %d\n", __func__, addr);
1032 if (rtl8380_rtl8214fc_media_is_fibre(addr))
1033 return PORT_FIBRE;
1034 return PORT_MII;
1035 }
1036
1037 /*
1038 * Enable EEE on the RTL8218B PHYs
1039 * The method used is not the preferred way (which would be based on the MAC-EEE state,
1040 * but the only way that works since the kernel first enables EEE in the MAC
1041 * and then sets up the PHY. The MAC-based approach would require the oppsite.
1042 */
1043 void rtl8218d_eee_set(int port, bool enable)
1044 {
1045 u32 val;
1046 bool an_enabled;
1047
1048 pr_debug("In %s %d, enable %d\n", __func__, port, enable);
1049 /* Set GPHY page to copper */
1050 write_phy(port, 0xa42, 30, 0x0001);
1051
1052 read_phy(port, 0, 0, &val);
1053 an_enabled = val & BIT(12);
1054
1055 /* Enable 100M (bit 1) / 1000M (bit 2) EEE */
1056 read_mmd_phy(port, 7, 60, &val);
1057 val |= BIT(2) | BIT(1);
1058 write_mmd_phy(port, 7, 60, enable ? 0x6 : 0);
1059
1060 /* 500M EEE ability */
1061 read_phy(port, 0xa42, 20, &val);
1062 if (enable)
1063 val |= BIT(7);
1064 else
1065 val &= ~BIT(7);
1066 write_phy(port, 0xa42, 20, val);
1067
1068 /* Restart AN if enabled */
1069 if (an_enabled) {
1070 read_phy(port, 0, 0, &val);
1071 val |= BIT(9);
1072 write_phy(port, 0, 0, val);
1073 }
1074
1075 /* GPHY page back to auto*/
1076 write_phy(port, 0xa42, 30, 0);
1077 }
1078
1079 static int rtl8218b_get_eee(struct phy_device *phydev,
1080 struct ethtool_eee *e)
1081 {
1082 u32 val;
1083 int addr = phydev->mdio.addr;
1084
1085 pr_debug("In %s, port %d, was enabled: %d\n", __func__, addr, e->eee_enabled);
1086
1087 /* Set GPHY page to copper */
1088 write_phy(addr, 0xa42, 29, 0x0001);
1089
1090 read_phy(addr, 7, 60, &val);
1091 if (e->eee_enabled) {
1092 // Verify vs MAC-based EEE
1093 e->eee_enabled = !!(val & BIT(7));
1094 if (!e->eee_enabled) {
1095 read_phy(addr, 0x0A43, 25, &val);
1096 e->eee_enabled = !!(val & BIT(4));
1097 }
1098 }
1099 pr_debug("%s: enabled: %d\n", __func__, e->eee_enabled);
1100
1101 /* GPHY page to auto */
1102 write_phy(addr, 0xa42, 29, 0x0000);
1103
1104 return 0;
1105 }
1106
1107 static int rtl8218d_get_eee(struct phy_device *phydev,
1108 struct ethtool_eee *e)
1109 {
1110 u32 val;
1111 int addr = phydev->mdio.addr;
1112
1113 pr_debug("In %s, port %d, was enabled: %d\n", __func__, addr, e->eee_enabled);
1114
1115 /* Set GPHY page to copper */
1116 write_phy(addr, 0xa42, 30, 0x0001);
1117
1118 read_phy(addr, 7, 60, &val);
1119 if (e->eee_enabled)
1120 e->eee_enabled = !!(val & BIT(7));
1121 pr_debug("%s: enabled: %d\n", __func__, e->eee_enabled);
1122
1123 /* GPHY page to auto */
1124 write_phy(addr, 0xa42, 30, 0x0000);
1125
1126 return 0;
1127 }
1128
1129 static int rtl8214fc_set_eee(struct phy_device *phydev,
1130 struct ethtool_eee *e)
1131 {
1132 u32 poll_state;
1133 int port = phydev->mdio.addr;
1134 bool an_enabled;
1135 u32 val;
1136
1137 pr_debug("In %s port %d, enabled %d\n", __func__, port, e->eee_enabled);
1138
1139 if (rtl8380_rtl8214fc_media_is_fibre(port)) {
1140 netdev_err(phydev->attached_dev, "Port %d configured for FIBRE", port);
1141 return -ENOTSUPP;
1142 }
1143
1144 poll_state = disable_polling(port);
1145
1146 /* Set GPHY page to copper */
1147 write_phy(port, 0xa42, 29, 0x0001);
1148
1149 // Get auto-negotiation status
1150 read_phy(port, 0, 0, &val);
1151 an_enabled = val & BIT(12);
1152
1153 pr_info("%s: aneg: %d\n", __func__, an_enabled);
1154 read_phy(port, 0x0A43, 25, &val);
1155 val &= ~BIT(5); // Use MAC-based EEE
1156 write_phy(port, 0x0A43, 25, val);
1157
1158 /* Enable 100M (bit 1) / 1000M (bit 2) EEE */
1159 write_phy(port, 7, 60, e->eee_enabled ? 0x6 : 0);
1160
1161 /* 500M EEE ability */
1162 read_phy(port, 0xa42, 20, &val);
1163 if (e->eee_enabled)
1164 val |= BIT(7);
1165 else
1166 val &= ~BIT(7);
1167 write_phy(port, 0xa42, 20, val);
1168
1169 /* Restart AN if enabled */
1170 if (an_enabled) {
1171 pr_info("%s: doing aneg\n", __func__);
1172 read_phy(port, 0, 0, &val);
1173 val |= BIT(9);
1174 write_phy(port, 0, 0, val);
1175 }
1176
1177 /* GPHY page back to auto*/
1178 write_phy(port, 0xa42, 29, 0);
1179
1180 resume_polling(poll_state);
1181
1182 return 0;
1183 }
1184
1185 static int rtl8214fc_get_eee(struct phy_device *phydev,
1186 struct ethtool_eee *e)
1187 {
1188 int addr = phydev->mdio.addr;
1189
1190 pr_debug("In %s port %d, enabled %d\n", __func__, addr, e->eee_enabled);
1191 if (rtl8380_rtl8214fc_media_is_fibre(addr)) {
1192 netdev_err(phydev->attached_dev, "Port %d configured for FIBRE", addr);
1193 return -ENOTSUPP;
1194 }
1195
1196 return rtl8218b_get_eee(phydev, e);
1197 }
1198
1199 static int rtl8218b_set_eee(struct phy_device *phydev, struct ethtool_eee *e)
1200 {
1201 int port = phydev->mdio.addr;
1202 u64 poll_state;
1203 u32 val;
1204 bool an_enabled;
1205
1206 pr_info("In %s, port %d, enabled %d\n", __func__, port, e->eee_enabled);
1207
1208 poll_state = disable_polling(port);
1209
1210 /* Set GPHY page to copper */
1211 write_phy(port, 0, 30, 0x0001);
1212 read_phy(port, 0, 0, &val);
1213 an_enabled = val & BIT(12);
1214
1215 if (e->eee_enabled) {
1216 /* 100/1000M EEE Capability */
1217 write_phy(port, 0, 13, 0x0007);
1218 write_phy(port, 0, 14, 0x003C);
1219 write_phy(port, 0, 13, 0x4007);
1220 write_phy(port, 0, 14, 0x0006);
1221
1222 read_phy(port, 0x0A43, 25, &val);
1223 val |= BIT(4);
1224 write_phy(port, 0x0A43, 25, val);
1225 } else {
1226 /* 100/1000M EEE Capability */
1227 write_phy(port, 0, 13, 0x0007);
1228 write_phy(port, 0, 14, 0x003C);
1229 write_phy(port, 0, 13, 0x0007);
1230 write_phy(port, 0, 14, 0x0000);
1231
1232 read_phy(port, 0x0A43, 25, &val);
1233 val &= ~BIT(4);
1234 write_phy(port, 0x0A43, 25, val);
1235 }
1236
1237 /* Restart AN if enabled */
1238 if (an_enabled) {
1239 read_phy(port, 0, 0, &val);
1240 val |= BIT(9);
1241 write_phy(port, 0, 0, val);
1242 }
1243
1244 /* GPHY page back to auto*/
1245 write_phy(port, 0xa42, 30, 0);
1246
1247 pr_info("%s done\n", __func__);
1248 resume_polling(poll_state);
1249
1250 return 0;
1251 }
1252
1253 static int rtl8218d_set_eee(struct phy_device *phydev, struct ethtool_eee *e)
1254 {
1255 int addr = phydev->mdio.addr;
1256 u64 poll_state;
1257
1258 pr_info("In %s, port %d, enabled %d\n", __func__, addr, e->eee_enabled);
1259
1260 poll_state = disable_polling(addr);
1261
1262 rtl8218d_eee_set(addr, (bool) e->eee_enabled);
1263
1264 resume_polling(poll_state);
1265
1266 return 0;
1267 }
1268
1269 static int rtl8214c_match_phy_device(struct phy_device *phydev)
1270 {
1271 return phydev->phy_id == PHY_ID_RTL8214C;
1272 }
1273
1274 static int rtl8380_configure_rtl8214c(struct phy_device *phydev)
1275 {
1276 u32 phy_id, val;
1277 int mac = phydev->mdio.addr;
1278
1279 read_phy(mac, 0, 2, &val);
1280 phy_id = val << 16;
1281 read_phy(mac, 0, 3, &val);
1282 phy_id |= val;
1283 pr_debug("Phy on MAC %d: %x\n", mac, phy_id);
1284
1285 phydev_info(phydev, "Detected external RTL8214C\n");
1286
1287 /* GPHY auto conf */
1288 write_phy(mac, 0xa42, 29, 0);
1289 return 0;
1290 }
1291
1292 static int rtl8380_configure_rtl8214fc(struct phy_device *phydev)
1293 {
1294 u32 phy_id, val, page = 0;
1295 int i, l;
1296 int mac = phydev->mdio.addr;
1297 struct fw_header *h;
1298 u32 *rtl8380_rtl8214fc_perchip;
1299 u32 *rtl8380_rtl8214fc_perport;
1300
1301 read_phy(mac, 0, 2, &val);
1302 phy_id = val << 16;
1303 read_phy(mac, 0, 3, &val);
1304 phy_id |= val;
1305 pr_debug("Phy on MAC %d: %x\n", mac, phy_id);
1306
1307 /* Read internal PHY id */
1308 write_phy(mac, 0, 30, 0x0001);
1309 write_phy(mac, 0, 31, 0x0a42);
1310 write_phy(mac, 31, 27, 0x0002);
1311 read_phy(mac, 31, 28, &val);
1312 if (val != 0x6276) {
1313 phydev_err(phydev, "Expected external RTL8214FC, found PHY-ID %x\n", val);
1314 return -1;
1315 }
1316 phydev_info(phydev, "Detected external RTL8214FC\n");
1317
1318 h = rtl838x_request_fw(phydev, &rtl838x_8214fc_fw, FIRMWARE_838X_8214FC_1);
1319 if (!h)
1320 return -1;
1321
1322 if (h->phy != 0x8214fc00) {
1323 phydev_err(phydev, "Wrong firmware file: PHY mismatch.\n");
1324 return -1;
1325 }
1326
1327 rtl8380_rtl8214fc_perchip = (void *)h + sizeof(struct fw_header)
1328 + h->parts[0].start;
1329
1330 rtl8380_rtl8214fc_perport = (void *)h + sizeof(struct fw_header)
1331 + h->parts[1].start;
1332
1333 /* detect phy version */
1334 write_phy(mac, 0xfff, 27, 0x0004);
1335 read_phy(mac, 0xfff, 28, &val);
1336
1337 read_phy(mac, 0, 16, &val);
1338 if (val & (1 << 11))
1339 rtl8380_rtl8214fc_on_off(mac, true);
1340 else
1341 rtl8380_phy_reset(mac);
1342
1343 msleep(100);
1344 write_phy(mac, 0, 30, 0x0001);
1345
1346 i = 0;
1347 while (rtl8380_rtl8214fc_perchip[i * 3]
1348 && rtl8380_rtl8214fc_perchip[i * 3 + 1]) {
1349 if (rtl8380_rtl8214fc_perchip[i * 3 + 1] == 0x1f)
1350 page = rtl8380_rtl8214fc_perchip[i * 3 + 2];
1351 if (rtl8380_rtl8214fc_perchip[i * 3 + 1] == 0x13 && page == 0x260) {
1352 read_phy(mac + rtl8380_rtl8214fc_perchip[i * 3], 0x260, 13, &val);
1353 val = (val & 0x1f00) | (rtl8380_rtl8214fc_perchip[i * 3 + 2]
1354 & 0xe0ff);
1355 write_phy(mac + rtl8380_rtl8214fc_perchip[i * 3],
1356 0xfff, rtl8380_rtl8214fc_perchip[i * 3 + 1], val);
1357 } else {
1358 write_phy(mac + rtl8380_rtl8214fc_perchip[i * 3],
1359 0xfff, rtl8380_rtl8214fc_perchip[i * 3 + 1],
1360 rtl8380_rtl8214fc_perchip[i * 3 + 2]);
1361 }
1362 i++;
1363 }
1364
1365 /* Force copper medium */
1366 for (i = 0; i < 4; i++) {
1367 write_phy(mac + i, 0xfff, 0x1f, 0x0000);
1368 write_phy(mac + i, 0xfff, 0x1e, 0x0001);
1369 }
1370
1371 /* Enable PHY */
1372 for (i = 0; i < 4; i++) {
1373 write_phy(mac + i, 0xfff, 0x1f, 0x0000);
1374 write_phy(mac + i, 0xfff, 0x00, 0x1140);
1375 }
1376 mdelay(100);
1377
1378 /* Disable Autosensing */
1379 for (i = 0; i < 4; i++) {
1380 for (l = 0; l < 100; l++) {
1381 read_phy(mac + i, 0x0a42, 0x10, &val);
1382 if ((val & 0x7) >= 3)
1383 break;
1384 }
1385 if (l >= 100) {
1386 phydev_err(phydev, "Could not disable autosensing\n");
1387 return -1;
1388 }
1389 }
1390
1391 /* Request patch */
1392 for (i = 0; i < 4; i++) {
1393 write_phy(mac + i, 0xfff, 0x1f, 0x0b82);
1394 write_phy(mac + i, 0xfff, 0x10, 0x0010);
1395 }
1396 mdelay(300);
1397
1398 /* Verify patch readiness */
1399 for (i = 0; i < 4; i++) {
1400 for (l = 0; l < 100; l++) {
1401 read_phy(mac + i, 0xb80, 0x10, &val);
1402 if (val & 0x40)
1403 break;
1404 }
1405 if (l >= 100) {
1406 phydev_err(phydev, "Could not patch PHY\n");
1407 return -1;
1408 }
1409 }
1410
1411 /* Use Broadcast ID method for patching */
1412 write_phy(mac, 0xfff, 0x1f, 0x0000);
1413 write_phy(mac, 0xfff, 0x1d, 0x0008);
1414 write_phy(mac, 0xfff, 0x1f, 0x0266);
1415 write_phy(mac, 0xfff, 0x16, 0xff00 + mac);
1416 write_phy(mac, 0xfff, 0x1f, 0x0000);
1417 write_phy(mac, 0xfff, 0x1d, 0x0000);
1418 mdelay(1);
1419
1420 i = 0;
1421 while (rtl8380_rtl8214fc_perport[i * 2]) {
1422 write_phy(mac, 0xfff, rtl8380_rtl8214fc_perport[i * 2],
1423 rtl8380_rtl8214fc_perport[i * 2 + 1]);
1424 i++;
1425 }
1426
1427 /*Disable broadcast ID*/
1428 write_phy(mac, 0xfff, 0x1f, 0x0000);
1429 write_phy(mac, 0xfff, 0x1d, 0x0008);
1430 write_phy(mac, 0xfff, 0x1f, 0x0266);
1431 write_phy(mac, 0xfff, 0x16, 0x00 + mac);
1432 write_phy(mac, 0xfff, 0x1f, 0x0000);
1433 write_phy(mac, 0xfff, 0x1d, 0x0000);
1434 mdelay(1);
1435
1436 /* Auto medium selection */
1437 for (i = 0; i < 4; i++) {
1438 write_phy(mac + i, 0xfff, 0x1f, 0x0000);
1439 write_phy(mac + i, 0xfff, 0x1e, 0x0000);
1440 }
1441
1442 return 0;
1443 }
1444
1445 static int rtl8214fc_match_phy_device(struct phy_device *phydev)
1446 {
1447 int addr = phydev->mdio.addr;
1448
1449 return phydev->phy_id == PHY_ID_RTL8214FC && addr >= 24;
1450 }
1451
1452 static int rtl8380_configure_serdes(struct phy_device *phydev)
1453 {
1454 u32 v;
1455 u32 sds_conf_value;
1456 int i;
1457 struct fw_header *h;
1458 u32 *rtl8380_sds_take_reset;
1459 u32 *rtl8380_sds_common;
1460 u32 *rtl8380_sds01_qsgmii_6275b;
1461 u32 *rtl8380_sds23_qsgmii_6275b;
1462 u32 *rtl8380_sds4_fiber_6275b;
1463 u32 *rtl8380_sds5_fiber_6275b;
1464 u32 *rtl8380_sds_reset;
1465 u32 *rtl8380_sds_release_reset;
1466
1467 phydev_info(phydev, "Detected internal RTL8380 SERDES\n");
1468
1469 h = rtl838x_request_fw(phydev, &rtl838x_8218b_fw, FIRMWARE_838X_8380_1);
1470 if (!h)
1471 return -1;
1472
1473 if (h->magic != 0x83808380) {
1474 phydev_err(phydev, "Wrong firmware file: magic number mismatch.\n");
1475 return -1;
1476 }
1477
1478 rtl8380_sds_take_reset = (void *)h + sizeof(struct fw_header)
1479 + h->parts[0].start;
1480
1481 rtl8380_sds_common = (void *)h + sizeof(struct fw_header)
1482 + h->parts[1].start;
1483
1484 rtl8380_sds01_qsgmii_6275b = (void *)h + sizeof(struct fw_header)
1485 + h->parts[2].start;
1486
1487 rtl8380_sds23_qsgmii_6275b = (void *)h + sizeof(struct fw_header)
1488 + h->parts[3].start;
1489
1490 rtl8380_sds4_fiber_6275b = (void *)h + sizeof(struct fw_header)
1491 + h->parts[4].start;
1492
1493 rtl8380_sds5_fiber_6275b = (void *)h + sizeof(struct fw_header)
1494 + h->parts[5].start;
1495
1496 rtl8380_sds_reset = (void *)h + sizeof(struct fw_header)
1497 + h->parts[6].start;
1498
1499 rtl8380_sds_release_reset = (void *)h + sizeof(struct fw_header)
1500 + h->parts[7].start;
1501
1502 /* Back up serdes power off value */
1503 sds_conf_value = sw_r32(RTL838X_SDS_CFG_REG);
1504 pr_info("SDS power down value: %x\n", sds_conf_value);
1505
1506 /* take serdes into reset */
1507 i = 0;
1508 while (rtl8380_sds_take_reset[2 * i]) {
1509 sw_w32(rtl8380_sds_take_reset[2 * i + 1], rtl8380_sds_take_reset[2 * i]);
1510 i++;
1511 udelay(1000);
1512 }
1513
1514 /* apply common serdes patch */
1515 i = 0;
1516 while (rtl8380_sds_common[2 * i]) {
1517 sw_w32(rtl8380_sds_common[2 * i + 1], rtl8380_sds_common[2 * i]);
1518 i++;
1519 udelay(1000);
1520 }
1521
1522 /* internal R/W enable */
1523 sw_w32(3, RTL838X_INT_RW_CTRL);
1524
1525 /* SerDes ports 4 and 5 are FIBRE ports */
1526 sw_w32_mask(0x7 | 0x38, 1 | (1 << 3), RTL838X_INT_MODE_CTRL);
1527
1528 /* SerDes module settings, SerDes 0-3 are QSGMII */
1529 v = 0x6 << 25 | 0x6 << 20 | 0x6 << 15 | 0x6 << 10;
1530 /* SerDes 4 and 5 are 1000BX FIBRE */
1531 v |= 0x4 << 5 | 0x4;
1532 sw_w32(v, RTL838X_SDS_MODE_SEL);
1533
1534 pr_info("PLL control register: %x\n", sw_r32(RTL838X_PLL_CML_CTRL));
1535 sw_w32_mask(0xfffffff0, 0xaaaaaaaf & 0xf, RTL838X_PLL_CML_CTRL);
1536 i = 0;
1537 while (rtl8380_sds01_qsgmii_6275b[2 * i]) {
1538 sw_w32(rtl8380_sds01_qsgmii_6275b[2 * i + 1],
1539 rtl8380_sds01_qsgmii_6275b[2 * i]);
1540 i++;
1541 }
1542
1543 i = 0;
1544 while (rtl8380_sds23_qsgmii_6275b[2 * i]) {
1545 sw_w32(rtl8380_sds23_qsgmii_6275b[2 * i + 1], rtl8380_sds23_qsgmii_6275b[2 * i]);
1546 i++;
1547 }
1548
1549 i = 0;
1550 while (rtl8380_sds4_fiber_6275b[2 * i]) {
1551 sw_w32(rtl8380_sds4_fiber_6275b[2 * i + 1], rtl8380_sds4_fiber_6275b[2 * i]);
1552 i++;
1553 }
1554
1555 i = 0;
1556 while (rtl8380_sds5_fiber_6275b[2 * i]) {
1557 sw_w32(rtl8380_sds5_fiber_6275b[2 * i + 1], rtl8380_sds5_fiber_6275b[2 * i]);
1558 i++;
1559 }
1560
1561 i = 0;
1562 while (rtl8380_sds_reset[2 * i]) {
1563 sw_w32(rtl8380_sds_reset[2 * i + 1], rtl8380_sds_reset[2 * i]);
1564 i++;
1565 }
1566
1567 i = 0;
1568 while (rtl8380_sds_release_reset[2 * i]) {
1569 sw_w32(rtl8380_sds_release_reset[2 * i + 1], rtl8380_sds_release_reset[2 * i]);
1570 i++;
1571 }
1572
1573 pr_info("SDS power down value now: %x\n", sw_r32(RTL838X_SDS_CFG_REG));
1574 sw_w32(sds_conf_value, RTL838X_SDS_CFG_REG);
1575
1576 pr_info("Configuration of SERDES done\n");
1577 return 0;
1578 }
1579
1580 static int rtl8390_configure_serdes(struct phy_device *phydev)
1581 {
1582 phydev_info(phydev, "Detected internal RTL8390 SERDES\n");
1583
1584 /* In autoneg state, force link, set SR4_CFG_EN_LINK_FIB1G */
1585 sw_w32_mask(0, 1 << 18, RTL839X_SDS12_13_XSG0 + 0x0a);
1586
1587 /* Disable EEE: Clear FRE16_EEE_RSG_FIB1G, FRE16_EEE_STD_FIB1G,
1588 * FRE16_C1_PWRSAV_EN_FIB1G, FRE16_C2_PWRSAV_EN_FIB1G
1589 * and FRE16_EEE_QUIET_FIB1G
1590 */
1591 sw_w32_mask(0x1f << 10, 0, RTL839X_SDS12_13_XSG0 + 0xe0);
1592
1593 return 0;
1594 }
1595
1596 int rtl9300_configure_serdes(struct phy_device *phydev)
1597 {
1598 struct device *dev = &phydev->mdio.dev;
1599 int phy_addr = phydev->mdio.addr;
1600 int sds_num = 0;
1601 int v;
1602
1603 phydev_info(phydev, "Configuring internal RTL9300 SERDES\n");
1604
1605 switch (phy_addr) {
1606 case 26:
1607 sds_num = 8;
1608 break;
1609 case 27:
1610 sds_num = 9;
1611 break;
1612 default:
1613 dev_err(dev, "Not a SerDes PHY\n");
1614 return -EINVAL;
1615 }
1616
1617 /* Set default Medium to fibre */
1618 v = rtl930x_read_sds_phy(sds_num, 0x1f, 11);
1619 if (v < 0) {
1620 dev_err(dev, "Cannot access SerDes PHY %d\n", phy_addr);
1621 return -EINVAL;
1622 }
1623 v |= BIT(2);
1624 rtl930x_write_sds_phy(sds_num, 0x1f, 11, v);
1625
1626 // TODO: this needs to be configurable via ethtool/.dts
1627 pr_info("Setting 10G/1000BX auto fibre medium\n");
1628 rtl9300_sds_rst(sds_num, 0x1b);
1629
1630 // TODO: Apply patch set for fibre type
1631
1632 return 0;
1633 }
1634
1635 static int rtl8214fc_phy_probe(struct phy_device *phydev)
1636 {
1637 struct device *dev = &phydev->mdio.dev;
1638 struct rtl838x_phy_priv *priv;
1639 int addr = phydev->mdio.addr;
1640
1641 /* 839x has internal SerDes */
1642 if (soc_info.id == 0x8393)
1643 return -ENODEV;
1644
1645 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1646 if (!priv)
1647 return -ENOMEM;
1648
1649 priv->name = "RTL8214FC";
1650
1651 /* All base addresses of the PHYs start at multiples of 8 */
1652 if (!(addr % 8)) {
1653 /* Configuration must be done whil patching still possible */
1654 return rtl8380_configure_rtl8214fc(phydev);
1655 }
1656 return 0;
1657 }
1658
1659 static int rtl8214c_phy_probe(struct phy_device *phydev)
1660 {
1661 struct device *dev = &phydev->mdio.dev;
1662 struct rtl838x_phy_priv *priv;
1663 int addr = phydev->mdio.addr;
1664
1665 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1666 if (!priv)
1667 return -ENOMEM;
1668
1669 priv->name = "RTL8214C";
1670
1671 /* All base addresses of the PHYs start at multiples of 8 */
1672 if (!(addr % 8)) {
1673 /* Configuration must be done whil patching still possible */
1674 return rtl8380_configure_rtl8214c(phydev);
1675 }
1676 return 0;
1677 }
1678
1679 static int rtl8218b_ext_phy_probe(struct phy_device *phydev)
1680 {
1681 struct device *dev = &phydev->mdio.dev;
1682 struct rtl838x_phy_priv *priv;
1683 int addr = phydev->mdio.addr;
1684
1685 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1686 if (!priv)
1687 return -ENOMEM;
1688
1689 priv->name = "RTL8218B (external)";
1690
1691 /* All base addresses of the PHYs start at multiples of 8 */
1692 if (!(addr % 8) && soc_info.family == RTL8380_FAMILY_ID) {
1693 /* Configuration must be done while patching still possible */
1694 return rtl8380_configure_ext_rtl8218b(phydev);
1695 }
1696 return 0;
1697 }
1698
1699 static int rtl8218b_int_phy_probe(struct phy_device *phydev)
1700 {
1701 struct device *dev = &phydev->mdio.dev;
1702 struct rtl838x_phy_priv *priv;
1703 int addr = phydev->mdio.addr;
1704
1705 if (soc_info.family != RTL8380_FAMILY_ID)
1706 return -ENODEV;
1707 if (addr >= 24)
1708 return -ENODEV;
1709
1710 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1711 if (!priv)
1712 return -ENOMEM;
1713
1714 priv->name = "RTL8218B (internal)";
1715
1716 /* All base addresses of the PHYs start at multiples of 8 */
1717 if (!(addr % 8)) {
1718 /* Configuration must be done while patching still possible */
1719 return rtl8380_configure_int_rtl8218b(phydev);
1720 }
1721 return 0;
1722 }
1723
1724 static int rtl8218d_phy_probe(struct phy_device *phydev)
1725 {
1726 struct device *dev = &phydev->mdio.dev;
1727 struct rtl838x_phy_priv *priv;
1728 int addr = phydev->mdio.addr;
1729
1730 pr_info("%s: id: %d\n", __func__, addr);
1731 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1732 if (!priv)
1733 return -ENOMEM;
1734
1735 priv->name = "RTL8218D";
1736
1737 /* All base addresses of the PHYs start at multiples of 8 */
1738 if (!(addr % 8)) {
1739 /* Configuration must be done while patching still possible */
1740 // TODO: return configure_rtl8218d(phydev);
1741 }
1742 return 0;
1743 }
1744
1745 static int rtl8226_phy_probe(struct phy_device *phydev)
1746 {
1747 struct device *dev = &phydev->mdio.dev;
1748 struct rtl838x_phy_priv *priv;
1749 int addr = phydev->mdio.addr;
1750
1751 pr_info("%s: id: %d\n", __func__, addr);
1752 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1753 if (!priv)
1754 return -ENOMEM;
1755
1756 priv->name = "RTL8226";
1757
1758 return 0;
1759 }
1760
1761 static int rtl838x_serdes_probe(struct phy_device *phydev)
1762 {
1763 struct device *dev = &phydev->mdio.dev;
1764 struct rtl838x_phy_priv *priv;
1765 int addr = phydev->mdio.addr;
1766
1767 if (soc_info.family != RTL8380_FAMILY_ID)
1768 return -ENODEV;
1769 if (addr < 24)
1770 return -ENODEV;
1771
1772 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1773 if (!priv)
1774 return -ENOMEM;
1775
1776 priv->name = "RTL8380 Serdes";
1777
1778 /* On the RTL8380M, PHYs 24-27 connect to the internal SerDes */
1779 if (soc_info.id == 0x8380) {
1780 if (addr == 24)
1781 return rtl8380_configure_serdes(phydev);
1782 return 0;
1783 }
1784 return -ENODEV;
1785 }
1786
1787 static int rtl8393_serdes_probe(struct phy_device *phydev)
1788 {
1789 struct device *dev = &phydev->mdio.dev;
1790 struct rtl838x_phy_priv *priv;
1791 int addr = phydev->mdio.addr;
1792
1793 pr_info("%s: id: %d\n", __func__, addr);
1794 if (soc_info.family != RTL8390_FAMILY_ID)
1795 return -ENODEV;
1796
1797 if (addr < 24)
1798 return -ENODEV;
1799
1800 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1801 if (!priv)
1802 return -ENOMEM;
1803
1804 priv->name = "RTL8393 Serdes";
1805 return rtl8390_configure_serdes(phydev);
1806 }
1807
1808 static int rtl8390_serdes_probe(struct phy_device *phydev)
1809 {
1810 struct device *dev = &phydev->mdio.dev;
1811 struct rtl838x_phy_priv *priv;
1812 int addr = phydev->mdio.addr;
1813
1814 if (soc_info.family != RTL8390_FAMILY_ID)
1815 return -ENODEV;
1816
1817 if (addr < 24)
1818 return -ENODEV;
1819
1820 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1821 if (!priv)
1822 return -ENOMEM;
1823
1824 priv->name = "RTL8390 Serdes";
1825 return rtl8390_configure_generic(phydev);
1826 }
1827
1828 static int rtl9300_serdes_probe(struct phy_device *phydev)
1829 {
1830 struct device *dev = &phydev->mdio.dev;
1831 struct rtl838x_phy_priv *priv;
1832 int addr = phydev->mdio.addr;
1833
1834 if (soc_info.family != RTL9300_FAMILY_ID)
1835 return -ENODEV;
1836
1837 if (addr < 24)
1838 return -ENODEV;
1839
1840 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1841 if (!priv)
1842 return -ENOMEM;
1843
1844 priv->name = "RTL9300 Serdes";
1845 return rtl9300_configure_serdes(phydev);
1846 }
1847
1848 static struct phy_driver rtl83xx_phy_driver[] = {
1849 {
1850 PHY_ID_MATCH_MODEL(PHY_ID_RTL8214C),
1851 .name = "Realtek RTL8214C",
1852 .features = PHY_GBIT_FEATURES,
1853 .match_phy_device = rtl8214c_match_phy_device,
1854 .probe = rtl8214c_phy_probe,
1855 .suspend = genphy_suspend,
1856 .resume = genphy_resume,
1857 .set_loopback = genphy_loopback,
1858 },
1859 {
1860 PHY_ID_MATCH_MODEL(PHY_ID_RTL8214FC),
1861 .name = "Realtek RTL8214FC",
1862 .features = PHY_GBIT_FIBRE_FEATURES,
1863 .match_phy_device = rtl8214fc_match_phy_device,
1864 .probe = rtl8214fc_phy_probe,
1865 .suspend = genphy_suspend,
1866 .resume = genphy_resume,
1867 .set_loopback = genphy_loopback,
1868 .read_mmd = rtl8218b_read_mmd,
1869 .write_mmd = rtl8218b_write_mmd,
1870 .set_port = rtl8214fc_set_port,
1871 .get_port = rtl8214fc_get_port,
1872 .set_eee = rtl8214fc_set_eee,
1873 .get_eee = rtl8214fc_get_eee,
1874 },
1875 {
1876 PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_E),
1877 .name = "Realtek RTL8218B (external)",
1878 .features = PHY_GBIT_FEATURES,
1879 .match_phy_device = rtl8218b_ext_match_phy_device,
1880 .probe = rtl8218b_ext_phy_probe,
1881 .suspend = genphy_suspend,
1882 .resume = genphy_resume,
1883 .set_loopback = genphy_loopback,
1884 .read_mmd = rtl8218b_read_mmd,
1885 .write_mmd = rtl8218b_write_mmd,
1886 .set_eee = rtl8218b_set_eee,
1887 .get_eee = rtl8218b_get_eee,
1888 },
1889 {
1890 PHY_ID_MATCH_MODEL(PHY_ID_RTL8218D),
1891 .name = "REALTEK RTL8218D",
1892 .features = PHY_GBIT_FEATURES,
1893 .probe = rtl8218d_phy_probe,
1894 .suspend = genphy_suspend,
1895 .resume = genphy_resume,
1896 .set_loopback = genphy_loopback,
1897 .set_eee = rtl8218d_set_eee,
1898 .get_eee = rtl8218d_get_eee,
1899 },
1900 {
1901 PHY_ID_MATCH_MODEL(PHY_ID_RTL8226),
1902 .name = "REALTEK RTL8226",
1903 .features = PHY_GBIT_FEATURES,
1904 .probe = rtl8226_phy_probe,
1905 .suspend = genphy_suspend,
1906 .resume = genphy_resume,
1907 .set_loopback = genphy_loopback,
1908 .read_mmd = rtl8226_read_mmd,
1909 .write_mmd = rtl8226_write_mmd,
1910 .read_page = rtl8226_read_page,
1911 .write_page = rtl8226_write_page,
1912 .read_status = rtl8226_read_status,
1913 .config_aneg = rtl8226_config_aneg,
1914 .set_eee = rtl8226_set_eee,
1915 .get_eee = rtl8226_get_eee,
1916 },
1917 {
1918 PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_I),
1919 .name = "Realtek RTL8218B (internal)",
1920 .features = PHY_GBIT_FEATURES,
1921 .probe = rtl8218b_int_phy_probe,
1922 .suspend = genphy_suspend,
1923 .resume = genphy_resume,
1924 .set_loopback = genphy_loopback,
1925 .read_mmd = rtl8218b_read_mmd,
1926 .write_mmd = rtl8218b_write_mmd,
1927 .set_eee = rtl8218b_set_eee,
1928 .get_eee = rtl8218b_get_eee,
1929 },
1930 {
1931 PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_I),
1932 .name = "Realtek RTL8380 SERDES",
1933 .features = PHY_GBIT_FIBRE_FEATURES,
1934 .probe = rtl838x_serdes_probe,
1935 .suspend = genphy_suspend,
1936 .resume = genphy_resume,
1937 .set_loopback = genphy_loopback,
1938 .read_mmd = rtl8218b_read_mmd,
1939 .write_mmd = rtl8218b_write_mmd,
1940 .read_status = rtl8380_read_status,
1941 },
1942 {
1943 PHY_ID_MATCH_MODEL(PHY_ID_RTL8393_I),
1944 .name = "Realtek RTL8393 SERDES",
1945 .features = PHY_GBIT_FIBRE_FEATURES,
1946 .probe = rtl8393_serdes_probe,
1947 .suspend = genphy_suspend,
1948 .resume = genphy_resume,
1949 .set_loopback = genphy_loopback,
1950 .read_status = rtl8393_read_status,
1951 },
1952 {
1953 PHY_ID_MATCH_MODEL(PHY_ID_RTL8390_GENERIC),
1954 .name = "Realtek RTL8390 Generic",
1955 .features = PHY_GBIT_FIBRE_FEATURES,
1956 .probe = rtl8390_serdes_probe,
1957 .suspend = genphy_suspend,
1958 .resume = genphy_resume,
1959 .set_loopback = genphy_loopback,
1960 },
1961 {
1962 PHY_ID_MATCH_MODEL(PHY_ID_RTL9300_I),
1963 .name = "REALTEK RTL9300 SERDES",
1964 .features = PHY_GBIT_FIBRE_FEATURES,
1965 .probe = rtl9300_serdes_probe,
1966 .suspend = genphy_suspend,
1967 .resume = genphy_resume,
1968 .set_loopback = genphy_loopback,
1969 },
1970 };
1971
1972 module_phy_driver(rtl83xx_phy_driver);
1973
1974 static struct mdio_device_id __maybe_unused rtl83xx_tbl[] = {
1975 { PHY_ID_MATCH_MODEL(PHY_ID_RTL8214FC) },
1976 { }
1977 };
1978
1979 MODULE_DEVICE_TABLE(mdio, rtl83xx_tbl);
1980
1981 MODULE_AUTHOR("B. Koblitz");
1982 MODULE_DESCRIPTION("RTL83xx PHY driver");
1983 MODULE_LICENSE("GPL");
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