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realtek: improve EEE support for RTL8380/8390/9300
[openwrt/openwrt.git] / target / linux / realtek / files-5.4 / drivers / net / phy / rtl83xx-phy.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Realtek RTL838X Ethernet MDIO interface driver
3 *
4 * Copyright (C) 2020 B. Koblitz
5 */
6
7 #include <linux/module.h>
8 #include <linux/delay.h>
9 #include <linux/phy.h>
10 #include <linux/netdevice.h>
11 #include <linux/firmware.h>
12 #include <linux/crc32.h>
13
14 #include <asm/mach-rtl838x/mach-rtl83xx.h>
15 #include "rtl83xx-phy.h"
16
17
18 extern struct rtl83xx_soc_info soc_info;
19 extern struct mutex smi_lock;
20
21 static const struct firmware rtl838x_8380_fw;
22 static const struct firmware rtl838x_8214fc_fw;
23 static const struct firmware rtl838x_8218b_fw;
24
25 int rtl930x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val);
26 int rtl930x_write_mmd_phy(u32 port, u32 addr, u32 reg, u32 val);
27
28 static int read_phy(u32 port, u32 page, u32 reg, u32 *val)
29 { switch (soc_info.family) {
30 case RTL8380_FAMILY_ID:
31 return rtl838x_read_phy(port, page, reg, val);
32 case RTL8390_FAMILY_ID:
33 return rtl839x_read_phy(port, page, reg, val);
34 case RTL9300_FAMILY_ID:
35 return rtl930x_read_phy(port, page, reg, val);
36 case RTL9310_FAMILY_ID:
37 return rtl931x_read_phy(port, page, reg, val);
38 }
39 return -1;
40 }
41
42 static int write_phy(u32 port, u32 page, u32 reg, u32 val)
43 {
44 switch (soc_info.family) {
45 case RTL8380_FAMILY_ID:
46 return rtl838x_write_phy(port, page, reg, val);
47 case RTL8390_FAMILY_ID:
48 return rtl839x_write_phy(port, page, reg, val);
49 case RTL9300_FAMILY_ID:
50 return rtl930x_write_phy(port, page, reg, val);
51 case RTL9310_FAMILY_ID:
52 return rtl931x_write_phy(port, page, reg, val);
53 }
54 return -1;
55 }
56
57 static void rtl8380_int_phy_on_off(int mac, bool on)
58 {
59 u32 val;
60
61 read_phy(mac, 0, 0, &val);
62 if (on)
63 write_phy(mac, 0, 0, val & ~BIT(11));
64 else
65 write_phy(mac, 0, 0, val | BIT(11));
66 }
67
68 static void rtl8380_rtl8214fc_on_off(int mac, bool on)
69 {
70 u32 val;
71
72 /* fiber ports */
73 write_phy(mac, 4095, 30, 3);
74 read_phy(mac, 0, 16, &val);
75 if (on)
76 write_phy(mac, 0, 16, val & ~BIT(11));
77 else
78 write_phy(mac, 0, 16, val | BIT(11));
79
80 /* copper ports */
81 write_phy(mac, 4095, 30, 1);
82 read_phy(mac, 0, 16, &val);
83 if (on)
84 write_phy(mac, 0xa40, 16, val & ~BIT(11));
85 else
86 write_phy(mac, 0xa40, 16, val | BIT(11));
87 }
88
89 static void rtl8380_phy_reset(int mac)
90 {
91 u32 val;
92
93 read_phy(mac, 0, 0, &val);
94 write_phy(mac, 0, 0, val | BIT(15));
95 }
96
97 static void rtl8380_sds_rst(int mac)
98 {
99 u32 offset = (mac == 24) ? 0 : 0x100;
100
101 sw_w32_mask(1 << 11, 0, RTL8380_SDS4_FIB_REG0 + offset);
102 sw_w32_mask(0x3, 0, RTL838X_SDS4_REG28 + offset);
103 sw_w32_mask(0x3, 0x3, RTL838X_SDS4_REG28 + offset);
104 sw_w32_mask(0, 0x1 << 6, RTL838X_SDS4_DUMMY0 + offset);
105 sw_w32_mask(0x1 << 6, 0, RTL838X_SDS4_DUMMY0 + offset);
106 pr_info("SERDES reset: %d\n", mac);
107 }
108
109 /*
110 * Reset the SerDes by powering it off and set a new operations mode
111 * of the SerDes. 0x1f is off. Other modes are
112 * 0x01: QSGMII 0x04: 1000BX_FIBER 0x05: FIBER100
113 * 0x06: QSGMII 0x09: RSGMII 0x0d: USXGMII
114 * 0x10: XSGMII 0x12: HISGMII 0x16: 2500Base_X
115 * 0x17: RXAUI_LITE 0x19: RXAUI_PLUS 0x1a: 10G Base-R
116 * 0x1b: 10GR1000BX_AUTO 0x1f: OFF
117 */
118 void rtl9300_sds_rst(int sds_num, u32 mode)
119 {
120 // The access registers for SDS_MODE_SEL and the LSB for each SDS within
121 u16 regs[] = { 0x0194, 0x0194, 0x0194, 0x0194, 0x02a0, 0x02a0, 0x02a0, 0x02a0,
122 0x02A4, 0x02A4, 0x0198, 0x0198 };
123 u8 lsb[] = { 0, 6, 12, 18, 0, 6, 12, 18, 0, 6, 0, 6};
124
125 pr_info("SerDes: %s %d\n", __func__, mode);
126 if (sds_num < 0 || sds_num > 11) {
127 pr_err("Wrong SerDes number: %d\n", sds_num);
128 return;
129 }
130
131 sw_w32_mask(0x1f << lsb[sds_num], 0x1f << lsb[sds_num], regs[sds_num]);
132 mdelay(10);
133
134 sw_w32_mask(0x1f << lsb[sds_num], mode << lsb[sds_num], regs[sds_num]);
135 mdelay(10);
136
137 pr_info("SDS: 194:%08x 198:%08x 2a0:%08x 2a4:%08x\n",
138 sw_r32(0x194), sw_r32(0x198), sw_r32(0x2a0), sw_r32(0x2a4));
139 }
140
141 /*
142 * On the RTL839x family of SoCs with inbuilt SerDes, these SerDes are accessed through
143 * a 2048 bit register that holds the contents of the PHY being simulated by the SoC.
144 */
145 int rtl839x_read_sds_phy(int phy_addr, int phy_reg)
146 {
147 int offset = 0;
148 int reg;
149 u32 val;
150
151 if (phy_addr == 49)
152 offset = 0x100;
153
154 /*
155 * For the RTL8393 internal SerDes, we simulate a PHY ID in registers 2/3
156 * which would otherwise read as 0.
157 */
158 if (soc_info.id == 0x8393) {
159 if (phy_reg == 2)
160 return 0x1c;
161 if (phy_reg == 3)
162 return 0x8393;
163 }
164
165 /*
166 * Register RTL839X_SDS12_13_XSG0 is 2048 bit broad, the MSB (bit 15) of the
167 * 0th PHY register is bit 1023 (in byte 0x80). Because PHY-registers are 16
168 * bit broad, we offset by reg << 1. In the SoC 2 registers are stored in
169 * one 32 bit register.
170 */
171 reg = (phy_reg << 1) & 0xfc;
172 val = sw_r32(RTL839X_SDS12_13_XSG0 + offset + 0x80 + reg);
173
174 if (phy_reg & 1)
175 val = (val >> 16) & 0xffff;
176 else
177 val &= 0xffff;
178 return val;
179 }
180
181 /*
182 * On the RTL930x family of SoCs, the internal SerDes are accessed through an IO
183 * register which simulates commands to an internal MDIO bus.
184 */
185 int rtl930x_read_sds_phy(int phy_addr, int page, int phy_reg)
186 {
187 int i;
188 u32 cmd = phy_addr << 2 | page << 7 | phy_reg << 13 | 1;
189
190 pr_info("%s: phy_addr %d, phy_reg: %d\n", __func__, phy_addr, phy_reg);
191 sw_w32(cmd, RTL930X_SDS_INDACS_CMD);
192
193 for (i = 0; i < 100; i++) {
194 if (!(sw_r32(RTL930X_SDS_INDACS_CMD) & 0x1))
195 break;
196 mdelay(1);
197 }
198
199 if (i >= 100)
200 return -EIO;
201
202 pr_info("%s: returning %04x\n", __func__, sw_r32(RTL930X_SDS_INDACS_DATA) & 0xffff);
203 return sw_r32(RTL930X_SDS_INDACS_DATA) & 0xffff;
204 }
205
206 int rtl930x_write_sds_phy(int phy_addr, int page, int phy_reg, u16 v)
207 {
208 int i;
209 u32 cmd;
210
211 sw_w32(v, RTL930X_SDS_INDACS_DATA);
212 cmd = phy_addr << 2 | page << 7 | phy_reg << 13 | 0x3;
213
214 for (i = 0; i < 100; i++) {
215 if (!(sw_r32(RTL930X_SDS_INDACS_CMD) & 0x1))
216 break;
217 mdelay(1);
218 }
219
220 if (i >= 100)
221 return -EIO;
222
223 return 0;
224 }
225
226 /*
227 * On the RTL838x SoCs, the internal SerDes is accessed through direct access to
228 * standard PHY registers, where a 32 bit register holds a 16 bit word as found
229 * in a standard page 0 of a PHY
230 */
231 int rtl838x_read_sds_phy(int phy_addr, int phy_reg)
232 {
233 int offset = 0;
234 u32 val;
235
236 if (phy_addr == 26)
237 offset = 0x100;
238 val = sw_r32(RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2)) & 0xffff;
239
240 return val;
241 }
242
243 int rtl839x_write_sds_phy(int phy_addr, int phy_reg, u16 v)
244 {
245 int offset = 0;
246 int reg;
247 u32 val;
248
249 if (phy_addr == 49)
250 offset = 0x100;
251
252 reg = (phy_reg << 1) & 0xfc;
253 val = v;
254 if (phy_reg & 1) {
255 val = val << 16;
256 sw_w32_mask(0xffff0000, val,
257 RTL839X_SDS12_13_XSG0 + offset + 0x80 + reg);
258 } else {
259 sw_w32_mask(0xffff, val,
260 RTL839X_SDS12_13_XSG0 + offset + 0x80 + reg);
261 }
262
263 return 0;
264 }
265
266 /* Read the link and speed status of the 2 internal SGMII/1000Base-X
267 * ports of the RTL838x SoCs
268 */
269 static int rtl8380_read_status(struct phy_device *phydev)
270 {
271 int err;
272
273 err = genphy_read_status(phydev);
274
275 if (phydev->link) {
276 phydev->speed = SPEED_1000;
277 phydev->duplex = DUPLEX_FULL;
278 }
279
280 return err;
281 }
282
283 /* Read the link and speed status of the 2 internal SGMII/1000Base-X
284 * ports of the RTL8393 SoC
285 */
286 static int rtl8393_read_status(struct phy_device *phydev)
287 {
288 int offset = 0;
289 int err;
290 int phy_addr = phydev->mdio.addr;
291 u32 v;
292
293 err = genphy_read_status(phydev);
294 if (phy_addr == 49)
295 offset = 0x100;
296
297 if (phydev->link) {
298 phydev->speed = SPEED_100;
299 /* Read SPD_RD_00 (bit 13) and SPD_RD_01 (bit 6) out of the internal
300 * PHY registers
301 */
302 v = sw_r32(RTL839X_SDS12_13_XSG0 + offset + 0x80);
303 if (!(v & (1 << 13)) && (v & (1 << 6)))
304 phydev->speed = SPEED_1000;
305 phydev->duplex = DUPLEX_FULL;
306 }
307
308 return err;
309 }
310 static int rtl8226_read_page(struct phy_device *phydev)
311 {
312 return __phy_read(phydev, 0x1f);
313 }
314
315 static int rtl8226_write_page(struct phy_device *phydev, int page)
316 {
317 return __phy_write(phydev, 0x1f, page);
318 }
319
320 static int rtl8226_read_status(struct phy_device *phydev)
321 {
322 int ret = 0, i;
323 u32 val;
324 int port = phydev->mdio.addr;
325
326 // TODO: ret = genphy_read_status(phydev);
327 // if (ret < 0) {
328 // pr_info("%s: genphy_read_status failed\n", __func__);
329 // return ret;
330 // }
331
332 // Link status must be read twice
333 for (i = 0; i < 2; i++) {
334 rtl930x_read_mmd_phy(port, MMD_VEND2, 0xA402, &val);
335 }
336 phydev->link = val & BIT(2) ? 1 : 0;
337 if (!phydev->link)
338 goto out;
339
340 // Read duplex status
341 ret = rtl930x_read_mmd_phy(port, MMD_VEND2, 0xA434, &val);
342 if (ret)
343 goto out;
344 phydev->duplex = !!(val & BIT(3));
345
346 // Read speed
347 ret = rtl930x_read_mmd_phy(port, MMD_VEND2, 0xA434, &val);
348 switch (val & 0x0630) {
349 case 0x0000:
350 phydev->speed = SPEED_10;
351 break;
352 case 0x0010:
353 phydev->speed = SPEED_100;
354 break;
355 case 0x0020:
356 phydev->speed = SPEED_1000;
357 break;
358 case 0x0200:
359 phydev->speed = SPEED_10000;
360 break;
361 case 0x0210:
362 phydev->speed = SPEED_2500;
363 break;
364 case 0x0220:
365 phydev->speed = SPEED_5000;
366 break;
367 default:
368 break;
369 }
370 out:
371 return ret;
372 }
373
374 static int rtl8266_advertise_aneg(struct phy_device *phydev)
375 {
376 int ret = 0;
377 u32 v;
378 int port = phydev->mdio.addr;
379
380 pr_info("In %s\n", __func__);
381
382 ret = rtl930x_read_mmd_phy(port, MMD_AN, 16, &v);
383 if (ret)
384 goto out;
385
386 v |= BIT(5); // HD 10M
387 v |= BIT(6); // FD 10M
388 v |= BIT(7); // HD 100M
389 v |= BIT(8); // FD 100M
390
391 ret = rtl930x_write_mmd_phy(port, MMD_AN, 16, v);
392
393 // Allow 1GBit
394 ret = rtl930x_read_mmd_phy(port, MMD_VEND2, 0xA412, &v);
395 if (ret)
396 goto out;
397 v |= BIT(9); // FD 1000M
398
399 ret = rtl930x_write_mmd_phy(port, MMD_VEND2, 0xA412, v);
400 if (ret)
401 goto out;
402
403 // Allow 2.5G
404 ret = rtl930x_read_mmd_phy(port, MMD_AN, 32, &v);
405 if (ret)
406 goto out;
407
408 v |= BIT(7);
409 ret = rtl930x_write_mmd_phy(port, MMD_AN, 32, v);
410
411 out:
412 return ret;
413 }
414
415
416 static int rtl8226_config_aneg(struct phy_device *phydev)
417 {
418 int ret = 0;
419 u32 v;
420 int port = phydev->mdio.addr;
421
422 pr_info("In %s\n", __func__);
423 if (phydev->autoneg == AUTONEG_ENABLE) {
424 ret = rtl8266_advertise_aneg(phydev);
425 if (ret)
426 goto out;
427 // AutoNegotiationEnable
428 ret = rtl930x_read_mmd_phy(port, MMD_AN, 0, &v);
429 if (ret)
430 goto out;
431
432 v |= BIT(12); // Enable AN
433 ret = rtl930x_write_mmd_phy(port, MMD_AN, 0, v);
434 if (ret)
435 goto out;
436
437 // RestartAutoNegotiation
438 ret = rtl930x_read_mmd_phy(port, MMD_VEND2, 0xA400, &v);
439 if (ret)
440 goto out;
441 v |= BIT(9);
442
443 ret = rtl930x_write_mmd_phy(port, MMD_VEND2, 0xA400, v);
444 }
445
446 pr_info("%s: Ret is already: %d\n", __func__, ret);
447 // TODO: ret = __genphy_config_aneg(phydev, ret);
448
449 out:
450 pr_info("%s: And ret is now: %d\n", __func__, ret);
451 return ret;
452 }
453
454 static struct fw_header *rtl838x_request_fw(struct phy_device *phydev,
455 const struct firmware *fw,
456 const char *name)
457 {
458 struct device *dev = &phydev->mdio.dev;
459 int err;
460 struct fw_header *h;
461 uint32_t checksum, my_checksum;
462
463 err = request_firmware(&fw, name, dev);
464 if (err < 0)
465 goto out;
466
467 if (fw->size < sizeof(struct fw_header)) {
468 pr_err("Firmware size too small.\n");
469 err = -EINVAL;
470 goto out;
471 }
472
473 h = (struct fw_header *) fw->data;
474 pr_info("Firmware loaded. Size %d, magic: %08x\n", fw->size, h->magic);
475
476 if (h->magic != 0x83808380) {
477 pr_err("Wrong firmware file: MAGIC mismatch.\n");
478 goto out;
479 }
480
481 checksum = h->checksum;
482 h->checksum = 0;
483 my_checksum = ~crc32(0xFFFFFFFFU, fw->data, fw->size);
484 if (checksum != my_checksum) {
485 pr_err("Firmware checksum mismatch.\n");
486 err = -EINVAL;
487 goto out;
488 }
489 h->checksum = checksum;
490
491 return h;
492 out:
493 dev_err(dev, "Unable to load firmware %s (%d)\n", name, err);
494 return NULL;
495 }
496
497 static int rtl8390_configure_generic(struct phy_device *phydev)
498 {
499 u32 val, phy_id;
500 int mac = phydev->mdio.addr;
501
502 read_phy(mac, 0, 2, &val);
503 phy_id = val << 16;
504 read_phy(mac, 0, 3, &val);
505 phy_id |= val;
506 pr_debug("Phy on MAC %d: %x\n", mac, phy_id);
507
508 /* Read internal PHY ID */
509 write_phy(mac, 31, 27, 0x0002);
510 read_phy(mac, 31, 28, &val);
511
512 /* Internal RTL8218B, version 2 */
513 phydev_info(phydev, "Detected unknown %x\n", val);
514 return 0;
515 }
516
517 static int rtl8380_configure_int_rtl8218b(struct phy_device *phydev)
518 {
519 u32 val, phy_id;
520 int i, p, ipd_flag;
521 int mac = phydev->mdio.addr;
522 struct fw_header *h;
523 u32 *rtl838x_6275B_intPhy_perport;
524 u32 *rtl8218b_6276B_hwEsd_perport;
525
526
527 read_phy(mac, 0, 2, &val);
528 phy_id = val << 16;
529 read_phy(mac, 0, 3, &val);
530 phy_id |= val;
531 pr_debug("Phy on MAC %d: %x\n", mac, phy_id);
532
533 /* Read internal PHY ID */
534 write_phy(mac, 31, 27, 0x0002);
535 read_phy(mac, 31, 28, &val);
536 if (val != 0x6275) {
537 phydev_err(phydev, "Expected internal RTL8218B, found PHY-ID %x\n", val);
538 return -1;
539 }
540
541 /* Internal RTL8218B, version 2 */
542 phydev_info(phydev, "Detected internal RTL8218B\n");
543
544 h = rtl838x_request_fw(phydev, &rtl838x_8380_fw, FIRMWARE_838X_8380_1);
545 if (!h)
546 return -1;
547
548 if (h->phy != 0x83800000) {
549 phydev_err(phydev, "Wrong firmware file: PHY mismatch.\n");
550 return -1;
551 }
552
553 rtl838x_6275B_intPhy_perport = (void *)h + sizeof(struct fw_header)
554 + h->parts[8].start;
555
556 rtl8218b_6276B_hwEsd_perport = (void *)h + sizeof(struct fw_header)
557 + h->parts[9].start;
558
559 if (sw_r32(RTL838X_DMY_REG31) == 0x1)
560 ipd_flag = 1;
561
562 read_phy(mac, 0, 0, &val);
563 if (val & (1 << 11))
564 rtl8380_int_phy_on_off(mac, true);
565 else
566 rtl8380_phy_reset(mac);
567 msleep(100);
568
569 /* Ready PHY for patch */
570 for (p = 0; p < 8; p++) {
571 write_phy(mac + p, 0xfff, 0x1f, 0x0b82);
572 write_phy(mac + p, 0xfff, 0x10, 0x0010);
573 }
574 msleep(500);
575 for (p = 0; p < 8; p++) {
576 for (i = 0; i < 100 ; i++) {
577 read_phy(mac + p, 0x0b80, 0x10, &val);
578 if (val & 0x40)
579 break;
580 }
581 if (i >= 100) {
582 phydev_err(phydev,
583 "ERROR: Port %d not ready for patch.\n",
584 mac + p);
585 return -1;
586 }
587 }
588 for (p = 0; p < 8; p++) {
589 i = 0;
590 while (rtl838x_6275B_intPhy_perport[i * 2]) {
591 write_phy(mac + p, 0xfff,
592 rtl838x_6275B_intPhy_perport[i * 2],
593 rtl838x_6275B_intPhy_perport[i * 2 + 1]);
594 i++;
595 }
596 i = 0;
597 while (rtl8218b_6276B_hwEsd_perport[i * 2]) {
598 write_phy(mac + p, 0xfff,
599 rtl8218b_6276B_hwEsd_perport[i * 2],
600 rtl8218b_6276B_hwEsd_perport[i * 2 + 1]);
601 i++;
602 }
603 }
604 return 0;
605 }
606
607 static int rtl8380_configure_ext_rtl8218b(struct phy_device *phydev)
608 {
609 u32 val, ipd, phy_id;
610 int i, l;
611 int mac = phydev->mdio.addr;
612 struct fw_header *h;
613 u32 *rtl8380_rtl8218b_perchip;
614 u32 *rtl8218B_6276B_rtl8380_perport;
615 u32 *rtl8380_rtl8218b_perport;
616
617 if (soc_info.family == RTL8380_FAMILY_ID && mac != 0 && mac != 16) {
618 phydev_err(phydev, "External RTL8218B must have PHY-IDs 0 or 16!\n");
619 return -1;
620 }
621 read_phy(mac, 0, 2, &val);
622 phy_id = val << 16;
623 read_phy(mac, 0, 3, &val);
624 phy_id |= val;
625 pr_info("Phy on MAC %d: %x\n", mac, phy_id);
626
627 /* Read internal PHY ID */
628 write_phy(mac, 31, 27, 0x0002);
629 read_phy(mac, 31, 28, &val);
630 if (val != 0x6276) {
631 phydev_err(phydev, "Expected external RTL8218B, found PHY-ID %x\n", val);
632 return -1;
633 }
634 phydev_info(phydev, "Detected external RTL8218B\n");
635
636 h = rtl838x_request_fw(phydev, &rtl838x_8218b_fw, FIRMWARE_838X_8218b_1);
637 if (!h)
638 return -1;
639
640 if (h->phy != 0x8218b000) {
641 phydev_err(phydev, "Wrong firmware file: PHY mismatch.\n");
642 return -1;
643 }
644
645 rtl8380_rtl8218b_perchip = (void *)h + sizeof(struct fw_header)
646 + h->parts[0].start;
647
648 rtl8218B_6276B_rtl8380_perport = (void *)h + sizeof(struct fw_header)
649 + h->parts[1].start;
650
651 rtl8380_rtl8218b_perport = (void *)h + sizeof(struct fw_header)
652 + h->parts[2].start;
653
654 read_phy(mac, 0, 0, &val);
655 if (val & (1 << 11))
656 rtl8380_int_phy_on_off(mac, true);
657 else
658 rtl8380_phy_reset(mac);
659 msleep(100);
660
661 /* Get Chip revision */
662 write_phy(mac, 0xfff, 0x1f, 0x0);
663 write_phy(mac, 0xfff, 0x1b, 0x4);
664 read_phy(mac, 0xfff, 0x1c, &val);
665
666 i = 0;
667 while (rtl8380_rtl8218b_perchip[i * 3]
668 && rtl8380_rtl8218b_perchip[i * 3 + 1]) {
669 write_phy(mac + rtl8380_rtl8218b_perchip[i * 3],
670 0xfff, rtl8380_rtl8218b_perchip[i * 3 + 1],
671 rtl8380_rtl8218b_perchip[i * 3 + 2]);
672 i++;
673 }
674
675 /* Enable PHY */
676 for (i = 0; i < 8; i++) {
677 write_phy(mac + i, 0xfff, 0x1f, 0x0000);
678 write_phy(mac + i, 0xfff, 0x00, 0x1140);
679 }
680 mdelay(100);
681
682 /* Request patch */
683 for (i = 0; i < 8; i++) {
684 write_phy(mac + i, 0xfff, 0x1f, 0x0b82);
685 write_phy(mac + i, 0xfff, 0x10, 0x0010);
686 }
687 mdelay(300);
688
689 /* Verify patch readiness */
690 for (i = 0; i < 8; i++) {
691 for (l = 0; l < 100; l++) {
692 read_phy(mac + i, 0xb80, 0x10, &val);
693 if (val & 0x40)
694 break;
695 }
696 if (l >= 100) {
697 phydev_err(phydev, "Could not patch PHY\n");
698 return -1;
699 }
700 }
701
702 /* Use Broadcast ID method for patching */
703 write_phy(mac, 0xfff, 0x1f, 0x0000);
704 write_phy(mac, 0xfff, 0x1d, 0x0008);
705 write_phy(mac, 0xfff, 0x1f, 0x0266);
706 write_phy(mac, 0xfff, 0x16, 0xff00 + mac);
707 write_phy(mac, 0xfff, 0x1f, 0x0000);
708 write_phy(mac, 0xfff, 0x1d, 0x0000);
709 mdelay(1);
710
711 write_phy(mac, 0xfff, 30, 8);
712 write_phy(mac, 0x26e, 17, 0xb);
713 write_phy(mac, 0x26e, 16, 0x2);
714 mdelay(1);
715 read_phy(mac, 0x26e, 19, &ipd);
716 write_phy(mac, 0, 30, 0);
717 ipd = (ipd >> 4) & 0xf;
718
719 i = 0;
720 while (rtl8218B_6276B_rtl8380_perport[i * 2]) {
721 write_phy(mac, 0xfff, rtl8218B_6276B_rtl8380_perport[i * 2],
722 rtl8218B_6276B_rtl8380_perport[i * 2 + 1]);
723 i++;
724 }
725
726 /*Disable broadcast ID*/
727 write_phy(mac, 0xfff, 0x1f, 0x0000);
728 write_phy(mac, 0xfff, 0x1d, 0x0008);
729 write_phy(mac, 0xfff, 0x1f, 0x0266);
730 write_phy(mac, 0xfff, 0x16, 0x00 + mac);
731 write_phy(mac, 0xfff, 0x1f, 0x0000);
732 write_phy(mac, 0xfff, 0x1d, 0x0000);
733 mdelay(1);
734
735 return 0;
736 }
737
738 static int rtl8218b_ext_match_phy_device(struct phy_device *phydev)
739 {
740 int addr = phydev->mdio.addr;
741
742 /* Both the RTL8214FC and the external RTL8218B have the same
743 * PHY ID. On the RTL838x, the RTL8218B can only be attached_dev
744 * at PHY IDs 0-7, while the RTL8214FC must be attached via
745 * the pair of SGMII/1000Base-X with higher PHY-IDs
746 */
747 if (soc_info.family == RTL8380_FAMILY_ID)
748 return phydev->phy_id == PHY_ID_RTL8218B_E && addr < 8;
749 else
750 return phydev->phy_id == PHY_ID_RTL8218B_E;
751 }
752
753 /*
754 * Read an mmd register of the PHY
755 */
756 static int rtl83xx_read_mmd_phy(u32 port, u32 addr, u32 reg, u32 *val)
757 {
758 u32 v;
759
760 mutex_lock(&smi_lock);
761
762 if (rtl838x_smi_wait_op(10000))
763 goto timeout;
764
765 sw_w32(1 << port, RTL838X_SMI_ACCESS_PHY_CTRL_0);
766 mdelay(10);
767
768 sw_w32_mask(0xffff0000, port << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2);
769
770 v = addr << 16 | reg;
771 sw_w32(v, RTL838X_SMI_ACCESS_PHY_CTRL_3);
772
773 /* mmd-access | read | cmd-start */
774 v = 1 << 1 | 0 << 2 | 1;
775 sw_w32(v, RTL838X_SMI_ACCESS_PHY_CTRL_1);
776
777 if (rtl838x_smi_wait_op(10000))
778 goto timeout;
779
780 *val = sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_2) & 0xffff;
781
782 mutex_unlock(&smi_lock);
783 return 0;
784
785 timeout:
786 mutex_unlock(&smi_lock);
787 return -ETIMEDOUT;
788 }
789
790 /*
791 * Write to an mmd register of the PHY
792 */
793 static int rtl838x_write_mmd_phy(u32 port, u32 addr, u32 reg, u32 val)
794 {
795 u32 v;
796
797 pr_debug("MMD write: port %d, dev %d, reg %d, val %x\n", port, addr, reg, val);
798 val &= 0xffff;
799 mutex_lock(&smi_lock);
800
801 if (rtl838x_smi_wait_op(10000))
802 goto timeout;
803
804 sw_w32(1 << port, RTL838X_SMI_ACCESS_PHY_CTRL_0);
805 mdelay(10);
806
807 sw_w32_mask(0xffff0000, val << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2);
808
809 sw_w32_mask(0x1f << 16, addr << 16, RTL838X_SMI_ACCESS_PHY_CTRL_3);
810 sw_w32_mask(0xffff, reg, RTL838X_SMI_ACCESS_PHY_CTRL_3);
811 /* mmd-access | write | cmd-start */
812 v = 1 << 1 | 1 << 2 | 1;
813 sw_w32(v, RTL838X_SMI_ACCESS_PHY_CTRL_1);
814
815 if (rtl838x_smi_wait_op(10000))
816 goto timeout;
817
818 mutex_unlock(&smi_lock);
819 return 0;
820
821 timeout:
822 mutex_unlock(&smi_lock);
823 return -ETIMEDOUT;
824 }
825
826 static int rtl8218b_read_mmd(struct phy_device *phydev,
827 int devnum, u16 regnum)
828 {
829 int ret;
830 u32 val;
831 int addr = phydev->mdio.addr;
832
833 ret = rtl83xx_read_mmd_phy(addr, devnum, regnum, &val);
834 if (ret)
835 return ret;
836 return val;
837 }
838
839 static int rtl8218b_write_mmd(struct phy_device *phydev,
840 int devnum, u16 regnum, u16 val)
841 {
842 int addr = phydev->mdio.addr;
843
844 return rtl838x_write_mmd_phy(addr, devnum, regnum, val);
845 }
846
847 static int rtl8226_read_mmd(struct phy_device *phydev, int devnum, u16 regnum)
848 {
849 int port = phydev->mdio.addr; // the SoC translates port addresses to PHY addr
850 int err;
851 u32 val;
852
853 err = rtl930x_read_mmd_phy(port, devnum, regnum, &val);
854
855 if (err)
856 return err;
857 return val;
858 }
859
860 static int rtl8226_write_mmd(struct phy_device *phydev, int devnum, u16 regnum, u16 val)
861 {
862 int port = phydev->mdio.addr; // the SoC translates port addresses to PHY addr
863
864 return rtl930x_write_mmd_phy(port, devnum, regnum, val);
865 }
866
867 static void rtl8380_rtl8214fc_media_set(int mac, bool set_fibre)
868 {
869 int base = mac - (mac % 4);
870 static int reg[] = {16, 19, 20, 21};
871 int val, media, power;
872
873 pr_info("%s: port %d, set_fibre: %d\n", __func__, mac, set_fibre);
874 write_phy(base, 0xfff, 29, 8);
875 read_phy(base, 0x266, reg[mac % 4], &val);
876
877 media = (val >> 10) & 0x3;
878 pr_info("Current media %x\n", media);
879 if (media & 0x2) {
880 pr_info("Powering off COPPER\n");
881 write_phy(base, 0xfff, 29, 1);
882 /* Ensure power is off */
883 read_phy(base, 0xa40, 16, &power);
884 if (!(power & (1 << 11)))
885 write_phy(base, 0xa40, 16, power | (1 << 11));
886 } else {
887 pr_info("Powering off FIBRE");
888 write_phy(base, 0xfff, 29, 3);
889 /* Ensure power is off */
890 read_phy(base, 0xa40, 16, &power);
891 if (!(power & (1 << 11)))
892 write_phy(base, 0xa40, 16, power | (1 << 11));
893 }
894
895 if (set_fibre) {
896 val |= 1 << 10;
897 val &= ~(1 << 11);
898 } else {
899 val |= 1 << 10;
900 val |= 1 << 11;
901 }
902 write_phy(base, 0xfff, 29, 8);
903 write_phy(base, 0x266, reg[mac % 4], val);
904 write_phy(base, 0xfff, 29, 0);
905
906 if (set_fibre) {
907 pr_info("Powering on FIBRE");
908 write_phy(base, 0xfff, 29, 3);
909 /* Ensure power is off */
910 read_phy(base, 0xa40, 16, &power);
911 if (power & (1 << 11))
912 write_phy(base, 0xa40, 16, power & ~(1 << 11));
913 } else {
914 pr_info("Powering on COPPER\n");
915 write_phy(base, 0xfff, 29, 1);
916 /* Ensure power is off */
917 read_phy(base, 0xa40, 16, &power);
918 if (power & (1 << 11))
919 write_phy(base, 0xa40, 16, power & ~(1 << 11));
920 }
921
922 write_phy(base, 0xfff, 29, 0);
923 }
924
925 static bool rtl8380_rtl8214fc_media_is_fibre(int mac)
926 {
927 int base = mac - (mac % 4);
928 static int reg[] = {16, 19, 20, 21};
929 u32 val;
930
931 write_phy(base, 0xfff, 29, 8);
932 read_phy(base, 0x266, reg[mac % 4], &val);
933 write_phy(base, 0xfff, 29, 0);
934 if (val & (1 << 11))
935 return false;
936 return true;
937 }
938
939 static int rtl8214fc_set_port(struct phy_device *phydev, int port)
940 {
941 bool is_fibre = (port == PORT_FIBRE ? true : false);
942 int addr = phydev->mdio.addr;
943
944 pr_debug("%s port %d to %d\n", __func__, addr, port);
945
946 rtl8380_rtl8214fc_media_set(addr, is_fibre);
947 return 0;
948 }
949
950 static int rtl8214fc_get_port(struct phy_device *phydev)
951 {
952 int addr = phydev->mdio.addr;
953
954 pr_debug("%s: port %d\n", __func__, addr);
955 if (rtl8380_rtl8214fc_media_is_fibre(addr))
956 return PORT_FIBRE;
957 return PORT_MII;
958 }
959
960 static void rtl8218b_eee_set_u_boot(int port, bool enable)
961 {
962 u32 val;
963 bool an_enabled;
964
965 /* Set GPHY page to copper */
966 write_phy(port, 0, 30, 0x0001);
967 read_phy(port, 0, 0, &val);
968 an_enabled = val & (1 << 12);
969
970 if (enable) {
971 /* 100/1000M EEE Capability */
972 write_phy(port, 0, 13, 0x0007);
973 write_phy(port, 0, 14, 0x003C);
974 write_phy(port, 0, 13, 0x4007);
975 write_phy(port, 0, 14, 0x0006);
976
977 read_phy(port, 0x0A43, 25, &val);
978 val |= 1 << 4;
979 write_phy(port, 0x0A43, 25, val);
980 } else {
981 /* 100/1000M EEE Capability */
982 write_phy(port, 0, 13, 0x0007);
983 write_phy(port, 0, 14, 0x003C);
984 write_phy(port, 0, 13, 0x0007);
985 write_phy(port, 0, 14, 0x0000);
986
987 read_phy(port, 0x0A43, 25, &val);
988 val &= ~(1 << 4);
989 write_phy(port, 0x0A43, 25, val);
990 }
991
992 /* Restart AN if enabled */
993 if (an_enabled) {
994 read_phy(port, 0, 0, &val);
995 val |= (1 << 12) | (1 << 9);
996 write_phy(port, 0, 0, val);
997 }
998
999 /* GPHY page back to auto*/
1000 write_phy(port, 0xa42, 29, 0);
1001 }
1002
1003 // TODO: unused
1004 void rtl8380_rtl8218b_eee_set(int port, bool enable)
1005 {
1006 u32 val;
1007 bool an_enabled;
1008
1009 pr_debug("In %s %d, enable %d\n", __func__, port, enable);
1010 /* Set GPHY page to copper */
1011 write_phy(port, 0xa42, 29, 0x0001);
1012
1013 read_phy(port, 0, 0, &val);
1014 an_enabled = val & (1 << 12);
1015
1016 /* MAC based EEE */
1017 read_phy(port, 0xa43, 25, &val);
1018 val &= ~(1 << 5);
1019 write_phy(port, 0xa43, 25, val);
1020
1021 /* 100M / 1000M EEE */
1022 if (enable)
1023 rtl838x_write_mmd_phy(port, 7, 60, 0x6);
1024 else
1025 rtl838x_write_mmd_phy(port, 7, 60, 0);
1026
1027 /* 500M EEE ability */
1028 read_phy(port, 0xa42, 20, &val);
1029 if (enable)
1030 val |= 1 << 7;
1031 else
1032 val &= ~(1 << 7);
1033 write_phy(port, 0xa42, 20, val);
1034
1035 /* Restart AN if enabled */
1036 if (an_enabled) {
1037 read_phy(port, 0, 0, &val);
1038 val |= (1 << 12) | (1 << 9);
1039 write_phy(port, 0, 0, val);
1040 }
1041
1042 /* GPHY page back to auto*/
1043 write_phy(port, 0xa42, 29, 0);
1044 }
1045
1046 static int rtl8218b_get_eee(struct phy_device *phydev,
1047 struct ethtool_eee *e)
1048 {
1049 u32 val;
1050 int addr = phydev->mdio.addr;
1051
1052 pr_debug("In %s, port %d\n", __func__, addr);
1053
1054 /* Set GPHY page to copper */
1055 write_phy(addr, 0xa42, 29, 0x0001);
1056
1057 rtl83xx_read_mmd_phy(addr, 7, 60, &val);
1058 if (e->eee_enabled && (!!(val & (1 << 7))))
1059 e->eee_enabled = !!(val & (1 << 7));
1060 else
1061 e->eee_enabled = 0;
1062
1063 /* GPHY page to auto */
1064 write_phy(addr, 0xa42, 29, 0x0000);
1065
1066 return 0;
1067 }
1068
1069 // TODO: unused
1070 void rtl8380_rtl8218b_green_set(int mac, bool enable)
1071 {
1072 u32 val;
1073
1074 /* Set GPHY page to copper */
1075 write_phy(mac, 0xa42, 29, 0x0001);
1076
1077 write_phy(mac, 0, 27, 0x8011);
1078 read_phy(mac, 0, 28, &val);
1079 if (enable) {
1080 val |= 1 << 9;
1081 write_phy(mac, 0, 27, 0x8011);
1082 write_phy(mac, 0, 28, val);
1083 } else {
1084 val &= ~(1 << 9);
1085 write_phy(mac, 0, 27, 0x8011);
1086 write_phy(mac, 0, 28, val);
1087 }
1088
1089 /* GPHY page to auto */
1090 write_phy(mac, 0xa42, 29, 0x0000);
1091 }
1092
1093 // TODO: unused
1094 int rtl8380_rtl8214fc_get_green(struct phy_device *phydev, struct ethtool_eee *e)
1095 {
1096 u32 val;
1097 int addr = phydev->mdio.addr;
1098
1099 pr_debug("In %s %d\n", __func__, addr);
1100 /* Set GPHY page to copper */
1101 write_phy(addr, 0xa42, 29, 0x0001);
1102
1103 write_phy(addr, 0, 27, 0x8011);
1104 read_phy(addr, 0, 28, &val);
1105 if (e->eee_enabled && (!!(val & (1 << 9))))
1106 e->eee_enabled = !!(val & (1 << 9));
1107 else
1108 e->eee_enabled = 0;
1109
1110 /* GPHY page to auto */
1111 write_phy(addr, 0xa42, 29, 0x0000);
1112
1113 return 0;
1114 }
1115
1116 static int rtl8214fc_set_eee(struct phy_device *phydev,
1117 struct ethtool_eee *e)
1118 {
1119 u32 pollMask;
1120 int addr = phydev->mdio.addr;
1121
1122 pr_debug("In %s port %d, enabled %d\n", __func__, addr, e->eee_enabled);
1123
1124 if (rtl8380_rtl8214fc_media_is_fibre(addr)) {
1125 netdev_err(phydev->attached_dev, "Port %d configured for FIBRE", addr);
1126 return -ENOTSUPP;
1127 }
1128
1129 pollMask = sw_r32(RTL838X_SMI_POLL_CTRL);
1130 sw_w32(0, RTL838X_SMI_POLL_CTRL);
1131 rtl8218b_eee_set_u_boot(addr, (bool) e->eee_enabled);
1132 sw_w32(pollMask, RTL838X_SMI_POLL_CTRL);
1133 return 0;
1134 }
1135
1136 static int rtl8214fc_get_eee(struct phy_device *phydev,
1137 struct ethtool_eee *e)
1138 {
1139 int addr = phydev->mdio.addr;
1140
1141 pr_debug("In %s port %d, enabled %d\n", __func__, addr, e->eee_enabled);
1142 if (rtl8380_rtl8214fc_media_is_fibre(addr)) {
1143 netdev_err(phydev->attached_dev, "Port %d configured for FIBRE", addr);
1144 return -ENOTSUPP;
1145 }
1146
1147 return rtl8218b_get_eee(phydev, e);
1148 }
1149
1150 static int rtl8218b_set_eee(struct phy_device *phydev,
1151 struct ethtool_eee *e)
1152 {
1153 u32 pollMask;
1154 int addr = phydev->mdio.addr;
1155
1156 pr_debug("In %s, port %d, enabled %d\n", __func__, addr, e->eee_enabled);
1157
1158 pollMask = sw_r32(RTL838X_SMI_POLL_CTRL);
1159 sw_w32(0, RTL838X_SMI_POLL_CTRL);
1160 rtl8218b_eee_set_u_boot(addr, (bool) e->eee_enabled);
1161 sw_w32(pollMask, RTL838X_SMI_POLL_CTRL);
1162
1163 return 0;
1164 }
1165
1166 static int rtl8214c_match_phy_device(struct phy_device *phydev)
1167 {
1168 return phydev->phy_id == PHY_ID_RTL8214C;
1169 }
1170
1171 static int rtl8380_configure_rtl8214c(struct phy_device *phydev)
1172 {
1173 u32 phy_id, val;
1174 int mac = phydev->mdio.addr;
1175
1176 read_phy(mac, 0, 2, &val);
1177 phy_id = val << 16;
1178 read_phy(mac, 0, 3, &val);
1179 phy_id |= val;
1180 pr_debug("Phy on MAC %d: %x\n", mac, phy_id);
1181
1182 phydev_info(phydev, "Detected external RTL8214C\n");
1183
1184 /* GPHY auto conf */
1185 write_phy(mac, 0xa42, 29, 0);
1186 return 0;
1187 }
1188
1189 static int rtl8380_configure_rtl8214fc(struct phy_device *phydev)
1190 {
1191 u32 phy_id, val, page = 0;
1192 int i, l;
1193 int mac = phydev->mdio.addr;
1194 struct fw_header *h;
1195 u32 *rtl8380_rtl8214fc_perchip;
1196 u32 *rtl8380_rtl8214fc_perport;
1197
1198 read_phy(mac, 0, 2, &val);
1199 phy_id = val << 16;
1200 read_phy(mac, 0, 3, &val);
1201 phy_id |= val;
1202 pr_debug("Phy on MAC %d: %x\n", mac, phy_id);
1203
1204 /* Read internal PHY id */
1205 write_phy(mac, 0, 30, 0x0001);
1206 write_phy(mac, 0, 31, 0x0a42);
1207 write_phy(mac, 31, 27, 0x0002);
1208 read_phy(mac, 31, 28, &val);
1209 if (val != 0x6276) {
1210 phydev_err(phydev, "Expected external RTL8214FC, found PHY-ID %x\n", val);
1211 return -1;
1212 }
1213 phydev_info(phydev, "Detected external RTL8214FC\n");
1214
1215 h = rtl838x_request_fw(phydev, &rtl838x_8214fc_fw, FIRMWARE_838X_8214FC_1);
1216 if (!h)
1217 return -1;
1218
1219 if (h->phy != 0x8214fc00) {
1220 phydev_err(phydev, "Wrong firmware file: PHY mismatch.\n");
1221 return -1;
1222 }
1223
1224 rtl8380_rtl8214fc_perchip = (void *)h + sizeof(struct fw_header)
1225 + h->parts[0].start;
1226
1227 rtl8380_rtl8214fc_perport = (void *)h + sizeof(struct fw_header)
1228 + h->parts[1].start;
1229
1230 /* detect phy version */
1231 write_phy(mac, 0xfff, 27, 0x0004);
1232 read_phy(mac, 0xfff, 28, &val);
1233
1234 read_phy(mac, 0, 16, &val);
1235 if (val & (1 << 11))
1236 rtl8380_rtl8214fc_on_off(mac, true);
1237 else
1238 rtl8380_phy_reset(mac);
1239
1240 msleep(100);
1241 write_phy(mac, 0, 30, 0x0001);
1242
1243 i = 0;
1244 while (rtl8380_rtl8214fc_perchip[i * 3]
1245 && rtl8380_rtl8214fc_perchip[i * 3 + 1]) {
1246 if (rtl8380_rtl8214fc_perchip[i * 3 + 1] == 0x1f)
1247 page = rtl8380_rtl8214fc_perchip[i * 3 + 2];
1248 if (rtl8380_rtl8214fc_perchip[i * 3 + 1] == 0x13 && page == 0x260) {
1249 read_phy(mac + rtl8380_rtl8214fc_perchip[i * 3], 0x260, 13, &val);
1250 val = (val & 0x1f00) | (rtl8380_rtl8214fc_perchip[i * 3 + 2]
1251 & 0xe0ff);
1252 write_phy(mac + rtl8380_rtl8214fc_perchip[i * 3],
1253 0xfff, rtl8380_rtl8214fc_perchip[i * 3 + 1], val);
1254 } else {
1255 write_phy(mac + rtl8380_rtl8214fc_perchip[i * 3],
1256 0xfff, rtl8380_rtl8214fc_perchip[i * 3 + 1],
1257 rtl8380_rtl8214fc_perchip[i * 3 + 2]);
1258 }
1259 i++;
1260 }
1261
1262 /* Force copper medium */
1263 for (i = 0; i < 4; i++) {
1264 write_phy(mac + i, 0xfff, 0x1f, 0x0000);
1265 write_phy(mac + i, 0xfff, 0x1e, 0x0001);
1266 }
1267
1268 /* Enable PHY */
1269 for (i = 0; i < 4; i++) {
1270 write_phy(mac + i, 0xfff, 0x1f, 0x0000);
1271 write_phy(mac + i, 0xfff, 0x00, 0x1140);
1272 }
1273 mdelay(100);
1274
1275 /* Disable Autosensing */
1276 for (i = 0; i < 4; i++) {
1277 for (l = 0; l < 100; l++) {
1278 read_phy(mac + i, 0x0a42, 0x10, &val);
1279 if ((val & 0x7) >= 3)
1280 break;
1281 }
1282 if (l >= 100) {
1283 phydev_err(phydev, "Could not disable autosensing\n");
1284 return -1;
1285 }
1286 }
1287
1288 /* Request patch */
1289 for (i = 0; i < 4; i++) {
1290 write_phy(mac + i, 0xfff, 0x1f, 0x0b82);
1291 write_phy(mac + i, 0xfff, 0x10, 0x0010);
1292 }
1293 mdelay(300);
1294
1295 /* Verify patch readiness */
1296 for (i = 0; i < 4; i++) {
1297 for (l = 0; l < 100; l++) {
1298 read_phy(mac + i, 0xb80, 0x10, &val);
1299 if (val & 0x40)
1300 break;
1301 }
1302 if (l >= 100) {
1303 phydev_err(phydev, "Could not patch PHY\n");
1304 return -1;
1305 }
1306 }
1307
1308 /* Use Broadcast ID method for patching */
1309 write_phy(mac, 0xfff, 0x1f, 0x0000);
1310 write_phy(mac, 0xfff, 0x1d, 0x0008);
1311 write_phy(mac, 0xfff, 0x1f, 0x0266);
1312 write_phy(mac, 0xfff, 0x16, 0xff00 + mac);
1313 write_phy(mac, 0xfff, 0x1f, 0x0000);
1314 write_phy(mac, 0xfff, 0x1d, 0x0000);
1315 mdelay(1);
1316
1317 i = 0;
1318 while (rtl8380_rtl8214fc_perport[i * 2]) {
1319 write_phy(mac, 0xfff, rtl8380_rtl8214fc_perport[i * 2],
1320 rtl8380_rtl8214fc_perport[i * 2 + 1]);
1321 i++;
1322 }
1323
1324 /*Disable broadcast ID*/
1325 write_phy(mac, 0xfff, 0x1f, 0x0000);
1326 write_phy(mac, 0xfff, 0x1d, 0x0008);
1327 write_phy(mac, 0xfff, 0x1f, 0x0266);
1328 write_phy(mac, 0xfff, 0x16, 0x00 + mac);
1329 write_phy(mac, 0xfff, 0x1f, 0x0000);
1330 write_phy(mac, 0xfff, 0x1d, 0x0000);
1331 mdelay(1);
1332
1333 /* Auto medium selection */
1334 for (i = 0; i < 4; i++) {
1335 write_phy(mac + i, 0xfff, 0x1f, 0x0000);
1336 write_phy(mac + i, 0xfff, 0x1e, 0x0000);
1337 }
1338
1339 return 0;
1340 }
1341
1342 static int rtl8214fc_match_phy_device(struct phy_device *phydev)
1343 {
1344 int addr = phydev->mdio.addr;
1345
1346 return phydev->phy_id == PHY_ID_RTL8214FC && addr >= 24;
1347 }
1348
1349 static int rtl8380_configure_serdes(struct phy_device *phydev)
1350 {
1351 u32 v;
1352 u32 sds_conf_value;
1353 int i;
1354 struct fw_header *h;
1355 u32 *rtl8380_sds_take_reset;
1356 u32 *rtl8380_sds_common;
1357 u32 *rtl8380_sds01_qsgmii_6275b;
1358 u32 *rtl8380_sds23_qsgmii_6275b;
1359 u32 *rtl8380_sds4_fiber_6275b;
1360 u32 *rtl8380_sds5_fiber_6275b;
1361 u32 *rtl8380_sds_reset;
1362 u32 *rtl8380_sds_release_reset;
1363
1364 phydev_info(phydev, "Detected internal RTL8380 SERDES\n");
1365
1366 h = rtl838x_request_fw(phydev, &rtl838x_8218b_fw, FIRMWARE_838X_8380_1);
1367 if (!h)
1368 return -1;
1369
1370 if (h->magic != 0x83808380) {
1371 phydev_err(phydev, "Wrong firmware file: magic number mismatch.\n");
1372 return -1;
1373 }
1374
1375 rtl8380_sds_take_reset = (void *)h + sizeof(struct fw_header)
1376 + h->parts[0].start;
1377
1378 rtl8380_sds_common = (void *)h + sizeof(struct fw_header)
1379 + h->parts[1].start;
1380
1381 rtl8380_sds01_qsgmii_6275b = (void *)h + sizeof(struct fw_header)
1382 + h->parts[2].start;
1383
1384 rtl8380_sds23_qsgmii_6275b = (void *)h + sizeof(struct fw_header)
1385 + h->parts[3].start;
1386
1387 rtl8380_sds4_fiber_6275b = (void *)h + sizeof(struct fw_header)
1388 + h->parts[4].start;
1389
1390 rtl8380_sds5_fiber_6275b = (void *)h + sizeof(struct fw_header)
1391 + h->parts[5].start;
1392
1393 rtl8380_sds_reset = (void *)h + sizeof(struct fw_header)
1394 + h->parts[6].start;
1395
1396 rtl8380_sds_release_reset = (void *)h + sizeof(struct fw_header)
1397 + h->parts[7].start;
1398
1399 /* Back up serdes power off value */
1400 sds_conf_value = sw_r32(RTL838X_SDS_CFG_REG);
1401 pr_info("SDS power down value: %x\n", sds_conf_value);
1402
1403 /* take serdes into reset */
1404 i = 0;
1405 while (rtl8380_sds_take_reset[2 * i]) {
1406 sw_w32(rtl8380_sds_take_reset[2 * i + 1], rtl8380_sds_take_reset[2 * i]);
1407 i++;
1408 udelay(1000);
1409 }
1410
1411 /* apply common serdes patch */
1412 i = 0;
1413 while (rtl8380_sds_common[2 * i]) {
1414 sw_w32(rtl8380_sds_common[2 * i + 1], rtl8380_sds_common[2 * i]);
1415 i++;
1416 udelay(1000);
1417 }
1418
1419 /* internal R/W enable */
1420 sw_w32(3, RTL838X_INT_RW_CTRL);
1421
1422 /* SerDes ports 4 and 5 are FIBRE ports */
1423 sw_w32_mask(0x7 | 0x38, 1 | (1 << 3), RTL838X_INT_MODE_CTRL);
1424
1425 /* SerDes module settings, SerDes 0-3 are QSGMII */
1426 v = 0x6 << 25 | 0x6 << 20 | 0x6 << 15 | 0x6 << 10;
1427 /* SerDes 4 and 5 are 1000BX FIBRE */
1428 v |= 0x4 << 5 | 0x4;
1429 sw_w32(v, RTL838X_SDS_MODE_SEL);
1430
1431 pr_info("PLL control register: %x\n", sw_r32(RTL838X_PLL_CML_CTRL));
1432 sw_w32_mask(0xfffffff0, 0xaaaaaaaf & 0xf, RTL838X_PLL_CML_CTRL);
1433 i = 0;
1434 while (rtl8380_sds01_qsgmii_6275b[2 * i]) {
1435 sw_w32(rtl8380_sds01_qsgmii_6275b[2 * i + 1],
1436 rtl8380_sds01_qsgmii_6275b[2 * i]);
1437 i++;
1438 }
1439
1440 i = 0;
1441 while (rtl8380_sds23_qsgmii_6275b[2 * i]) {
1442 sw_w32(rtl8380_sds23_qsgmii_6275b[2 * i + 1], rtl8380_sds23_qsgmii_6275b[2 * i]);
1443 i++;
1444 }
1445
1446 i = 0;
1447 while (rtl8380_sds4_fiber_6275b[2 * i]) {
1448 sw_w32(rtl8380_sds4_fiber_6275b[2 * i + 1], rtl8380_sds4_fiber_6275b[2 * i]);
1449 i++;
1450 }
1451
1452 i = 0;
1453 while (rtl8380_sds5_fiber_6275b[2 * i]) {
1454 sw_w32(rtl8380_sds5_fiber_6275b[2 * i + 1], rtl8380_sds5_fiber_6275b[2 * i]);
1455 i++;
1456 }
1457
1458 i = 0;
1459 while (rtl8380_sds_reset[2 * i]) {
1460 sw_w32(rtl8380_sds_reset[2 * i + 1], rtl8380_sds_reset[2 * i]);
1461 i++;
1462 }
1463
1464 i = 0;
1465 while (rtl8380_sds_release_reset[2 * i]) {
1466 sw_w32(rtl8380_sds_release_reset[2 * i + 1], rtl8380_sds_release_reset[2 * i]);
1467 i++;
1468 }
1469
1470 pr_info("SDS power down value now: %x\n", sw_r32(RTL838X_SDS_CFG_REG));
1471 sw_w32(sds_conf_value, RTL838X_SDS_CFG_REG);
1472
1473 pr_info("Configuration of SERDES done\n");
1474 return 0;
1475 }
1476
1477 static int rtl8390_configure_serdes(struct phy_device *phydev)
1478 {
1479 phydev_info(phydev, "Detected internal RTL8390 SERDES\n");
1480
1481 /* In autoneg state, force link, set SR4_CFG_EN_LINK_FIB1G */
1482 sw_w32_mask(0, 1 << 18, RTL839X_SDS12_13_XSG0 + 0x0a);
1483
1484 /* Disable EEE: Clear FRE16_EEE_RSG_FIB1G, FRE16_EEE_STD_FIB1G,
1485 * FRE16_C1_PWRSAV_EN_FIB1G, FRE16_C2_PWRSAV_EN_FIB1G
1486 * and FRE16_EEE_QUIET_FIB1G
1487 */
1488 sw_w32_mask(0x1f << 10, 0, RTL839X_SDS12_13_XSG0 + 0xe0);
1489
1490 return 0;
1491 }
1492
1493 int rtl9300_configure_serdes(struct phy_device *phydev)
1494 {
1495 struct device *dev = &phydev->mdio.dev;
1496 int phy_addr = phydev->mdio.addr;
1497 int sds_num = 0;
1498 int v;
1499
1500 phydev_info(phydev, "Configuring internal RTL9300 SERDES\n");
1501
1502 switch (phy_addr) {
1503 case 26:
1504 sds_num = 8;
1505 break;
1506 case 27:
1507 sds_num = 9;
1508 break;
1509 default:
1510 dev_err(dev, "Not a SerDes PHY\n");
1511 return -EINVAL;
1512 }
1513
1514 /* Set default Medium to fibre */
1515 v = rtl930x_read_sds_phy(sds_num, 0x1f, 11);
1516 if (v < 0) {
1517 dev_err(dev, "Cannot access SerDes PHY %d\n", phy_addr);
1518 return -EINVAL;
1519 }
1520 v |= BIT(2);
1521 rtl930x_write_sds_phy(sds_num, 0x1f, 11, v);
1522
1523 // TODO: this needs to be configurable via ethtool/.dts
1524 pr_info("Setting 10G/1000BX auto fibre medium\n");
1525 rtl9300_sds_rst(sds_num, 0x1b);
1526
1527 // TODO: Apply patch set for fibre type
1528
1529 return 0;
1530 }
1531
1532 static int rtl8214fc_phy_probe(struct phy_device *phydev)
1533 {
1534 struct device *dev = &phydev->mdio.dev;
1535 struct rtl838x_phy_priv *priv;
1536 int addr = phydev->mdio.addr;
1537
1538 /* 839x has internal SerDes */
1539 if (soc_info.id == 0x8393)
1540 return -ENODEV;
1541
1542 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1543 if (!priv)
1544 return -ENOMEM;
1545
1546 priv->name = "RTL8214FC";
1547
1548 /* All base addresses of the PHYs start at multiples of 8 */
1549 if (!(addr % 8)) {
1550 /* Configuration must be done whil patching still possible */
1551 return rtl8380_configure_rtl8214fc(phydev);
1552 }
1553 return 0;
1554 }
1555
1556 static int rtl8214c_phy_probe(struct phy_device *phydev)
1557 {
1558 struct device *dev = &phydev->mdio.dev;
1559 struct rtl838x_phy_priv *priv;
1560 int addr = phydev->mdio.addr;
1561
1562 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1563 if (!priv)
1564 return -ENOMEM;
1565
1566 priv->name = "RTL8214C";
1567
1568 /* All base addresses of the PHYs start at multiples of 8 */
1569 if (!(addr % 8)) {
1570 /* Configuration must be done whil patching still possible */
1571 return rtl8380_configure_rtl8214c(phydev);
1572 }
1573 return 0;
1574 }
1575
1576 static int rtl8218b_ext_phy_probe(struct phy_device *phydev)
1577 {
1578 struct device *dev = &phydev->mdio.dev;
1579 struct rtl838x_phy_priv *priv;
1580 int addr = phydev->mdio.addr;
1581
1582 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1583 if (!priv)
1584 return -ENOMEM;
1585
1586 priv->name = "RTL8218B (external)";
1587
1588 /* All base addresses of the PHYs start at multiples of 8 */
1589 if (!(addr % 8) && soc_info.family == RTL8380_FAMILY_ID) {
1590 /* Configuration must be done while patching still possible */
1591 return rtl8380_configure_ext_rtl8218b(phydev);
1592 }
1593 return 0;
1594 }
1595
1596 static int rtl8218b_int_phy_probe(struct phy_device *phydev)
1597 {
1598 struct device *dev = &phydev->mdio.dev;
1599 struct rtl838x_phy_priv *priv;
1600 int addr = phydev->mdio.addr;
1601
1602 if (soc_info.family != RTL8380_FAMILY_ID)
1603 return -ENODEV;
1604 if (addr >= 24)
1605 return -ENODEV;
1606
1607 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1608 if (!priv)
1609 return -ENOMEM;
1610
1611 priv->name = "RTL8218B (internal)";
1612
1613 /* All base addresses of the PHYs start at multiples of 8 */
1614 if (!(addr % 8)) {
1615 /* Configuration must be done while patching still possible */
1616 return rtl8380_configure_int_rtl8218b(phydev);
1617 }
1618 return 0;
1619 }
1620
1621 static int rtl8218d_phy_probe(struct phy_device *phydev)
1622 {
1623 struct device *dev = &phydev->mdio.dev;
1624 struct rtl838x_phy_priv *priv;
1625 int addr = phydev->mdio.addr;
1626
1627 pr_info("%s: id: %d\n", __func__, addr);
1628 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1629 if (!priv)
1630 return -ENOMEM;
1631
1632 priv->name = "RTL8218D";
1633
1634 /* All base addresses of the PHYs start at multiples of 8 */
1635 if (!(addr % 8)) {
1636 /* Configuration must be done while patching still possible */
1637 // TODO: return configure_rtl8218d(phydev);
1638 }
1639 return 0;
1640 }
1641
1642 static int rtl8226_phy_probe(struct phy_device *phydev)
1643 {
1644 struct device *dev = &phydev->mdio.dev;
1645 struct rtl838x_phy_priv *priv;
1646 int addr = phydev->mdio.addr;
1647
1648 pr_info("%s: id: %d\n", __func__, addr);
1649 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1650 if (!priv)
1651 return -ENOMEM;
1652
1653 priv->name = "RTL8226";
1654
1655 return 0;
1656 }
1657
1658 static int rtl838x_serdes_probe(struct phy_device *phydev)
1659 {
1660 struct device *dev = &phydev->mdio.dev;
1661 struct rtl838x_phy_priv *priv;
1662 int addr = phydev->mdio.addr;
1663
1664 if (soc_info.family != RTL8380_FAMILY_ID)
1665 return -ENODEV;
1666 if (addr < 24)
1667 return -ENODEV;
1668
1669 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1670 if (!priv)
1671 return -ENOMEM;
1672
1673 priv->name = "RTL8380 Serdes";
1674
1675 /* On the RTL8380M, PHYs 24-27 connect to the internal SerDes */
1676 if (soc_info.id == 0x8380) {
1677 if (addr == 24)
1678 return rtl8380_configure_serdes(phydev);
1679 return 0;
1680 }
1681 return -ENODEV;
1682 }
1683
1684 static int rtl8393_serdes_probe(struct phy_device *phydev)
1685 {
1686 struct device *dev = &phydev->mdio.dev;
1687 struct rtl838x_phy_priv *priv;
1688 int addr = phydev->mdio.addr;
1689
1690 pr_info("%s: id: %d\n", __func__, addr);
1691 if (soc_info.family != RTL8390_FAMILY_ID)
1692 return -ENODEV;
1693
1694 if (addr < 24)
1695 return -ENODEV;
1696
1697 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1698 if (!priv)
1699 return -ENOMEM;
1700
1701 priv->name = "RTL8393 Serdes";
1702 return rtl8390_configure_serdes(phydev);
1703 }
1704
1705 static int rtl8390_serdes_probe(struct phy_device *phydev)
1706 {
1707 struct device *dev = &phydev->mdio.dev;
1708 struct rtl838x_phy_priv *priv;
1709 int addr = phydev->mdio.addr;
1710
1711 if (soc_info.family != RTL8390_FAMILY_ID)
1712 return -ENODEV;
1713
1714 if (addr < 24)
1715 return -ENODEV;
1716
1717 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1718 if (!priv)
1719 return -ENOMEM;
1720
1721 priv->name = "RTL8390 Serdes";
1722 return rtl8390_configure_generic(phydev);
1723 }
1724
1725 static int rtl9300_serdes_probe(struct phy_device *phydev)
1726 {
1727 struct device *dev = &phydev->mdio.dev;
1728 struct rtl838x_phy_priv *priv;
1729 int addr = phydev->mdio.addr;
1730
1731 if (soc_info.family != RTL9300_FAMILY_ID)
1732 return -ENODEV;
1733
1734 if (addr < 24)
1735 return -ENODEV;
1736
1737 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1738 if (!priv)
1739 return -ENOMEM;
1740
1741 priv->name = "RTL9300 Serdes";
1742 return rtl9300_configure_serdes(phydev);
1743 }
1744
1745 static struct phy_driver rtl83xx_phy_driver[] = {
1746 {
1747 PHY_ID_MATCH_MODEL(PHY_ID_RTL8214C),
1748 .name = "Realtek RTL8214C",
1749 .features = PHY_GBIT_FEATURES,
1750 .match_phy_device = rtl8214c_match_phy_device,
1751 .probe = rtl8214c_phy_probe,
1752 .suspend = genphy_suspend,
1753 .resume = genphy_resume,
1754 .set_loopback = genphy_loopback,
1755 },
1756 {
1757 PHY_ID_MATCH_MODEL(PHY_ID_RTL8214FC),
1758 .name = "Realtek RTL8214FC",
1759 .features = PHY_GBIT_FIBRE_FEATURES,
1760 .match_phy_device = rtl8214fc_match_phy_device,
1761 .probe = rtl8214fc_phy_probe,
1762 .suspend = genphy_suspend,
1763 .resume = genphy_resume,
1764 .set_loopback = genphy_loopback,
1765 .read_mmd = rtl8218b_read_mmd,
1766 .write_mmd = rtl8218b_write_mmd,
1767 .set_port = rtl8214fc_set_port,
1768 .get_port = rtl8214fc_get_port,
1769 .set_eee = rtl8214fc_set_eee,
1770 .get_eee = rtl8214fc_get_eee,
1771 },
1772 {
1773 PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_E),
1774 .name = "Realtek RTL8218B (external)",
1775 .features = PHY_GBIT_FEATURES,
1776 .match_phy_device = rtl8218b_ext_match_phy_device,
1777 .probe = rtl8218b_ext_phy_probe,
1778 .suspend = genphy_suspend,
1779 .resume = genphy_resume,
1780 .set_loopback = genphy_loopback,
1781 .read_mmd = rtl8218b_read_mmd,
1782 .write_mmd = rtl8218b_write_mmd,
1783 .set_eee = rtl8218b_set_eee,
1784 .get_eee = rtl8218b_get_eee,
1785 },
1786 {
1787 PHY_ID_MATCH_MODEL(PHY_ID_RTL8218D),
1788 .name = "REALTEK RTL8218D",
1789 .features = PHY_GBIT_FEATURES,
1790 .probe = rtl8218d_phy_probe,
1791 .suspend = genphy_suspend,
1792 .resume = genphy_resume,
1793 .set_loopback = genphy_loopback,
1794 }, {
1795 PHY_ID_MATCH_MODEL(PHY_ID_RTL8226),
1796 .name = "REALTEK RTL8226",
1797 .features = PHY_GBIT_FEATURES,
1798 .probe = rtl8226_phy_probe,
1799 .suspend = genphy_suspend,
1800 .resume = genphy_resume,
1801 .set_loopback = genphy_loopback,
1802 .read_mmd = rtl8226_read_mmd,
1803 .write_mmd = rtl8226_write_mmd,
1804 .read_page = rtl8226_read_page,
1805 .write_page = rtl8226_write_page,
1806 .read_status = rtl8226_read_status,
1807 .config_aneg = rtl8226_config_aneg,
1808 },
1809 {
1810 PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_I),
1811 .name = "Realtek RTL8218B (internal)",
1812 .features = PHY_GBIT_FEATURES,
1813 .probe = rtl8218b_int_phy_probe,
1814 .suspend = genphy_suspend,
1815 .resume = genphy_resume,
1816 .set_loopback = genphy_loopback,
1817 .read_mmd = rtl8218b_read_mmd,
1818 .write_mmd = rtl8218b_write_mmd,
1819 .set_eee = rtl8218b_set_eee,
1820 .get_eee = rtl8218b_get_eee,
1821 },
1822 {
1823 PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_I),
1824 .name = "Realtek RTL8380 SERDES",
1825 .features = PHY_GBIT_FIBRE_FEATURES,
1826 .probe = rtl838x_serdes_probe,
1827 .suspend = genphy_suspend,
1828 .resume = genphy_resume,
1829 .set_loopback = genphy_loopback,
1830 .read_mmd = rtl8218b_read_mmd,
1831 .write_mmd = rtl8218b_write_mmd,
1832 .read_status = rtl8380_read_status,
1833 },
1834 {
1835 PHY_ID_MATCH_MODEL(PHY_ID_RTL8393_I),
1836 .name = "Realtek RTL8393 SERDES",
1837 .features = PHY_GBIT_FIBRE_FEATURES,
1838 .probe = rtl8393_serdes_probe,
1839 .suspend = genphy_suspend,
1840 .resume = genphy_resume,
1841 .set_loopback = genphy_loopback,
1842 .read_status = rtl8393_read_status,
1843 },
1844 {
1845 PHY_ID_MATCH_MODEL(PHY_ID_RTL8390_GENERIC),
1846 .name = "Realtek RTL8390 Generic",
1847 .features = PHY_GBIT_FIBRE_FEATURES,
1848 .probe = rtl8390_serdes_probe,
1849 .suspend = genphy_suspend,
1850 .resume = genphy_resume,
1851 .set_loopback = genphy_loopback,
1852 },
1853 {
1854 PHY_ID_MATCH_MODEL(PHY_ID_RTL9300_I),
1855 .name = "REALTEK RTL9300 SERDES",
1856 .features = PHY_GBIT_FIBRE_FEATURES,
1857 .probe = rtl9300_serdes_probe,
1858 .suspend = genphy_suspend,
1859 .resume = genphy_resume,
1860 .set_loopback = genphy_loopback,
1861 },
1862 };
1863
1864 module_phy_driver(rtl83xx_phy_driver);
1865
1866 static struct mdio_device_id __maybe_unused rtl83xx_tbl[] = {
1867 { PHY_ID_MATCH_MODEL(PHY_ID_RTL8214FC) },
1868 { }
1869 };
1870
1871 MODULE_DEVICE_TABLE(mdio, rtl83xx_tbl);
1872
1873 MODULE_AUTHOR("B. Koblitz");
1874 MODULE_DESCRIPTION("RTL83xx PHY driver");
1875 MODULE_LICENSE("GPL");
OpenWrt Source Repository