projects / openwrt / openwrt.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
kernel: bump 5.4 to 5.4.80
[openwrt/openwrt.git] / target / linux / rtl838x / files-5.4 / drivers / net / dsa / rtl838x_sw.c
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <linux/etherdevice.h>
4 #include <linux/if_bridge.h>
5 #include <linux/iopoll.h>
6 #include <linux/mdio.h>
7 #include <linux/mfd/syscon.h>
8 #include <linux/module.h>
9 #include <linux/netdevice.h>
10 #include <linux/of_mdio.h>
11 #include <linux/of_net.h>
12 #include <linux/of_platform.h>
13 #include <linux/phylink.h>
14 #include <linux/phy_fixed.h>
15 #include <net/dsa.h>
16 #include <net/switchdev.h>
17
18 #include <asm/mach-rtl838x/mach-rtl838x.h>
19 #include "rtl838x.h"
20
21 #define RTL8380_VERSION_A 'A'
22 #define RTL8390_VERSION_A 'A'
23 #define RTL8380_VERSION_B 'B'
24
25 DEFINE_MUTEX(smi_lock);
26
27 #define MIB_DESC(_size, _offset, _name) {.size = _size, .offset = _offset, .name = _name}
28 struct rtl838x_mib_desc {
29 unsigned int size;
30 unsigned int offset;
31 const char *name;
32 };
33
34 static inline void rtl838x_mask_port_reg(u64 clear, u64 set, int reg)
35 {
36 sw_w32_mask((u32)clear, (u32)set, reg);
37 }
38
39 static inline void rtl838x_set_port_reg(u64 set, int reg)
40 {
41 sw_w32(set, reg);
42 }
43
44 static inline u64 rtl838x_get_port_reg(int reg)
45 {
46 return ((u64) sw_r32(reg));
47 }
48
49 static inline void rtl839x_mask_port_reg_be(u64 clear, u64 set, int reg)
50 {
51 sw_w32_mask((u32)(clear >> 32), (u32)(set >> 32), reg);
52 sw_w32_mask((u32)(clear & 0xffffffff), (u32)(set & 0xffffffff), reg + 4);
53 }
54
55 static inline void rtl839x_mask_port_reg_le(u64 clear, u64 set, int reg)
56 {
57 sw_w32_mask((u32)clear, (u32)set, reg);
58 sw_w32_mask((u32)(clear >> 32), (u32)(set >> 32), reg + 4);
59 }
60
61 static inline void rtl839x_set_port_reg_be(u64 set, int reg)
62 {
63 sw_w32(set >> 32, reg);
64 sw_w32(set & 0xffffffff, reg + 4);
65 }
66
67 static inline void rtl839x_set_port_reg_le(u64 set, int reg)
68 {
69 sw_w32(set, reg);
70 sw_w32(set >> 32, reg + 4);
71 }
72
73 static inline u64 rtl839x_get_port_reg_be(int reg)
74 {
75 u64 v = sw_r32(reg);
76
77 v <<= 32;
78 v |= sw_r32(reg + 4);
79 return v;
80 }
81
82 static inline u64 rtl839x_get_port_reg_le(int reg)
83 {
84 u64 v = sw_r32(reg + 4);
85
86 v <<= 32;
87 v |= sw_r32(reg);
88 return v;
89 }
90
91 static inline int rtl838x_stat_port_std_mib(int p)
92 {
93 return RTL838X_STAT_PORT_STD_MIB + (p << 8);
94 }
95
96 static inline int rtl839x_stat_port_std_mib(int p)
97 {
98 return RTL839X_STAT_PORT_STD_MIB + (p << 8);
99 }
100
101 static inline int rtl838x_port_iso_ctrl(int p)
102 {
103 return RTL838X_PORT_ISO_CTRL(p);
104 }
105
106 static inline int rtl839x_port_iso_ctrl(int p)
107 {
108 return RTL839X_PORT_ISO_CTRL(p);
109 }
110
111 static inline void rtl838x_exec_tbl0_cmd(u32 cmd)
112 {
113 sw_w32(cmd, RTL838X_TBL_ACCESS_CTRL_0);
114 do { } while (sw_r32(RTL838X_TBL_ACCESS_CTRL_0) & (1 << 15));
115 }
116
117 static inline void rtl839x_exec_tbl0_cmd(u32 cmd)
118 {
119 sw_w32(cmd, RTL839X_TBL_ACCESS_CTRL_0);
120 do { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_0) & (1 << 16));
121 }
122
123 static inline void rtl838x_exec_tbl1_cmd(u32 cmd)
124 {
125 sw_w32(cmd, RTL838X_TBL_ACCESS_CTRL_1);
126 do { } while (sw_r32(RTL838X_TBL_ACCESS_CTRL_1) & (1 << 15));
127 }
128
129 static inline void rtl839x_exec_tbl1_cmd(u32 cmd)
130 {
131 sw_w32(cmd, RTL839X_TBL_ACCESS_CTRL_1);
132 do { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_1) & (1 << 16));
133 }
134
135 static inline int rtl838x_tbl_access_data_0(int i)
136 {
137 return RTL838X_TBL_ACCESS_DATA_0 + (i << 2);
138 }
139
140 static inline int rtl839x_tbl_access_data_0(int i)
141 {
142 return RTL839X_TBL_ACCESS_DATA_0 + (i << 2);
143 }
144
145 static inline int rtl838x_vlan_profile(int profile)
146 {
147 return RTL838X_VLAN_PROFILE + (profile << 2);
148 }
149
150 static inline int rtl839x_vlan_profile(int profile)
151 {
152 return RTL839X_VLAN_PROFILE + (profile << 3);
153 }
154
155 static inline int rtl838x_vlan_port_egr_filter(int port)
156 {
157 return RTL838X_VLAN_PORT_EGR_FLTR;
158 }
159
160 static inline int rtl839x_vlan_port_egr_filter(int port)
161 {
162 return RTL839X_VLAN_PORT_EGR_FLTR + ((port >> 5) << 2);
163 }
164
165 static inline int rtl838x_vlan_port_igr_filter(int port)
166 {
167 return RTL838X_VLAN_PORT_IGR_FLTR + ((port >> 4) << 2);
168 }
169
170 static inline int rtl839x_vlan_port_igr_filter(int port)
171 {
172 return RTL839X_VLAN_PORT_IGR_FLTR + ((port >> 4) << 2);
173 }
174
175 static inline int rtl838x_vlan_port_pb(int port)
176 {
177 return RTL838X_VLAN_PORT_PB_VLAN + (port << 2);
178 }
179
180 static inline int rtl839x_vlan_port_pb(int port)
181 {
182 return RTL839X_VLAN_PORT_PB_VLAN + (port << 2);
183 }
184
185 static void rtl839x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info)
186 {
187 u32 cmd;
188 u64 v;
189 u32 u, w;
190
191 cmd = 1 << 16 /* Execute cmd */
192 | 0 << 15 /* Read */
193 | 0 << 12 /* Table type 0b000 */
194 | (vlan & 0xfff);
195 rtl839x_exec_tbl0_cmd(cmd);
196
197 v = sw_r32(rtl838x_tbl_access_data_0(0));
198 v <<= 32;
199 u = sw_r32(rtl838x_tbl_access_data_0(1));
200 v |= u;
201 info->tagged_ports = v >> 11;
202
203 w = sw_r32(rtl838x_tbl_access_data_0(2));
204
205 info->profile_id = w >> 30 | ((u & 1) << 2);
206 info->hash_mc = !!(u & 2);
207 info->hash_uc = !!(u & 4);
208 info->fid = (u >> 3) & 0xff;
209
210 cmd = 1 << 16 /* Execute cmd */
211 | 0 << 15 /* Read */
212 | 0 << 12 /* Table type 0b000 */
213 | (vlan & 0xfff);
214 rtl839x_exec_tbl1_cmd(cmd);
215 v = sw_r32(RTL838X_TBL_ACCESS_DATA_1(0));
216 v <<= 32;
217 v |= sw_r32(RTL838X_TBL_ACCESS_DATA_1(1));
218 info->untagged_ports = v >> 11;
219 }
220
221 static void rtl838x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info)
222 {
223 u32 cmd, v;
224
225 cmd = 1 << 15 /* Execute cmd */
226 | 1 << 14 /* Read */
227 | 0 << 12 /* Table type 0b00 */
228 | (vlan & 0xfff);
229 rtl838x_exec_tbl0_cmd(cmd);
230 info->tagged_ports = sw_r32(rtl838x_tbl_access_data_0(0));
231 v = sw_r32(rtl838x_tbl_access_data_0(1));
232 info->profile_id = v & 0x7;
233 info->hash_mc = !!(v & 0x8);
234 info->hash_uc = !!(v & 0x10);
235 info->fid = (v >> 5) & 0x3f;
236
237
238 cmd = 1 << 15 /* Execute cmd */
239 | 1 << 14 /* Read */
240 | 0 << 12 /* Table type 0b00 */
241 | (vlan & 0xfff);
242 rtl838x_exec_tbl1_cmd(cmd);
243 info->untagged_ports = sw_r32(RTL838X_TBL_ACCESS_DATA_1(0));
244 }
245
246 static void rtl839x_vlan_set_tagged(u32 vlan, const struct rtl838x_vlan_info *info)
247 {
248 u32 cmd = 1 << 16 /* Execute cmd */
249 | 1 << 15 /* Write */
250 | 0 << 12 /* Table type 0b00 */
251 | (vlan & 0xfff);
252 u32 w;
253 u64 v = info->tagged_ports << 11;
254
255 v |= info->profile_id >> 2;
256 v |= info->hash_mc ? 2 : 0;
257 v |= info->hash_uc ? 4 : 0;
258 v |= ((u32)info->fid) << 3;
259 rtl839x_set_port_reg_be(v, rtl838x_tbl_access_data_0(0));
260
261 w = info->profile_id;
262 sw_w32(w << 30, rtl838x_tbl_access_data_0(2));
263 rtl839x_exec_tbl0_cmd(cmd);
264 }
265
266 static void rtl838x_vlan_set_tagged(u32 vlan, const struct rtl838x_vlan_info *info)
267 {
268 u32 cmd = 1 << 15 /* Execute cmd */
269 | 0 << 14 /* Write */
270 | 0 << 12 /* Table type 0b00 */
271 | (vlan & 0xfff);
272 u32 v;
273
274 sw_w32(info->tagged_ports, rtl838x_tbl_access_data_0(0));
275
276 v = info->profile_id;
277 v |= info->hash_mc ? 0x8 : 0;
278 v |= info->hash_uc ? 0x10 : 0;
279 v |= ((u32)info->fid) << 5;
280
281 sw_w32(v, rtl838x_tbl_access_data_0(1));
282 rtl838x_exec_tbl0_cmd(cmd);
283 }
284
285 static void rtl839x_vlan_set_untagged(u32 vlan, u64 portmask)
286 {
287 u32 cmd = 1 << 16 /* Execute cmd */
288 | 1 << 15 /* Write */
289 | 0 << 12 /* Table type 0b00 */
290 | (vlan & 0xfff);
291 rtl839x_set_port_reg_be(portmask << 11, RTL838X_TBL_ACCESS_DATA_1(0));
292 rtl839x_exec_tbl1_cmd(cmd);
293 }
294
295 static void rtl838x_vlan_set_untagged(u32 vlan, u64 portmask)
296 {
297 u32 cmd = 1 << 15 /* Execute cmd */
298 | 0 << 14 /* Write */
299 | 0 << 12 /* Table type 0b00 */
300 | (vlan & 0xfff);
301 sw_w32(portmask & 0x1fffffff, RTL838X_TBL_ACCESS_DATA_1(0));
302 rtl838x_exec_tbl1_cmd(cmd);
303 }
304
305 static inline int rtl838x_mac_force_mode_ctrl(int p)
306 {
307 return RTL838X_MAC_FORCE_MODE_CTRL + (p << 2);
308 }
309
310 static inline int rtl839x_mac_force_mode_ctrl(int p)
311 {
312 return RTL839X_MAC_FORCE_MODE_CTRL + (p << 2);
313 }
314
315 static inline int rtl838x_mac_port_ctrl(int p)
316 {
317 return RTL838X_MAC_PORT_CTRL(p);
318 }
319
320 static inline int rtl839x_mac_port_ctrl(int p)
321 {
322 return RTL839X_MAC_PORT_CTRL(p);
323 }
324
325 static inline int rtl838x_l2_port_new_salrn(int p)
326 {
327 return RTL838X_L2_PORT_NEW_SALRN(p);
328 }
329
330 static inline int rtl839x_l2_port_new_salrn(int p)
331 {
332 return RTL839X_L2_PORT_NEW_SALRN(p);
333 }
334
335 static inline int rtl838x_l2_port_new_sa_fwd(int p)
336 {
337 return RTL838X_L2_PORT_NEW_SA_FWD(p);
338 }
339
340 static inline int rtl839x_l2_port_new_sa_fwd(int p)
341 {
342 return RTL839X_L2_PORT_NEW_SA_FWD(p);
343 }
344
345 static inline int rtl838x_mac_link_spd_sts(int p)
346 {
347 return RTL838X_MAC_LINK_SPD_STS(p);
348 }
349
350 static inline int rtl839x_mac_link_spd_sts(int p)
351 {
352 return RTL839X_MAC_LINK_SPD_STS(p);
353 }
354
355 static inline int rtl838x_mir_ctrl(int group)
356 {
357 return RTL838X_MIR_CTRL(group);
358 }
359
360 static inline int rtl839x_mir_ctrl(int group)
361 {
362 return RTL839X_MIR_CTRL(group);
363 }
364
365 static inline int rtl838x_mir_dpm(int group)
366 {
367 return RTL838X_MIR_DPM_CTRL(group);
368 }
369
370 static inline int rtl839x_mir_dpm(int group)
371 {
372 return RTL839X_MIR_DPM_CTRL(group);
373 }
374
375 static inline int rtl838x_mir_spm(int group)
376 {
377 return RTL838X_MIR_SPM_CTRL(group);
378 }
379
380 static inline int rtl839x_mir_spm(int group)
381 {
382 return RTL839X_MIR_SPM_CTRL(group);
383 }
384
385 static u64 rtl838x_read_l2_entry_using_hash(u32 hash, u32 position, struct rtl838x_l2_entry *e)
386 {
387 u64 entry;
388 u32 r[3];
389
390 /* Search in SRAM, with hash and at position in hash bucket (0-3) */
391 u32 idx = (0 << 14) | (hash << 2) | position;
392
393 u32 cmd = 1 << 16 /* Execute cmd */
394 | 1 << 15 /* Read */
395 | 0 << 13 /* Table type 0b00 */
396 | (idx & 0x1fff);
397
398 sw_w32(cmd, RTL838X_TBL_ACCESS_L2_CTRL);
399 do { } while (sw_r32(RTL838X_TBL_ACCESS_L2_CTRL) & (1 << 16));
400 r[0] = sw_r32(RTL838X_TBL_ACCESS_L2_DATA(0));
401 r[1] = sw_r32(RTL838X_TBL_ACCESS_L2_DATA(1));
402 r[2] = sw_r32(RTL838X_TBL_ACCESS_L2_DATA(2));
403
404 e->mac[0] = (r[1] >> 20);
405 e->mac[1] = (r[1] >> 12);
406 e->mac[2] = (r[1] >> 4);
407 e->mac[3] = (r[1] & 0xf) << 4 | (r[2] >> 28);
408 e->mac[4] = (r[2] >> 20);
409 e->mac[5] = (r[2] >> 12);
410 e->is_static = !!((r[0] >> 19) & 1);
411 e->vid = r[0] & 0xfff;
412 e->rvid = r[2] & 0xfff;
413 e->port = (r[0] >> 12) & 0x1f;
414
415 e->valid = true;
416 if (!(r[0] >> 17)) /* Check for invalid entry */
417 e->valid = false;
418
419 if (e->valid)
420 pr_info("Found in Hash: R1 %x R2 %x R3 %x\n", r[0], r[1], r[2]);
421
422 entry = (((u64) r[1]) << 32) | (r[2] & 0xfffff000) | (r[0] & 0xfff);
423 return entry;
424 }
425
426 static u64 rtl839x_read_l2_entry_using_hash(u32 hash, u32 position, struct rtl838x_l2_entry *e)
427 {
428 u64 entry;
429 u32 r[3];
430
431 /* Search in SRAM, with hash and at position in hash bucket (0-3) */
432 u32 idx = (0 << 14) | (hash << 2) | position;
433
434 u32 cmd = 1 << 17 /* Execute cmd */
435 | 0 << 16 /* Read */
436 | 0 << 14 /* Table type 0b00 */
437 | (idx & 0x3fff);
438
439 sw_w32(cmd, RTL839X_TBL_ACCESS_L2_CTRL);
440 do { } while (sw_r32(RTL839X_TBL_ACCESS_L2_CTRL) & (1 << 17));
441 r[0] = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(0));
442 r[1] = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(1));
443 r[2] = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(2));
444
445 /* Table contains different entry types, we need to identify the right one:
446 * Check for MC entries, first
447 */
448 e->is_ip_mc = !!(r[2] & (1 << 31));
449 e->is_ipv6_mc = !!(r[2] & (1 << 30));
450 e->type = L2_INVALID;
451 if (!e->is_ip_mc) {
452 e->mac[0] = (r[0] >> 12);
453 e->mac[1] = (r[0] >> 4);
454 e->mac[2] = ((r[1] >> 28) | (r[0] << 4));
455 e->mac[3] = (r[1] >> 20);
456 e->mac[4] = (r[1] >> 12);
457 e->mac[5] = (r[1] >> 4);
458
459 /* Is it a unicast entry? check multicast bit */
460 if (!(e->mac[0] & 1)) {
461 e->is_static = !!((r[2] >> 18) & 1);
462 e->vid = (r[2] >> 4) & 0xfff;
463 e->rvid = (r[0] >> 20) & 0xfff;
464 e->port = (r[2] >> 24) & 0x3f;
465 e->block_da = !!(r[2] & (1 << 19));
466 e->block_sa = !!(r[2] & (1 << 20));
467 e->suspended = !!(r[2] & (1 << 17));
468 e->next_hop = !!(r[2] & (1 << 16));
469 if (e->next_hop)
470 pr_info("Found next hop entry, need to read data\n");
471 e->age = (r[2] >> 21) & 3;
472 e->valid = true;
473 if (!(r[2] & 0xc0fd0000)) /* Check for valid entry */
474 e->valid = false;
475 else
476 e->type = L2_UNICAST;
477 } else {
478 e->valid = true;
479 e->type = L2_MULTICAST;
480 e->mc_portmask_index = (r[2] >> 6) & 0xfff;
481 }
482 }
483 if (e->is_ip_mc) {
484 e->valid = true;
485 e->type = IP4_MULTICAST;
486 }
487 if (e->is_ipv6_mc) {
488 e->valid = true;
489 e->type = IP6_MULTICAST;
490 }
491
492 entry = (((u64) r[0]) << 44) | ((u64)(r[1] & 0xfffffff0) << 12) | ((r[2] >> 4) & 0xfff);
493 return entry;
494 }
495
496 static u64 rtl838x_read_cam(int idx, struct rtl838x_l2_entry *e)
497 {
498 u64 entry;
499 u32 r[3];
500
501 u32 cmd = 1 << 16 /* Execute cmd */
502 | 1 << 15 /* Read */
503 | 1 << 13 /* Table type 0b01 */
504 | (idx & 0x3f);
505 sw_w32(cmd, RTL838X_TBL_ACCESS_L2_CTRL);
506 do { } while (sw_r32(RTL838X_TBL_ACCESS_L2_CTRL) & (1 << 16));
507 r[0] = sw_r32(RTL838X_TBL_ACCESS_L2_DATA(0));
508 r[1] = sw_r32(RTL838X_TBL_ACCESS_L2_DATA(1));
509 r[2] = sw_r32(RTL838X_TBL_ACCESS_L2_DATA(2));
510
511 e->mac[0] = (r[1] >> 20);
512 e->mac[1] = (r[1] >> 12);
513 e->mac[2] = (r[1] >> 4);
514 e->mac[3] = (r[1] & 0xf) << 4 | (r[2] >> 28);
515 e->mac[4] = (r[2] >> 20);
516 e->mac[5] = (r[2] >> 12);
517 e->is_static = !!((r[0] >> 19) & 1);
518 e->vid = r[0] & 0xfff;
519 e->rvid = r[2] & 0xfff;
520 e->port = (r[0] >> 12) & 0x1f;
521
522 e->valid = true;
523 if (!(r[0] >> 17)) /* Check for invalid entry */
524 e->valid = false;
525
526 if (e->valid)
527 pr_info("Found in CAM: R1 %x R2 %x R3 %x\n", r[0], r[1], r[2]);
528
529 entry = (((u64) r[1]) << 32) | (r[2] & 0xfffff000) | (r[0] & 0xfff);
530 return entry;
531 }
532
533 static u64 rtl839x_read_cam(int idx, struct rtl838x_l2_entry *e)
534 {
535 u64 entry;
536 u32 r[3];
537
538 u32 cmd = 1 << 17 /* Execute cmd */
539 | 0 << 16 /* Read */
540 | 1 << 14 /* Table type 0b01 */
541 | (idx & 0x3f);
542 sw_w32(cmd, RTL839X_TBL_ACCESS_L2_CTRL);
543 do { } while (sw_r32(RTL839X_TBL_ACCESS_L2_CTRL) & (1 << 17));
544 r[0] = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(0));
545 r[1] = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(1));
546 r[2] = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(2));
547
548 e->mac[0] = (r[0] >> 12);
549 e->mac[1] = (r[0] >> 4);
550 e->mac[2] = ((r[1] >> 28) | (r[0] << 4));
551 e->mac[3] = (r[1] >> 20);
552 e->mac[4] = (r[1] >> 12);
553 e->mac[5] = (r[1] >> 4);
554 e->is_static = !!((r[2] >> 18) & 1);
555 e->vid = (r[2] >> 4) & 0xfff;
556 e->rvid = (r[0] >> 20) & 0xfff;
557 e->port = (r[2] >> 24) & 0x3f;
558
559 e->valid = true;
560 if (!(r[2] & 0x10fd0000)) /* Check for invalid entry */
561 e->valid = false;
562
563 if (e->valid)
564 pr_info("Found in CAM: R1 %x R2 %x R3 %x\n", r[0], r[1], r[2]);
565
566 entry = (((u64) r[0]) << 12) | ((r[1] & 0xfffffff0) << 12) | ((r[2] >> 4) & 0xfff);
567 return entry;
568 }
569
570 static const struct rtl838x_reg rtl838x_reg = {
571 .mask_port_reg_be = rtl838x_mask_port_reg,
572 .set_port_reg_be = rtl838x_set_port_reg,
573 .get_port_reg_be = rtl838x_get_port_reg,
574 .mask_port_reg_le = rtl838x_mask_port_reg,
575 .set_port_reg_le = rtl838x_set_port_reg,
576 .get_port_reg_le = rtl838x_get_port_reg,
577 .stat_port_rst = RTL838X_STAT_PORT_RST,
578 .stat_rst = RTL838X_STAT_RST,
579 .stat_port_std_mib = rtl838x_stat_port_std_mib,
580 .port_iso_ctrl = rtl838x_port_iso_ctrl,
581 .l2_ctrl_0 = RTL838X_L2_CTRL_0,
582 .l2_ctrl_1 = RTL838X_L2_CTRL_1,
583 .l2_port_aging_out = RTL838X_L2_PORT_AGING_OUT,
584 .smi_poll_ctrl = RTL838X_SMI_POLL_CTRL,
585 .l2_tbl_flush_ctrl = RTL838X_L2_TBL_FLUSH_CTRL,
586 .exec_tbl0_cmd = rtl838x_exec_tbl0_cmd,
587 .exec_tbl1_cmd = rtl838x_exec_tbl1_cmd,
588 .tbl_access_data_0 = rtl838x_tbl_access_data_0,
589 .isr_glb_src = RTL838X_ISR_GLB_SRC,
590 .isr_port_link_sts_chg = RTL838X_ISR_PORT_LINK_STS_CHG,
591 .imr_port_link_sts_chg = RTL838X_IMR_PORT_LINK_STS_CHG,
592 .imr_glb = RTL838X_IMR_GLB,
593 .vlan_tables_read = rtl838x_vlan_tables_read,
594 .vlan_set_tagged = rtl838x_vlan_set_tagged,
595 .vlan_set_untagged = rtl838x_vlan_set_untagged,
596 .mac_force_mode_ctrl = rtl838x_mac_force_mode_ctrl,
597 .mac_port_ctrl = rtl838x_mac_port_ctrl,
598 .l2_port_new_salrn = rtl838x_l2_port_new_salrn,
599 .l2_port_new_sa_fwd = rtl838x_l2_port_new_sa_fwd,
600 .mir_ctrl = rtl838x_mir_ctrl,
601 .mir_dpm = rtl838x_mir_dpm,
602 .mir_spm = rtl838x_mir_spm,
603 .mac_link_sts = RTL838X_MAC_LINK_STS,
604 .mac_link_dup_sts = RTL838X_MAC_LINK_DUP_STS,
605 .mac_link_spd_sts = rtl838x_mac_link_spd_sts,
606 .mac_rx_pause_sts = RTL838X_MAC_RX_PAUSE_STS,
607 .mac_tx_pause_sts = RTL838X_MAC_TX_PAUSE_STS,
608 .read_l2_entry_using_hash = rtl838x_read_l2_entry_using_hash,
609 .read_cam = rtl838x_read_cam,
610 .vlan_profile = rtl838x_vlan_profile,
611 .vlan_port_egr_filter = rtl838x_vlan_port_egr_filter,
612 .vlan_port_igr_filter = rtl838x_vlan_port_igr_filter,
613 .vlan_port_pb = rtl838x_vlan_port_pb,
614 };
615
616 static const struct rtl838x_reg rtl839x_reg = {
617 .mask_port_reg_be = rtl839x_mask_port_reg_be,
618 .set_port_reg_be = rtl839x_set_port_reg_be,
619 .get_port_reg_be = rtl839x_get_port_reg_be,
620 .mask_port_reg_le = rtl839x_mask_port_reg_le,
621 .set_port_reg_le = rtl839x_set_port_reg_le,
622 .get_port_reg_le = rtl839x_get_port_reg_le,
623 .stat_port_rst = RTL839X_STAT_PORT_RST,
624 .stat_rst = RTL839X_STAT_RST,
625 .stat_port_std_mib = rtl839x_stat_port_std_mib,
626 .port_iso_ctrl = rtl839x_port_iso_ctrl,
627 .l2_ctrl_0 = RTL839X_L2_CTRL_0,
628 .l2_ctrl_1 = RTL839X_L2_CTRL_1,
629 .l2_port_aging_out = RTL839X_L2_PORT_AGING_OUT,
630 .smi_poll_ctrl = RTL839X_SMI_PORT_POLLING_CTRL,
631 .l2_tbl_flush_ctrl = RTL839X_L2_TBL_FLUSH_CTRL,
632 .exec_tbl0_cmd = rtl839x_exec_tbl0_cmd,
633 .exec_tbl1_cmd = rtl839x_exec_tbl1_cmd,
634 .tbl_access_data_0 = rtl839x_tbl_access_data_0,
635 .isr_glb_src = RTL839X_ISR_GLB_SRC,
636 .isr_port_link_sts_chg = RTL839X_ISR_PORT_LINK_STS_CHG,
637 .imr_port_link_sts_chg = RTL839X_IMR_PORT_LINK_STS_CHG,
638 .imr_glb = RTL839X_IMR_GLB,
639 .vlan_tables_read = rtl839x_vlan_tables_read,
640 .vlan_set_tagged = rtl839x_vlan_set_tagged,
641 .vlan_set_untagged = rtl839x_vlan_set_untagged,
642 .mac_force_mode_ctrl = rtl839x_mac_force_mode_ctrl,
643 .mac_port_ctrl = rtl839x_mac_port_ctrl,
644 .l2_port_new_salrn = rtl839x_l2_port_new_salrn,
645 .l2_port_new_sa_fwd = rtl839x_l2_port_new_sa_fwd,
646 .mir_ctrl = rtl839x_mir_ctrl,
647 .mir_dpm = rtl839x_mir_dpm,
648 .mir_spm = rtl839x_mir_spm,
649 .mac_link_sts = RTL839X_MAC_LINK_STS,
650 .mac_link_dup_sts = RTL839X_MAC_LINK_DUP_STS,
651 .mac_link_spd_sts = rtl839x_mac_link_spd_sts,
652 .mac_rx_pause_sts = RTL839X_MAC_RX_PAUSE_STS,
653 .mac_tx_pause_sts = RTL839X_MAC_TX_PAUSE_STS,
654 .read_l2_entry_using_hash = rtl839x_read_l2_entry_using_hash,
655 .read_cam = rtl839x_read_cam,
656 .vlan_profile = rtl839x_vlan_profile,
657 .vlan_port_egr_filter = rtl839x_vlan_port_egr_filter,
658 .vlan_port_igr_filter = rtl839x_vlan_port_igr_filter,
659 .vlan_port_pb = rtl839x_vlan_port_pb,
660 };
661
662 static const struct rtl838x_mib_desc rtl838x_mib[] = {
663 MIB_DESC(2, 0xf8, "ifInOctets"),
664 MIB_DESC(2, 0xf0, "ifOutOctets"),
665 MIB_DESC(1, 0xec, "dot1dTpPortInDiscards"),
666 MIB_DESC(1, 0xe8, "ifInUcastPkts"),
667 MIB_DESC(1, 0xe4, "ifInMulticastPkts"),
668 MIB_DESC(1, 0xe0, "ifInBroadcastPkts"),
669 MIB_DESC(1, 0xdc, "ifOutUcastPkts"),
670 MIB_DESC(1, 0xd8, "ifOutMulticastPkts"),
671 MIB_DESC(1, 0xd4, "ifOutBroadcastPkts"),
672 MIB_DESC(1, 0xd0, "ifOutDiscards"),
673 MIB_DESC(1, 0xcc, ".3SingleCollisionFrames"),
674 MIB_DESC(1, 0xc8, ".3MultipleCollisionFrames"),
675 MIB_DESC(1, 0xc4, ".3DeferredTransmissions"),
676 MIB_DESC(1, 0xc0, ".3LateCollisions"),
677 MIB_DESC(1, 0xbc, ".3ExcessiveCollisions"),
678 MIB_DESC(1, 0xb8, ".3SymbolErrors"),
679 MIB_DESC(1, 0xb4, ".3ControlInUnknownOpcodes"),
680 MIB_DESC(1, 0xb0, ".3InPauseFrames"),
681 MIB_DESC(1, 0xac, ".3OutPauseFrames"),
682 MIB_DESC(1, 0xa8, "DropEvents"),
683 MIB_DESC(1, 0xa4, "tx_BroadcastPkts"),
684 MIB_DESC(1, 0xa0, "tx_MulticastPkts"),
685 MIB_DESC(1, 0x9c, "CRCAlignErrors"),
686 MIB_DESC(1, 0x98, "tx_UndersizePkts"),
687 MIB_DESC(1, 0x94, "rx_UndersizePkts"),
688 MIB_DESC(1, 0x90, "rx_UndersizedropPkts"),
689 MIB_DESC(1, 0x8c, "tx_OversizePkts"),
690 MIB_DESC(1, 0x88, "rx_OversizePkts"),
691 MIB_DESC(1, 0x84, "Fragments"),
692 MIB_DESC(1, 0x80, "Jabbers"),
693 MIB_DESC(1, 0x7c, "Collisions"),
694 MIB_DESC(1, 0x78, "tx_Pkts64Octets"),
695 MIB_DESC(1, 0x74, "rx_Pkts64Octets"),
696 MIB_DESC(1, 0x70, "tx_Pkts65to127Octets"),
697 MIB_DESC(1, 0x6c, "rx_Pkts65to127Octets"),
698 MIB_DESC(1, 0x68, "tx_Pkts128to255Octets"),
699 MIB_DESC(1, 0x64, "rx_Pkts128to255Octets"),
700 MIB_DESC(1, 0x60, "tx_Pkts256to511Octets"),
701 MIB_DESC(1, 0x5c, "rx_Pkts256to511Octets"),
702 MIB_DESC(1, 0x58, "tx_Pkts512to1023Octets"),
703 MIB_DESC(1, 0x54, "rx_Pkts512to1023Octets"),
704 MIB_DESC(1, 0x50, "tx_Pkts1024to1518Octets"),
705 MIB_DESC(1, 0x4c, "rx_StatsPkts1024to1518Octets"),
706 MIB_DESC(1, 0x48, "tx_Pkts1519toMaxOctets"),
707 MIB_DESC(1, 0x44, "rx_Pkts1519toMaxOctets"),
708 MIB_DESC(1, 0x40, "rxMacDiscards")
709 };
710
711 static irqreturn_t rtl838x_switch_irq(int irq, void *dev_id)
712 {
713 struct dsa_switch *ds = dev_id;
714 u32 status = sw_r32(RTL838X_ISR_GLB_SRC);
715 u32 ports = sw_r32(RTL838X_ISR_PORT_LINK_STS_CHG);
716 u32 link;
717 int i;
718
719 /* Clear status */
720 sw_w32(ports, RTL838X_ISR_PORT_LINK_STS_CHG);
721 pr_info("RTL8380 Link change: status: %x, ports %x\n", status, ports);
722
723 for (i = 0; i < 28; i++) {
724 if (ports & (1 << i)) {
725 link = sw_r32(RTL838X_MAC_LINK_STS);
726 if (link & (1 << i))
727 dsa_port_phylink_mac_change(ds, i, true);
728 else
729 dsa_port_phylink_mac_change(ds, i, false);
730 }
731 }
732 return IRQ_HANDLED;
733 }
734
735 static irqreturn_t rtl839x_switch_irq(int irq, void *dev_id)
736 {
737 struct dsa_switch *ds = dev_id;
738 u32 status = sw_r32(RTL839X_ISR_GLB_SRC);
739 u64 ports = rtl839x_get_port_reg_le(RTL839X_ISR_PORT_LINK_STS_CHG);
740 u64 link;
741 int i;
742
743 /* Clear status */
744 rtl839x_set_port_reg_le(ports, RTL839X_ISR_PORT_LINK_STS_CHG);
745 pr_info("RTL8390 Link change: status: %x, ports %llx\n", status, ports);
746
747 for (i = 0; i < 52; i++) {
748 if (ports & (1ULL << i)) {
749 link = rtl839x_get_port_reg_le(RTL839X_MAC_LINK_STS);
750 if (link & (1ULL << i))
751 dsa_port_phylink_mac_change(ds, i, true);
752 else
753 dsa_port_phylink_mac_change(ds, i, false);
754 }
755 }
756 return IRQ_HANDLED;
757 }
758
759 struct fdb_update_work {
760 struct work_struct work;
761 struct net_device *ndev;
762 u64 macs[];
763 };
764
765 void rtl838x_fdb_sync(struct work_struct *work)
766 {
767 const struct fdb_update_work *uw =
768 container_of(work, struct fdb_update_work, work);
769 struct switchdev_notifier_fdb_info info;
770 u8 addr[ETH_ALEN];
771 int i = 0;
772 int action;
773
774 while (uw->macs[i]) {
775 action = (uw->macs[i] & (1ULL << 63)) ? SWITCHDEV_FDB_ADD_TO_BRIDGE
776 : SWITCHDEV_FDB_DEL_TO_BRIDGE;
777 u64_to_ether_addr(uw->macs[i] & 0xffffffffffffULL, addr);
778 info.addr = &addr[0];
779 info.vid = 0;
780 info.offloaded = 1;
781 pr_debug("FDB entry %d: %llx, action %d\n", i, uw->macs[0], action);
782 call_switchdev_notifiers(action, uw->ndev, &info.info, NULL);
783 i++;
784 }
785 kfree(work);
786 }
787
788 int rtl8380_sds_power(int mac, int val)
789 {
790 u32 mode = (val == 1) ? 0x4 : 0x9;
791 u32 offset = (mac == 24) ? 5 : 0;
792
793 if ((mac != 24) && (mac != 26)) {
794 pr_err("%s: not a fibre port: %d\n", __func__, mac);
795 return -1;
796 }
797
798 sw_w32_mask(0x1f << offset, mode << offset, RTL838X_SDS_MODE_SEL);
799
800 rtl8380_sds_rst(mac);
801
802 return 0;
803 }
804
805 int rtl8390_sds_power(int mac, int val)
806 {
807 u32 offset = (mac == 48) ? 0x0 : 0x100;
808 u32 mode = val ? 0 : 1;
809
810 pr_info("In %s: mac %d, set %d\n", __func__, mac, val);
811
812 if ((mac != 48) && (mac != 49)) {
813 pr_err("%s: not an SFP port: %d\n", __func__, mac);
814 return -1;
815 }
816
817 // Set bit 1003. 1000 starts at 7c
818 sw_w32_mask(1 << 11, mode << 11, RTL839X_SDS12_13_PWR0 + offset);
819
820 return 0;
821 }
822
823 static int rtl838x_smi_wait_op(int timeout)
824 {
825 do {
826 timeout--;
827 udelay(10);
828 } while ((sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_1) & 0x1) && (timeout >= 0));
829 if (timeout <= 0)
830 return -1;
831 return 0;
832 }
833
834 /*
835 * Write to a register in a page of the PHY
836 */
837 int rtl838x_write_phy(u32 port, u32 page, u32 reg, u32 val)
838 {
839 u32 v;
840 u32 park_page;
841
842 val &= 0xffff;
843 if (port > 31 || page > 4095 || reg > 31)
844 return -ENOTSUPP;
845
846 mutex_lock(&smi_lock);
847 if (rtl838x_smi_wait_op(10000))
848 goto timeout;
849
850 sw_w32(1 << port, RTL838X_SMI_ACCESS_PHY_CTRL_0);
851 mdelay(10);
852
853 sw_w32_mask(0xffff0000, val << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2);
854
855 park_page = sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_1) & ((0x1f << 15) | 0x2);
856 v = reg << 20 | page << 3 | 0x4;
857 sw_w32(v | park_page, RTL838X_SMI_ACCESS_PHY_CTRL_1);
858 sw_w32_mask(0, 1, RTL838X_SMI_ACCESS_PHY_CTRL_1);
859
860 if (rtl838x_smi_wait_op(10000))
861 goto timeout;
862
863 mutex_unlock(&smi_lock);
864 return 0;
865
866 timeout:
867 mutex_unlock(&smi_lock);
868 return -ETIMEDOUT;
869 }
870
871 int rtl839x_write_phy(u32 port, u32 page, u32 reg, u32 val)
872 {
873 u32 v;
874 int err = 0;
875
876 val &= 0xffff;
877 if (port > 63 || page > 4095 || reg > 31)
878 return -ENOTSUPP;
879
880 mutex_lock(&smi_lock);
881 /* Clear both port registers */
882 sw_w32(0, RTL839X_PHYREG_PORT_CTRL(0));
883 sw_w32(0, RTL839X_PHYREG_PORT_CTRL(0) + 4);
884 sw_w32_mask(0, 1 << port, RTL839X_PHYREG_PORT_CTRL(port));
885
886 sw_w32_mask(0xffff0000, val << 16, RTL839X_PHYREG_DATA_CTRL);
887
888 v = reg << 5 | page << 10 | ((page == 0x1fff) ? 0x1f : 0) << 23;
889 sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
890
891 sw_w32(0x1ff, RTL839X_PHYREG_CTRL);
892
893 v |= 1 << 3 | 1; /* Write operation and execute */
894 sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
895
896 do {
897 } while (sw_r32(RTL839X_PHYREG_ACCESS_CTRL) & 0x1);
898
899 if (sw_r32(RTL839X_PHYREG_ACCESS_CTRL) & 0x2)
900 err = -EIO;
901
902 mutex_unlock(&smi_lock);
903 return err;
904 }
905
906 /*
907 * Reads a register in a page from the PHY
908 */
909 int rtl838x_read_phy(u32 port, u32 page, u32 reg, u32 *val)
910 {
911 u32 v;
912 u32 park_page;
913
914 if (port > 31) {
915 *val = 0xffff;
916 return 0;
917 }
918
919 if (page > 4095 || reg > 31)
920 return -ENOTSUPP;
921
922 mutex_lock(&smi_lock);
923
924 if (rtl838x_smi_wait_op(10000))
925 goto timeout;
926
927 sw_w32_mask(0xffff0000, port << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2);
928
929 park_page = sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_1) & ((0x1f << 15) | 0x2);
930 v = reg << 20 | page << 3;
931 sw_w32(v | park_page, RTL838X_SMI_ACCESS_PHY_CTRL_1);
932 sw_w32_mask(0, 1, RTL838X_SMI_ACCESS_PHY_CTRL_1);
933
934 if (rtl838x_smi_wait_op(10000))
935 goto timeout;
936
937 *val = sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_2) & 0xffff;
938
939 mutex_unlock(&smi_lock);
940 return 0;
941
942 timeout:
943 mutex_unlock(&smi_lock);
944 return -ETIMEDOUT;
945 }
946
947 int rtl839x_read_phy(u32 port, u32 page, u32 reg, u32 *val)
948 {
949 u32 v;
950
951 if (port > 63 || page > 4095 || reg > 31)
952 return -ENOTSUPP;
953
954 mutex_lock(&smi_lock);
955
956 sw_w32_mask(0xffff0000, port << 16, RTL839X_PHYREG_DATA_CTRL);
957 v = reg << 5 | page << 10 | ((page == 0x1fff) ? 0x1f : 0) << 23;
958 sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
959
960 sw_w32(0x1ff, RTL839X_PHYREG_CTRL);
961
962 v |= 1;
963 sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
964
965 do {
966 } while (sw_r32(RTL839X_PHYREG_ACCESS_CTRL) & 0x1);
967
968 *val = sw_r32(RTL839X_PHYREG_DATA_CTRL) & 0xffff;
969
970 mutex_unlock(&smi_lock);
971 return 0;
972 }
973
974 static int read_phy(u32 port, u32 page, u32 reg, u32 *val)
975 {
976 if (soc_info.family == RTL8390_FAMILY_ID)
977 return rtl839x_read_phy(port, page, reg, val);
978 else
979 return rtl838x_read_phy(port, page, reg, val);
980 }
981
982 static int write_phy(u32 port, u32 page, u32 reg, u32 val)
983 {
984 if (soc_info.family == RTL8390_FAMILY_ID)
985 return rtl839x_write_phy(port, page, reg, val);
986 else
987 return rtl838x_write_phy(port, page, reg, val);
988 }
989
990 /*
991 * Write to an mmd register of the PHY
992 */
993 int rtl838x_write_mmd_phy(u32 port, u32 addr, u32 reg, u32 val)
994 {
995 u32 v;
996
997 pr_debug("MMD write: port %d, dev %d, reg %d, val %x\n", port, addr, reg, val);
998 val &= 0xffff;
999 mutex_lock(&smi_lock);
1000
1001 if (rtl838x_smi_wait_op(10000))
1002 goto timeout;
1003
1004 sw_w32(1 << port, RTL838X_SMI_ACCESS_PHY_CTRL_0);
1005 mdelay(10);
1006
1007 sw_w32_mask(0xffff0000, val << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2);
1008
1009 sw_w32_mask(0x1f << 16, addr << 16, RTL838X_SMI_ACCESS_PHY_CTRL_3);
1010 sw_w32_mask(0xffff, reg, RTL838X_SMI_ACCESS_PHY_CTRL_3);
1011 /* mmd-access | write | cmd-start */
1012 v = 1 << 1 | 1 << 2 | 1;
1013 sw_w32(v, RTL838X_SMI_ACCESS_PHY_CTRL_1);
1014
1015 if (rtl838x_smi_wait_op(10000))
1016 goto timeout;
1017
1018 mutex_unlock(&smi_lock);
1019 return 0;
1020
1021 timeout:
1022 mutex_unlock(&smi_lock);
1023 return -ETIMEDOUT;
1024 }
1025
1026 /*
1027 * Read an mmd register of the PHY
1028 */
1029 int rtl838x_read_mmd_phy(u32 port, u32 addr, u32 reg, u32 *val)
1030 {
1031 u32 v;
1032
1033 mutex_lock(&smi_lock);
1034
1035 if (rtl838x_smi_wait_op(10000))
1036 goto timeout;
1037
1038 sw_w32(1 << port, RTL838X_SMI_ACCESS_PHY_CTRL_0);
1039 mdelay(10);
1040
1041 sw_w32_mask(0xffff0000, port << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2);
1042
1043 v = addr << 16 | reg;
1044 sw_w32(v, RTL838X_SMI_ACCESS_PHY_CTRL_3);
1045
1046 /* mmd-access | read | cmd-start */
1047 v = 1 << 1 | 0 << 2 | 1;
1048 sw_w32(v, RTL838X_SMI_ACCESS_PHY_CTRL_1);
1049
1050 if (rtl838x_smi_wait_op(10000))
1051 goto timeout;
1052
1053 *val = sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_2) & 0xffff;
1054
1055 mutex_unlock(&smi_lock);
1056 return 0;
1057
1058 timeout:
1059 mutex_unlock(&smi_lock);
1060 return -ETIMEDOUT;
1061 }
1062
1063 static void rtl8380_get_version(struct rtl838x_switch_priv *priv)
1064 {
1065 u32 rw_save, info_save;
1066 u32 info;
1067
1068 if (priv->id)
1069 pr_debug("SoC ID: %4x: %s\n", priv->id, soc_info.name);
1070 else
1071 pr_err("Unknown chip id (%04x)\n", priv->id);
1072
1073 rw_save = sw_r32(RTL838X_INT_RW_CTRL);
1074 sw_w32(rw_save | 0x3, RTL838X_INT_RW_CTRL);
1075
1076 info_save = sw_r32(RTL838X_CHIP_INFO);
1077 sw_w32(info_save | 0xA0000000, RTL838X_CHIP_INFO);
1078
1079 info = sw_r32(RTL838X_CHIP_INFO);
1080 sw_w32(info_save, RTL838X_CHIP_INFO);
1081 sw_w32(rw_save, RTL838X_INT_RW_CTRL);
1082
1083 if ((info & 0xFFFF) == 0x6275) {
1084 if (((info >> 16) & 0x1F) == 0x1)
1085 priv->version = RTL8380_VERSION_A;
1086 else if (((info >> 16) & 0x1F) == 0x2)
1087 priv->version = RTL8380_VERSION_B;
1088 else
1089 priv->version = RTL8380_VERSION_B;
1090 } else {
1091 priv->version = '-';
1092 }
1093 }
1094
1095 static void rtl8390_get_version(struct rtl838x_switch_priv *priv)
1096 {
1097 u32 info;
1098
1099 sw_w32_mask(0xf << 28, 0xa << 28, RTL839X_CHIP_INFO);
1100 info = sw_r32(RTL839X_CHIP_INFO);
1101 pr_info("Chip-Info: %x\n", info);
1102 priv->version = RTL8390_VERSION_A;
1103 }
1104
1105 int dsa_phy_read(struct dsa_switch *ds, int phy_addr, int phy_reg)
1106 {
1107 u32 val;
1108 u32 offset = 0;
1109 struct rtl838x_switch_priv *priv = ds->priv;
1110
1111 if (phy_addr >= 24 && phy_addr <= 27
1112 && priv->ports[24].phy == PHY_RTL838X_SDS) {
1113 if (phy_addr == 26)
1114 offset = 0x100;
1115 val = sw_r32(MAPLE_SDS4_FIB_REG0r + offset + (phy_reg << 2)) & 0xffff;
1116 return val;
1117 }
1118
1119 read_phy(phy_addr, 0, phy_reg, &val);
1120 return val;
1121 }
1122
1123 int dsa_phy_write(struct dsa_switch *ds, int phy_addr, int phy_reg, u16 val)
1124 {
1125 u32 offset = 0;
1126 struct rtl838x_switch_priv *priv = ds->priv;
1127
1128 if (phy_addr >= 24 && phy_addr <= 27
1129 && priv->ports[24].phy == PHY_RTL838X_SDS) {
1130 if (phy_addr == 26)
1131 offset = 0x100;
1132 sw_w32(val, MAPLE_SDS4_FIB_REG0r + offset + (phy_reg << 2));
1133 return 0;
1134 }
1135 return write_phy(phy_addr, 0, phy_reg, val);
1136 }
1137
1138 static int rtl838x_mdio_read(struct mii_bus *bus, int addr, int regnum)
1139 {
1140 int ret;
1141 struct rtl838x_switch_priv *priv = bus->priv;
1142
1143 ret = dsa_phy_read(priv->ds, addr, regnum);
1144 return ret;
1145 }
1146
1147 static int rtl838x_mdio_write(struct mii_bus *bus, int addr, int regnum,
1148 u16 val)
1149 {
1150 struct rtl838x_switch_priv *priv = bus->priv;
1151
1152 return dsa_phy_write(priv->ds, addr, regnum, val);
1153 }
1154
1155 static void rtl838x_enable_phy_polling(struct rtl838x_switch_priv *priv)
1156 {
1157 int i;
1158 u64 v = 0;
1159
1160 msleep(1000);
1161 /* Enable all ports with a PHY, including the SFP-ports */
1162 for (i = 0; i < priv->cpu_port; i++) {
1163 if (priv->ports[i].phy)
1164 v |= 1 << i;
1165 }
1166
1167 pr_info("%s: %16llx\n", __func__, v);
1168 priv->r->set_port_reg_le(v, priv->r->smi_poll_ctrl);
1169
1170 /* PHY update complete */
1171 if (priv->family_id == RTL8390_FAMILY_ID)
1172 sw_w32_mask(0, 1 << 7, RTL839X_SMI_GLB_CTRL);
1173 else
1174 sw_w32_mask(0, 0x8000, RTL838X_SMI_GLB_CTRL);
1175 }
1176
1177 void rtl839x_print_matrix(void)
1178 {
1179 volatile u64 *ptr = RTL838X_SW_BASE + RTL839X_PORT_ISO_CTRL(0);
1180 int i;
1181
1182 for (i = 0; i < 52; i += 4)
1183 pr_info("> %16llx %16llx %16llx %16llx\n",
1184 ptr[i + 0], ptr[i + 1], ptr[i + 2], ptr[i + 3]);
1185 pr_info("CPU_PORT> %16llx\n", ptr[52]);
1186 }
1187
1188 void rtl838x_print_matrix(void)
1189 {
1190 unsigned volatile int *ptr = RTL838X_SW_BASE + RTL838X_PORT_ISO_CTRL(0);
1191 int i;
1192
1193 if (soc_info.family == RTL8390_FAMILY_ID)
1194 return rtl839x_print_matrix();
1195
1196 for (i = 0; i < 28; i += 8)
1197 pr_info("> %8x %8x %8x %8x %8x %8x %8x %8x\n",
1198 ptr[i + 0], ptr[i + 1], ptr[i + 2], ptr[i + 3], ptr[i + 4], ptr[i + 5],
1199 ptr[i + 6], ptr[i + 7]);
1200 pr_info("CPU_PORT> %8x\n", ptr[28]);
1201 }
1202
1203 static void rtl838x_init_stats(struct rtl838x_switch_priv *priv)
1204 {
1205 mutex_lock(&priv->reg_mutex);
1206
1207 /* Enable statistics module: all counters plus debug.
1208 * On RTL839x all counters are enabled by default
1209 */
1210 if (priv->family_id == RTL8380_FAMILY_ID)
1211 sw_w32_mask(0, 3, RTL838X_STAT_CTRL);
1212
1213 /* Reset statistics counters */
1214 sw_w32_mask(0, 1, priv->r->stat_rst);
1215
1216 mutex_unlock(&priv->reg_mutex);
1217 }
1218
1219 static int rtl838x_setup(struct dsa_switch *ds)
1220 {
1221 int i;
1222 struct rtl838x_switch_priv *priv = ds->priv;
1223 u64 port_bitmap = 1ULL << priv->cpu_port;
1224
1225 pr_info("%s called\n", __func__);
1226
1227 /* Disable MAC polling the PHY so that we can start configuration */
1228 priv->r->set_port_reg_le(0ULL, priv->r->smi_poll_ctrl);
1229
1230 for (i = 0; i < ds->num_ports; i++)
1231 priv->ports[i].enable = false;
1232 priv->ports[priv->cpu_port].enable = true;
1233
1234 /* Isolate ports from each other: traffic only CPU <-> port */
1235 /* Setting bit j in register RTL838X_PORT_ISO_CTRL(i) allows
1236 * traffic from source port i to destination port j
1237 */
1238 for (i = 0; i < priv->cpu_port; i++) {
1239 if (priv->ports[i].phy) {
1240 priv->r->set_port_reg_be(1ULL << priv->cpu_port | 1ULL << i,
1241 priv->r->port_iso_ctrl(i));
1242 port_bitmap |= 1ULL << i;
1243 }
1244 }
1245 priv->r->set_port_reg_be(port_bitmap, priv->r->port_iso_ctrl(priv->cpu_port));
1246
1247 rtl838x_print_matrix();
1248
1249 rtl838x_init_stats(priv);
1250
1251 /* Enable MAC Polling PHY again */
1252 rtl838x_enable_phy_polling(priv);
1253 pr_info("Please wait until PHY is settled\n");
1254 msleep(1000);
1255 return 0;
1256 }
1257
1258 static void rtl838x_get_strings(struct dsa_switch *ds,
1259 int port, u32 stringset, u8 *data)
1260 {
1261 int i;
1262
1263 if (stringset != ETH_SS_STATS)
1264 return;
1265
1266 for (i = 0; i < ARRAY_SIZE(rtl838x_mib); i++)
1267 strncpy(data + i * ETH_GSTRING_LEN, rtl838x_mib[i].name,
1268 ETH_GSTRING_LEN);
1269 }
1270
1271 static void rtl838x_get_ethtool_stats(struct dsa_switch *ds, int port,
1272 uint64_t *data)
1273 {
1274 struct rtl838x_switch_priv *priv = ds->priv;
1275 const struct rtl838x_mib_desc *mib;
1276 int i;
1277 u64 high;
1278
1279 for (i = 0; i < ARRAY_SIZE(rtl838x_mib); i++) {
1280 mib = &rtl838x_mib[i];
1281
1282 data[i] = sw_r32(priv->r->stat_port_std_mib(port) + 252 - mib->offset);
1283 if (mib->size == 2) {
1284 high = sw_r32(priv->r->stat_port_std_mib(port) + 252 - mib->offset - 4);
1285 data[i] |= high << 32;
1286 }
1287 }
1288 }
1289
1290 static int rtl838x_get_sset_count(struct dsa_switch *ds, int port, int sset)
1291 {
1292 if (sset != ETH_SS_STATS)
1293 return 0;
1294
1295 return ARRAY_SIZE(rtl838x_mib);
1296 }
1297
1298 static enum dsa_tag_protocol
1299 rtl838x_get_tag_protocol(struct dsa_switch *ds, int port)
1300 {
1301 /* The switch does not tag the frames, instead internally the header
1302 * structure for each packet is tagged accordingly.
1303 */
1304 return DSA_TAG_PROTO_TRAILER;
1305 }
1306
1307 static int rtl838x_get_l2aging(struct rtl838x_switch_priv *priv)
1308 {
1309 int t = sw_r32(priv->r->l2_ctrl_1);
1310
1311 t &= priv->family_id == RTL8380_FAMILY_ID ? 0x7fffff : 0x1FFFFF;
1312
1313 if (priv->family_id == RTL8380_FAMILY_ID)
1314 t = t * 128 / 625; /* Aging time in seconds. 0: L2 aging disabled */
1315 else
1316 t = (t * 3) / 5;
1317
1318 pr_info("L2 AGING time: %d sec\n", t);
1319 pr_info("Dynamic aging for ports: %x\n", sw_r32(priv->r->l2_port_aging_out));
1320 return t;
1321 }
1322
1323 /*
1324 * Set Switch L2 Aging time, t is time in milliseconds
1325 * t = 0: aging is disabled
1326 */
1327 static int rtl838x_set_l2aging(struct dsa_switch *ds, u32 t)
1328 {
1329 struct rtl838x_switch_priv *priv = ds->priv;
1330 int t_max = priv->family_id == RTL8380_FAMILY_ID ? 0x7fffff : 0x1FFFFF;
1331
1332 /* Convert time in mseconds to internal value */
1333 if (t > 0x10000000) { /* Set to maximum */
1334 t = t_max;
1335 } else {
1336 if (priv->family_id == RTL8380_FAMILY_ID)
1337 t = ((t * 625) / 1000 + 127) / 128;
1338 else
1339 t = (t * 5 + 2) / 3;
1340 }
1341 sw_w32(t, priv->r->l2_ctrl_1);
1342 return 0;
1343 }
1344
1345 static void rtl838x_fast_age(struct dsa_switch *ds, int port)
1346 {
1347 struct rtl838x_switch_priv *priv = ds->priv;
1348 int s = priv->family_id == RTL8390_FAMILY_ID ? 2 : 0;
1349
1350 pr_info("FAST AGE port %d\n", port);
1351 mutex_lock(&priv->reg_mutex);
1352 /* RTL838X_L2_TBL_FLUSH_CTRL register bits, 839x has 1 bit larger
1353 * port fields:
1354 * 0-4: Replacing port
1355 * 5-9: Flushed/replaced port
1356 * 10-21: FVID
1357 * 22: Entry types: 1: dynamic, 0: also static
1358 * 23: Match flush port
1359 * 24: Match FVID
1360 * 25: Flush (0) or replace (1) L2 entries
1361 * 26: Status of action (1: Start, 0: Done)
1362 */
1363 sw_w32(1 << (26 + s) | 1 << (23 + s) | port << (5 + (s / 2)), priv->r->l2_tbl_flush_ctrl);
1364
1365 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & (1 << (26 + s)));
1366
1367 mutex_unlock(&priv->reg_mutex);
1368 }
1369
1370 /*
1371 * Applies the same hash algorithm as the one used currently by the ASIC
1372 */
1373 static u32 rtl838x_hash(struct rtl838x_switch_priv *priv, u64 seed)
1374 {
1375 u32 h1, h2, h3, h;
1376
1377 if (sw_r32(priv->r->l2_ctrl_0) & 1) {
1378 h1 = (seed >> 11) & 0x7ff;
1379 h1 = ((h1 & 0x1f) << 6) | ((h1 >> 5) & 0x3f);
1380
1381 h2 = (seed >> 33) & 0x7ff;
1382 h2 = ((h2 & 0x3f) << 5) | ((h2 >> 6) & 0x1f);
1383
1384 h3 = (seed >> 44) & 0x7ff;
1385 h3 = ((h3 & 0x7f) << 4) | ((h3 >> 7) & 0xf);
1386
1387 h = h1 ^ h2 ^ h3 ^ ((seed >> 55) & 0x1ff);
1388 h ^= ((seed >> 22) & 0x7ff) ^ (seed & 0x7ff);
1389 } else {
1390 h = ((seed >> 55) & 0x1ff) ^ ((seed >> 44) & 0x7ff)
1391 ^ ((seed >> 33) & 0x7ff) ^ ((seed >> 22) & 0x7ff)
1392 ^ ((seed >> 11) & 0x7ff) ^ (seed & 0x7ff);
1393 }
1394
1395 return h;
1396 }
1397
1398 static u32 rtl839x_hash(struct rtl838x_switch_priv *priv, u64 seed)
1399 {
1400 u32 h1, h2, h;
1401
1402 if (sw_r32(priv->r->l2_ctrl_0) & 1) {
1403 h1 = (u32) (((seed >> 60) & 0x3f) ^ ((seed >> 54) & 0x3f)
1404 ^ ((seed >> 36) & 0x3f) ^ ((seed >> 30) & 0x3f)
1405 ^ ((seed >> 12) & 0x3f) ^ ((seed >> 6) & 0x3f));
1406 h2 = (u32) (((seed >> 48) & 0x3f) ^ ((seed >> 42) & 0x3f)
1407 ^ ((seed >> 24) & 0x3f) ^ ((seed >> 18) & 0x3f)
1408 ^ (seed & 0x3f));
1409 h = (h1 << 6) | h2;
1410 } else {
1411 h = (seed >> 60)
1412 ^ ((((seed >> 48) & 0x3f) << 6) | ((seed >> 54) & 0x3f))
1413 ^ ((seed >> 36) & 0xfff) ^ ((seed >> 24) & 0xfff)
1414 ^ ((seed >> 12) & 0xfff) ^ (seed & 0xfff);
1415 }
1416
1417 return h;
1418 }
1419
1420 static u64 rtl838x_hash_key(struct rtl838x_switch_priv *priv, u64 mac, u32 vid)
1421 {
1422 if (priv->family_id == RTL8380_FAMILY_ID)
1423 return rtl838x_hash(priv, mac << 12 | vid);
1424 else
1425 return rtl839x_hash(priv, mac << 12 | vid);
1426 }
1427
1428 static void rtl838x_write_cam(int idx, u32 *r)
1429 {
1430 u32 cmd = 1 << 16 /* Execute cmd */
1431 | 1 << 15 /* Read */
1432 | 1 << 13 /* Table type 0b01 */
1433 | (idx & 0x3f);
1434
1435 sw_w32(r[0], RTL838X_TBL_ACCESS_L2_DATA(0));
1436 sw_w32(r[1], RTL838X_TBL_ACCESS_L2_DATA(1));
1437 sw_w32(r[2], RTL838X_TBL_ACCESS_L2_DATA(2));
1438
1439 sw_w32(cmd, RTL838X_TBL_ACCESS_L2_CTRL);
1440 do { } while (sw_r32(RTL838X_TBL_ACCESS_L2_CTRL) & (1 << 16));
1441 }
1442
1443 static void rtl838x_write_hash(int idx, u32 *r)
1444 {
1445 u32 cmd = 1 << 16 /* Execute cmd */
1446 | 0 << 15 /* Write */
1447 | 0 << 13 /* Table type 0b00 */
1448 | (idx & 0x1fff);
1449
1450 sw_w32(0, RTL838X_TBL_ACCESS_L2_DATA(0));
1451 sw_w32(0, RTL838X_TBL_ACCESS_L2_DATA(1));
1452 sw_w32(0, RTL838X_TBL_ACCESS_L2_DATA(2));
1453 sw_w32(cmd, RTL838X_TBL_ACCESS_L2_CTRL);
1454 do { } while (sw_r32(RTL838X_TBL_ACCESS_L2_CTRL) & (1 << 16));
1455 }
1456
1457 static void dump_fdb(struct rtl838x_switch_priv *priv)
1458 {
1459 struct rtl838x_l2_entry e;
1460 int i;
1461
1462 mutex_lock(&priv->reg_mutex);
1463
1464 for (i = 0; i < priv->fib_entries; i++) {
1465 priv->r->read_l2_entry_using_hash(i >> 2, i & 0x3, &e);
1466
1467 if (!e.valid) /* Check for invalid entry */
1468 continue;
1469
1470 pr_info("-> port %02d: mac %pM, vid: %d, rvid: %d, MC: %d, %d\n",
1471 e.port, &e.mac[0], e.vid, e.rvid, e.is_ip_mc, e.is_ipv6_mc);
1472 }
1473
1474 mutex_unlock(&priv->reg_mutex);
1475 }
1476
1477 static void rtl838x_port_get_stp_state(struct rtl838x_switch_priv *priv, int port)
1478 {
1479 u32 cmd, msti = 0;
1480 u32 port_state[4];
1481 int index, bit, i;
1482 int pos = port;
1483 int n = priv->family_id == RTL8380_FAMILY_ID ? 2 : 4;
1484
1485 /* CPU PORT can only be configured on RTL838x */
1486 if (port >= priv->cpu_port || port > 51)
1487 return;
1488
1489 mutex_lock(&priv->reg_mutex);
1490
1491 /* For the RTL839x, the bits are left-aligned in the 128 bit field */
1492 if (priv->family_id == RTL8390_FAMILY_ID)
1493 pos += 12;
1494
1495 index = n - (pos >> 4) - 1;
1496 bit = (pos << 1) % 32;
1497
1498 if (priv->family_id == RTL8380_FAMILY_ID) {
1499 cmd = 1 << 15 /* Execute cmd */
1500 | 1 << 14 /* Read */
1501 | 2 << 12 /* Table type 0b10 */
1502 | (msti & 0xfff);
1503 } else {
1504 cmd = 1 << 16 /* Execute cmd */
1505 | 0 << 15 /* Read */
1506 | 5 << 12 /* Table type 0b101 */
1507 | (msti & 0xfff);
1508 }
1509 priv->r->exec_tbl0_cmd(cmd);
1510
1511 for (i = 0; i < n; i++)
1512 port_state[i] = sw_r32(priv->r->tbl_access_data_0(i));
1513
1514 mutex_unlock(&priv->reg_mutex);
1515 }
1516
1517 static int rtl838x_port_fdb_dump(struct dsa_switch *ds, int port,
1518 dsa_fdb_dump_cb_t *cb, void *data)
1519 {
1520 struct rtl838x_l2_entry e;
1521 struct rtl838x_switch_priv *priv = ds->priv;
1522 int i;
1523 u32 fid;
1524 u32 pkey;
1525 u64 mac;
1526
1527 mutex_lock(&priv->reg_mutex);
1528
1529 for (i = 0; i < priv->fib_entries; i++) {
1530 priv->r->read_l2_entry_using_hash(i >> 2, i & 0x3, &e);
1531
1532 if (!e.valid)
1533 continue;
1534
1535 if (e.port == port) {
1536 fid = (i & 0x3ff) | (e.rvid & ~0x3ff);
1537 mac = ether_addr_to_u64(&e.mac[0]);
1538 pkey = rtl838x_hash(priv, mac << 12 | fid);
1539 fid = (pkey & 0x3ff) | (fid & ~0x3ff);
1540 pr_info("-> mac %016llx, fid: %d\n", mac, fid);
1541 cb(e.mac, e.vid, e.is_static, data);
1542 }
1543 }
1544
1545 for (i = 0; i < 64; i++) {
1546 priv->r->read_cam(i, &e);
1547
1548 if (!e.valid)
1549 continue;
1550
1551 if (e.port == port)
1552 cb(e.mac, e.vid, e.is_static, data);
1553 }
1554
1555 mutex_unlock(&priv->reg_mutex);
1556 return 0;
1557 }
1558
1559 static int rtl838x_port_fdb_del(struct dsa_switch *ds, int port,
1560 const unsigned char *addr, u16 vid)
1561 {
1562 struct rtl838x_switch_priv *priv = ds->priv;
1563 u64 mac = ether_addr_to_u64(addr);
1564 u32 key = rtl838x_hash_key(priv, mac, vid);
1565 struct rtl838x_l2_entry e;
1566 u32 r[3];
1567 u64 entry;
1568 int idx = -1, err = 0, i;
1569
1570 pr_info("In %s, mac %llx, vid: %d, key: %x\n", __func__, mac, vid, key);
1571 mutex_lock(&priv->reg_mutex);
1572 for (i = 0; i < 4; i++) {
1573 entry = priv->r->read_l2_entry_using_hash(key, i, &e);
1574 if (!e.valid)
1575 continue;
1576 if ((entry & 0x0fffffffffffffffULL) == ((mac << 12) | vid)) {
1577 idx = (key << 2) | i;
1578 break;
1579 }
1580 }
1581
1582 if (idx >= 0) {
1583 r[0] = r[1] = r[2] = 0;
1584 rtl838x_write_hash(idx, r);
1585 goto out;
1586 }
1587
1588 /* Check CAM for spillover from hash buckets */
1589 for (i = 0; i < 64; i++) {
1590 entry = priv->r->read_cam(i, &e);
1591 if ((entry & 0x0fffffffffffffffULL) == ((mac << 12) | vid)) {
1592 idx = i;
1593 break;
1594 }
1595 }
1596 if (idx >= 0) {
1597 r[0] = r[1] = r[2] = 0;
1598 rtl838x_write_cam(idx, r);
1599 goto out;
1600 }
1601 err = -ENOENT;
1602 out:
1603 mutex_unlock(&priv->reg_mutex);
1604 return err;
1605 }
1606
1607 static int rtl838x_port_fdb_add(struct dsa_switch *ds, int port,
1608 const unsigned char *addr, u16 vid)
1609 {
1610 struct rtl838x_switch_priv *priv = ds->priv;
1611 u64 mac = ether_addr_to_u64(addr);
1612 u32 key = rtl838x_hash_key(priv, mac, vid);
1613 struct rtl838x_l2_entry e;
1614 u32 r[3];
1615 u64 entry;
1616 int idx = -1, err = 0, i;
1617
1618 mutex_lock(&priv->reg_mutex);
1619 for (i = 0; i < 4; i++) {
1620 entry = priv->r->read_l2_entry_using_hash(key, i, &e);
1621 if (!e.valid) {
1622 idx = (key << 2) | i;
1623 break;
1624 }
1625 if ((entry & 0x0fffffffffffffffULL) == ((mac << 12) | vid)) {
1626 idx = (key << 2) | i;
1627 break;
1628 }
1629 }
1630 if (idx >= 0) {
1631 r[0] = 3 << 17 | port << 12; // Aging and port
1632 r[0] |= vid;
1633 r[1] = mac >> 16;
1634 r[2] = (mac & 0xffff) << 12; /* rvid = 0 */
1635 rtl838x_write_hash(idx, r);
1636 goto out;
1637 }
1638
1639 /* Hash buckets full, try CAM */
1640 for (i = 0; i < 64; i++) {
1641 entry = rtl838x_read_cam(i, &e);
1642 if (!e.valid) {
1643 if (idx < 0) /* First empty entry? */
1644 idx = i;
1645 break;
1646 } else if ((entry & 0x0fffffffffffffffULL) == ((mac << 12) | vid)) {
1647 pr_debug("Found entry in CAM\n");
1648 idx = i;
1649 break;
1650 }
1651 }
1652 if (idx >= 0) {
1653 r[0] = 3 << 17 | port << 12; // Aging
1654 r[0] |= vid;
1655 r[1] = mac >> 16;
1656 r[2] = (mac & 0xffff) << 12; /* rvid = 0 */
1657 rtl838x_write_cam(idx, r);
1658 goto out;
1659 }
1660 err = -ENOTSUPP;
1661 out:
1662 mutex_unlock(&priv->reg_mutex);
1663 return err;
1664 }
1665
1666 static void rtl838x_port_stp_state_set(struct dsa_switch *ds, int port,
1667 u8 state)
1668 {
1669 u32 cmd, msti = 0;
1670 u32 port_state[4];
1671 int index, bit, i;
1672 int pos = port;
1673 struct rtl838x_switch_priv *priv = ds->priv;
1674 int n = priv->family_id == RTL8380_FAMILY_ID ? 2 : 4;
1675
1676 pr_info("%s: port %d state %2x\n", __func__, port, state);
1677
1678 /* CPU PORT can only be configured on RTL838x */
1679 if (port >= priv->cpu_port || port > 51)
1680 return;
1681
1682 mutex_lock(&priv->reg_mutex);
1683
1684 /* For the RTL839x, the bits are left-aligned in the 128 bit field */
1685 if (priv->family_id == RTL8390_FAMILY_ID)
1686 pos += 12;
1687
1688 index = n - (pos >> 4) - 1;
1689 bit = (pos << 1) % 32;
1690
1691 if (priv->family_id == RTL8380_FAMILY_ID) {
1692 cmd = 1 << 15 /* Execute cmd */
1693 | 1 << 14 /* Read */
1694 | 2 << 12 /* Table type 0b10 */
1695 | (msti & 0xfff);
1696 } else {
1697 cmd = 1 << 16 /* Execute cmd */
1698 | 0 << 15 /* Read */
1699 | 5 << 12 /* Table type 0b101 */
1700 | (msti & 0xfff);
1701 }
1702 priv->r->exec_tbl0_cmd(cmd);
1703
1704 for (i = 0; i < n; i++)
1705 port_state[i] = sw_r32(priv->r->tbl_access_data_0(i));
1706
1707 pr_debug("Current state, port %d: %d\n", port, (port_state[index] >> bit) & 3);
1708 port_state[index] &= ~(3 << bit);
1709
1710 switch (state) {
1711 case BR_STATE_DISABLED: /* 0 */
1712 port_state[index] |= (0 << bit);
1713 break;
1714 case BR_STATE_BLOCKING: /* 4 */
1715 case BR_STATE_LISTENING: /* 1 */
1716 port_state[index] |= (1 << bit);
1717 break;
1718 case BR_STATE_LEARNING: /* 2 */
1719 port_state[index] |= (2 << bit);
1720 break;
1721 case BR_STATE_FORWARDING: /* 3*/
1722 port_state[index] |= (3 << bit);
1723 default:
1724 break;
1725 }
1726
1727 if (priv->family_id == RTL8380_FAMILY_ID) {
1728 cmd = 1 << 15 /* Execute cmd */
1729 | 0 << 14 /* Write */
1730 | 2 << 12 /* Table type 0b10 */
1731 | (msti & 0xfff);
1732 } else {
1733 cmd = 1 << 16 /* Execute cmd */
1734 | 1 << 15 /* Write */
1735 | 5 << 12 /* Table type 0b101 */
1736 | (msti & 0xfff);
1737 }
1738 for (i = 0; i < n; i++)
1739 sw_w32(port_state[i], priv->r->tbl_access_data_0(i));
1740 priv->r->exec_tbl0_cmd(cmd);
1741
1742 mutex_unlock(&priv->reg_mutex);
1743 }
1744
1745 static int rtl838x_port_mirror_add(struct dsa_switch *ds, int port,
1746 struct dsa_mall_mirror_tc_entry *mirror,
1747 bool ingress)
1748 {
1749 /* We support 4 mirror groups, one destination port per group */
1750 int group;
1751 struct rtl838x_switch_priv *priv = ds->priv;
1752
1753 pr_info("In %s\n", __func__);
1754
1755 for (group = 0; group < 4; group++) {
1756 if (priv->mirror_group_ports[group] == mirror->to_local_port)
1757 break;
1758 }
1759 if (group >= 4) {
1760 for (group = 0; group < 4; group++) {
1761 if (priv->mirror_group_ports[group] < 0)
1762 break;
1763 }
1764 }
1765
1766 if (group >= 4)
1767 return -ENOSPC;
1768
1769 pr_debug("Using group %d\n", group);
1770 mutex_lock(&priv->reg_mutex);
1771
1772 if (priv->family_id == RTL8380_FAMILY_ID) {
1773 /* Enable mirroring to port across VLANs (bit 11) */
1774 sw_w32(1 << 11 | (mirror->to_local_port << 4) | 1, RTL838X_MIR_CTRL(group));
1775 } else {
1776 /* Enable mirroring to destination port */
1777 sw_w32((mirror->to_local_port << 4) | 1, RTL839X_MIR_CTRL(group));
1778 }
1779
1780 if (ingress && (priv->r->get_port_reg_be(priv->r->mir_spm(group)) & (1ULL << port))) {
1781 mutex_unlock(&priv->reg_mutex);
1782 return -EEXIST;
1783 }
1784 if ((!ingress) && (priv->r->get_port_reg_be(priv->r->mir_dpm(group)) & (1ULL << port))) {
1785 mutex_unlock(&priv->reg_mutex);
1786 return -EEXIST;
1787 }
1788
1789 if (ingress)
1790 priv->r->mask_port_reg_be(0, 1ULL << port, priv->r->mir_spm(group));
1791 else
1792 priv->r->mask_port_reg_be(0, 1ULL << port, priv->r->mir_dpm(group));
1793
1794 priv->mirror_group_ports[group] = mirror->to_local_port;
1795 mutex_unlock(&priv->reg_mutex);
1796 return 0;
1797 }
1798
1799 static void rtl838x_port_mirror_del(struct dsa_switch *ds, int port,
1800 struct dsa_mall_mirror_tc_entry *mirror)
1801 {
1802 int group = 0;
1803 struct rtl838x_switch_priv *priv = ds->priv;
1804
1805 pr_info("In %s\n", __func__);
1806 for (group = 0; group < 4; group++) {
1807 if (priv->mirror_group_ports[group] == mirror->to_local_port)
1808 break;
1809 }
1810 if (group >= 4)
1811 return;
1812
1813 mutex_lock(&priv->reg_mutex);
1814 if (mirror->ingress) {
1815 /* Ingress, clear source port matrix */
1816 priv->r->mask_port_reg_be(1ULL << port, 0, priv->r->mir_spm(group));
1817 } else {
1818 /* Egress, clear destination port matrix */
1819 priv->r->mask_port_reg_be(1ULL << port, 0, priv->r->mir_dpm(group));
1820 }
1821
1822 if (!(sw_r32(priv->r->mir_spm(group)) || sw_r32(priv->r->mir_dpm(group)))) {
1823 priv->mirror_group_ports[group] = -1;
1824 sw_w32(0, priv->r->mir_ctrl(group));
1825 }
1826
1827 mutex_unlock(&priv->reg_mutex);
1828 }
1829
1830 void rtl838x_vlan_profile_dump(int index)
1831 {
1832 u32 profile;
1833
1834 if (index < 0 || index > 7)
1835 return;
1836
1837 profile = sw_r32(rtl838x_vlan_profile(index));
1838
1839 pr_info("VLAN %d: L2 learning: %d, L2 Unknown MultiCast Field %x, \
1840 IPv4 Unknown MultiCast Field %x, IPv6 Unknown MultiCast Field: %x",
1841 index, profile & 1, (profile >> 1) & 0x1ff, (profile >> 10) & 0x1ff,
1842 (profile >> 19) & 0x1ff);
1843 }
1844
1845 void rtl839x_vlan_profile_dump(int index)
1846 {
1847 u32 profile, profile1;
1848
1849 if (index < 0 || index > 7)
1850 return;
1851
1852 profile1 = sw_r32(rtl839x_vlan_profile(index) + 4);
1853 profile = sw_r32(rtl839x_vlan_profile(index));
1854
1855 pr_info("VLAN %d: L2 learning: %d, L2 Unknown MultiCast Field %x, \
1856 IPv4 Unknown MultiCast Field %x, IPv6 Unknown MultiCast Field: %x",
1857 index, profile & 1, (profile >> 1) & 0xfff, (profile >> 13) & 0xfff,
1858 (profile1) & 0xfff);
1859 }
1860
1861 static int rtl838x_vlan_filtering(struct dsa_switch *ds, int port,
1862 bool vlan_filtering)
1863 {
1864 struct rtl838x_switch_priv *priv = ds->priv;
1865
1866 pr_info("%s: port %d\n", __func__, port);
1867 mutex_lock(&priv->reg_mutex);
1868
1869 if (vlan_filtering) {
1870 /* Enable ingress and egress filtering */
1871 if (port != priv->cpu_port)
1872 sw_w32_mask(0b10 << ((port % 16) << 1), 0b01 << ((port % 16) << 1),
1873 priv->r->vlan_port_igr_filter(port));
1874 sw_w32_mask(0, 1 << (port % 32), priv->r->vlan_port_egr_filter(port));
1875 } else {
1876 /* Disable ingress and egress filtering */
1877 if (port != priv->cpu_port)
1878 sw_w32_mask(0b11 << ((port % 16) << 1), 0,
1879 priv->r->vlan_port_igr_filter(port));
1880 sw_w32_mask(1 << (port % 32), 0, priv->r->vlan_port_egr_filter(port));
1881 }
1882
1883 /* Do we need to do something to the CPU-Port, too? */
1884 mutex_unlock(&priv->reg_mutex);
1885
1886 return 0;
1887 }
1888
1889 static int rtl838x_vlan_prepare(struct dsa_switch *ds, int port,
1890 const struct switchdev_obj_port_vlan *vlan)
1891 {
1892 struct rtl838x_vlan_info info;
1893 struct rtl838x_switch_priv *priv = ds->priv;
1894
1895 pr_info("%s: port %d\n", __func__, port);
1896
1897 mutex_lock(&priv->reg_mutex);
1898
1899 if (priv->family_id == RTL8380_FAMILY_ID)
1900 rtl839x_vlan_profile_dump(0);
1901 else
1902 rtl839x_vlan_profile_dump(0);
1903
1904 priv->r->vlan_tables_read(0, &info);
1905
1906 pr_info("Tagged ports %llx, untag %llx, prof %x, MC# %d, UC# %d, FID %x\n",
1907 info.tagged_ports, info.untagged_ports, info.profile_id,
1908 info.hash_mc, info.hash_uc, info.fid);
1909
1910 mutex_unlock(&priv->reg_mutex);
1911 return 0;
1912 }
1913
1914 static void rtl838x_vlan_add(struct dsa_switch *ds, int port,
1915 const struct switchdev_obj_port_vlan *vlan)
1916 {
1917 struct rtl838x_vlan_info info;
1918 struct rtl838x_switch_priv *priv = ds->priv;
1919 int v;
1920 u64 portmask;
1921
1922 pr_info("%s port %d, vid_end %d, vid_end %d, flags %x\n", __func__,
1923 port, vlan->vid_begin, vlan->vid_end, vlan->flags);
1924
1925 if (vlan->vid_begin > 4095 || vlan->vid_end > 4095) {
1926 dev_err(priv->dev, "VLAN out of range: %d - %d",
1927 vlan->vid_begin, vlan->vid_end);
1928 return;
1929 }
1930
1931 mutex_lock(&priv->reg_mutex);
1932
1933 if (vlan->flags & BRIDGE_VLAN_INFO_PVID) {
1934 for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
1935 /* Set both inner and outer PVID of the port */
1936 sw_w32((v << 16) | v, priv->r->vlan_port_pb(port));
1937 }
1938 }
1939
1940 if (vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED) {
1941 for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
1942 /* Get untagged port memberships of this vlan */
1943 priv->r->vlan_tables_read(v, &info);
1944 portmask = info.untagged_ports | (1 << port);
1945 pr_debug("Untagged ports, VLAN %d: %llx\n", v, portmask);
1946 priv->r->vlan_set_untagged(v, portmask);
1947 }
1948 } else {
1949 for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
1950 /* Get tagged port memberships of this vlan */
1951 priv->r->vlan_tables_read(v, &info);
1952 info.tagged_ports |= (1 << port);
1953 pr_debug("Tagged ports, VLAN %d: %llx\n", v, info.tagged_ports);
1954 priv->r->vlan_set_tagged(v, &info);
1955 }
1956 }
1957
1958 mutex_unlock(&priv->reg_mutex);
1959 }
1960
1961 static int rtl838x_vlan_del(struct dsa_switch *ds, int port,
1962 const struct switchdev_obj_port_vlan *vlan)
1963 {
1964 struct rtl838x_vlan_info info;
1965 struct rtl838x_switch_priv *priv = ds->priv;
1966 int v;
1967 u64 portmask;
1968
1969 pr_info("%s: port %d, vid_end %d, vid_end %d, flags %x\n", __func__,
1970 port, vlan->vid_begin, vlan->vid_end, vlan->flags);
1971
1972 if (vlan->vid_begin > 4095 || vlan->vid_end > 4095) {
1973 dev_err(priv->dev, "VLAN out of range: %d - %d",
1974 vlan->vid_begin, vlan->vid_end);
1975 return -ENOTSUPP;
1976 }
1977
1978 mutex_lock(&priv->reg_mutex);
1979
1980 for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
1981 /* Reset both inner and out PVID of the port */
1982 sw_w32(0, priv->r->vlan_port_pb(port));
1983
1984 if (vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED) {
1985 /* Get untagged port memberships of this vlan */
1986 priv->r->vlan_tables_read(v, &info);
1987 portmask = info.untagged_ports & (~(1ULL << port));
1988 pr_info("Untagged ports, VLAN %d: %llx\n", v, portmask);
1989 priv->r->vlan_set_untagged(v, portmask);
1990 }
1991
1992 /* Get tagged port memberships of this vlan */
1993 priv->r->vlan_tables_read(v, &info);
1994 info.tagged_ports &= (~(1ULL << port));
1995 pr_info("Tagged ports, VLAN %d: %llx\n", v, info.tagged_ports);
1996 priv->r->vlan_set_tagged(v, &info);
1997 }
1998 mutex_unlock(&priv->reg_mutex);
1999
2000 return 0;
2001 }
2002
2003 static void rtl838x_port_bridge_leave(struct dsa_switch *ds, int port,
2004 struct net_device *bridge)
2005 {
2006 struct rtl838x_switch_priv *priv = ds->priv;
2007 u64 port_bitmap = 1ULL << priv->cpu_port;
2008 int i;
2009
2010 pr_info("%s %x: %d", __func__, (u32)priv, port);
2011 mutex_lock(&priv->reg_mutex);
2012 for (i = 0; i < ds->num_ports; i++) {
2013 /* Remove this port from the port matrix of the other ports
2014 * in the same bridge. If the port is disabled, port matrix
2015 * is kept and not being setup until the port becomes enabled.
2016 * And the other port's port matrix cannot be broken when the
2017 * other port is still a VLAN-aware port.
2018 */
2019 if (dsa_is_user_port(ds, i) && i != port) {
2020 if (dsa_to_port(ds, i)->bridge_dev != bridge)
2021 continue;
2022 if (priv->ports[i].enable)
2023 priv->r->mask_port_reg_be(1ULL << port, 0,
2024 priv->r->port_iso_ctrl(i));
2025 priv->ports[i].pm |= 1ULL << port;
2026
2027 port_bitmap &= ~(1ULL << i);
2028 }
2029 }
2030
2031 /* Add all other ports to this port matrix. */
2032 if (priv->ports[port].enable)
2033 priv->r->mask_port_reg_be(0, port_bitmap, priv->r->port_iso_ctrl(port));
2034 priv->ports[port].pm &= ~port_bitmap;
2035 mutex_unlock(&priv->reg_mutex);
2036 }
2037
2038 static int rtl838x_port_bridge_join(struct dsa_switch *ds, int port,
2039 struct net_device *bridge)
2040 {
2041 struct rtl838x_switch_priv *priv = ds->priv;
2042 u64 port_bitmap = 1ULL << priv->cpu_port;
2043 int i;
2044
2045 pr_info("%s %x: %d %llx", __func__, (u32)priv, port, port_bitmap);
2046 mutex_lock(&priv->reg_mutex);
2047 for (i = 0; i < ds->num_ports; i++) {
2048 /* Add this port to the port matrix of the other ports in the
2049 * same bridge. If the port is disabled, port matrix is kept
2050 * and not being setup until the port becomes enabled.
2051 */
2052 if (dsa_is_user_port(ds, i) && i != port) {
2053 if (dsa_to_port(ds, i)->bridge_dev != bridge)
2054 continue;
2055 if (priv->ports[i].enable)
2056 priv->r->mask_port_reg_be(0, 1ULL << port,
2057 priv->r->port_iso_ctrl(i));
2058 priv->ports[i].pm |= 1ULL << port;
2059
2060 port_bitmap |= 1ULL << i;
2061 }
2062 }
2063
2064 /* Add all other ports to this port matrix. */
2065 if (priv->ports[port].enable) {
2066 priv->r->mask_port_reg_be(0, 1ULL << port,
2067 priv->r->port_iso_ctrl(priv->cpu_port));
2068 priv->r->mask_port_reg_be(0, port_bitmap,
2069 priv->r->port_iso_ctrl(port));
2070 }
2071 priv->ports[port].pm |= port_bitmap;
2072 mutex_unlock(&priv->reg_mutex);
2073
2074 return 0;
2075 }
2076
2077 static int rtl838x_port_enable(struct dsa_switch *ds, int port,
2078 struct phy_device *phydev)
2079 {
2080 struct rtl838x_switch_priv *priv = ds->priv;
2081
2082 pr_info("%s: %x %d", __func__, (u32) priv, port);
2083 priv->ports[port].enable = true;
2084
2085 if (dsa_is_cpu_port(ds, port))
2086 return 0;
2087
2088 /* add port to switch mask of CPU_PORT */
2089 priv->r->mask_port_reg_be(0, 1ULL << port, priv->r->port_iso_ctrl(priv->cpu_port));
2090
2091 /* add all other ports in the same bridge to switch mask of port */
2092 priv->r->mask_port_reg_be(0, priv->ports[port].pm, priv->r->port_iso_ctrl(port));
2093
2094 return 0;
2095 }
2096
2097 static void rtl838x_port_disable(struct dsa_switch *ds, int port)
2098 {
2099 struct rtl838x_switch_priv *priv = ds->priv;
2100
2101 pr_info("%s %x: %d", __func__, (u32)priv, port);
2102 /* you can only disable user ports */
2103 if (!dsa_is_user_port(ds, port))
2104 return;
2105
2106 /* remove port from switch mask of CPU_PORT */
2107 priv->r->mask_port_reg_be(1ULL << port, 0, priv->r->port_iso_ctrl(priv->cpu_port));
2108
2109 /* remove all other ports in the same bridge from switch mask of port */
2110 priv->r->mask_port_reg_be(priv->ports[port].pm, 0LL, priv->r->port_iso_ctrl(port));
2111
2112 priv->ports[port].enable = false;
2113 }
2114
2115 static int rtl838x_get_mac_eee(struct dsa_switch *ds, int port,
2116 struct ethtool_eee *e)
2117 {
2118 struct rtl838x_switch_priv *priv = ds->priv;
2119
2120 pr_info("%s: port %d", __func__, port);
2121 e->supported = SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full;
2122 if (sw_r32(priv->r->mac_force_mode_ctrl(port)) & (1 << 9))
2123 e->advertised |= ADVERTISED_100baseT_Full;
2124
2125 if (sw_r32(priv->r->mac_force_mode_ctrl(port)) & (1 << 10))
2126 e->advertised |= ADVERTISED_1000baseT_Full;
2127
2128 e->eee_enabled = priv->ports[port].eee_enabled;
2129 pr_info("enabled: %d, active %x\n", e->eee_enabled, e->advertised);
2130
2131 if (sw_r32(RTL838X_MAC_EEE_ABLTY) & (1 << port)) {
2132 e->lp_advertised = ADVERTISED_100baseT_Full;
2133 e->lp_advertised |= ADVERTISED_1000baseT_Full;
2134 }
2135
2136 e->eee_active = !!(e->advertised & e->lp_advertised);
2137 pr_info("active: %d, lp %x\n", e->eee_active, e->lp_advertised);
2138
2139 return 0;
2140 }
2141
2142 static int rtl838x_set_mac_eee(struct dsa_switch *ds, int port,
2143 struct ethtool_eee *e)
2144 {
2145 struct rtl838x_switch_priv *priv = ds->priv;
2146
2147 pr_info("%s: port %d", __func__, port);
2148 if (e->eee_enabled) {
2149 pr_info("Globally enabling EEE\n");
2150 sw_w32_mask(0x4, 0, RTL838X_SMI_GLB_CTRL);
2151 }
2152 if (e->eee_enabled) {
2153 pr_info("Enabling EEE for MAC %d\n", port);
2154 sw_w32_mask(0, 3 << 9, priv->r->mac_force_mode_ctrl(port));
2155 sw_w32_mask(0, 1 << port, RTL838X_EEE_PORT_TX_EN);
2156 sw_w32_mask(0, 1 << port, RTL838X_EEE_PORT_RX_EN);
2157 priv->ports[port].eee_enabled = true;
2158 e->eee_enabled = true;
2159 } else {
2160 pr_info("Disabling EEE for MAC %d\n", port);
2161 sw_w32_mask(3 << 9, 0, priv->r->mac_force_mode_ctrl(port));
2162 sw_w32_mask(1 << port, 0, RTL838X_EEE_PORT_TX_EN);
2163 sw_w32_mask(1 << port, 0, RTL838X_EEE_PORT_RX_EN);
2164 priv->ports[port].eee_enabled = false;
2165 e->eee_enabled = false;
2166 }
2167 return 0;
2168 }
2169
2170 static void rtl838x_phylink_mac_config(struct dsa_switch *ds, int port,
2171 unsigned int mode,
2172 const struct phylink_link_state *state)
2173 {
2174 struct rtl838x_switch_priv *priv = ds->priv;
2175 u32 reg;
2176 int speed_bit = priv->family_id == RTL8380_FAMILY_ID ? 4 : 3;
2177
2178 pr_info("%s port %d, mode %x\n", __func__, port, mode);
2179
2180 if (port == priv->cpu_port) {
2181 /* Set Speed, duplex, flow control
2182 * FORCE_EN | LINK_EN | NWAY_EN | DUP_SEL
2183 * | SPD_SEL = 0b10 | FORCE_FC_EN | PHY_MASTER_SLV_MANUAL_EN
2184 * | MEDIA_SEL
2185 */
2186 if (priv->family_id == RTL8380_FAMILY_ID) {
2187 sw_w32(0x6192F, priv->r->mac_force_mode_ctrl(priv->cpu_port));
2188 /* allow CRC errors on CPU-port */
2189 sw_w32_mask(0, 0x8, RTL838X_MAC_PORT_CTRL(priv->cpu_port));
2190 } else {
2191 sw_w32_mask(0, 3, priv->r->mac_force_mode_ctrl(priv->cpu_port));
2192 }
2193 return;
2194 }
2195
2196 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
2197 /* Auto-Negotiation does not work for MAC in RTL8390 */
2198 if (priv->family_id == RTL8380_FAMILY_ID) {
2199 if (mode == MLO_AN_PHY) {
2200 pr_info("PHY autonegotiates\n");
2201 reg |= 1 << 2;
2202 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
2203 return;
2204 }
2205 }
2206
2207 if (mode != MLO_AN_FIXED)
2208 pr_info("Fixed state.\n");
2209
2210 if (priv->family_id == RTL8380_FAMILY_ID) {
2211 /* Clear id_mode_dis bit, and the existing port mode, let
2212 * RGMII_MODE_EN bet set by mac_link_{up,down}
2213 */
2214 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN);
2215
2216 if (state->pause & MLO_PAUSE_TXRX_MASK) {
2217 if (state->pause & MLO_PAUSE_TX)
2218 reg |= TX_PAUSE_EN;
2219 reg |= RX_PAUSE_EN;
2220 }
2221 }
2222
2223 reg &= ~(3 << speed_bit);
2224 switch (state->speed) {
2225 case SPEED_1000:
2226 reg |= 2 << speed_bit;
2227 break;
2228 case SPEED_100:
2229 reg |= 1 << speed_bit;
2230 break;
2231 }
2232
2233 if (priv->family_id == RTL8380_FAMILY_ID) {
2234 reg &= ~(DUPLEX_FULL | FORCE_LINK_EN);
2235 if (state->link)
2236 reg |= FORCE_LINK_EN;
2237 if (state->duplex == DUPLEX_FULL)
2238 reg |= DUPLX_MODE;
2239 }
2240
2241 // Disable AN
2242 if (priv->family_id == RTL8380_FAMILY_ID)
2243 reg &= ~(1 << 2);
2244 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
2245 }
2246
2247 static void rtl838x_phylink_mac_link_down(struct dsa_switch *ds, int port,
2248 unsigned int mode,
2249 phy_interface_t interface)
2250 {
2251 struct rtl838x_switch_priv *priv = ds->priv;
2252 /* Stop TX/RX to port */
2253 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(port));
2254 }
2255
2256 static void rtl838x_phylink_mac_link_up(struct dsa_switch *ds, int port,
2257 unsigned int mode,
2258 phy_interface_t interface,
2259 struct phy_device *phydev)
2260 {
2261 struct rtl838x_switch_priv *priv = ds->priv;
2262 /* Restart TX/RX to port */
2263 sw_w32_mask(0, 0x3, priv->r->mac_port_ctrl(port));
2264 }
2265
2266 static void rtl838x_phylink_validate(struct dsa_switch *ds, int port,
2267 unsigned long *supported,
2268 struct phylink_link_state *state)
2269 {
2270 struct rtl838x_switch_priv *priv = ds->priv;
2271 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
2272
2273 pr_info("In %s port %d", __func__, port);
2274
2275 if (!phy_interface_mode_is_rgmii(state->interface) &&
2276 state->interface != PHY_INTERFACE_MODE_1000BASEX &&
2277 state->interface != PHY_INTERFACE_MODE_MII &&
2278 state->interface != PHY_INTERFACE_MODE_REVMII &&
2279 state->interface != PHY_INTERFACE_MODE_GMII &&
2280 state->interface != PHY_INTERFACE_MODE_QSGMII &&
2281 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
2282 state->interface != PHY_INTERFACE_MODE_SGMII) {
2283 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
2284 dev_err(ds->dev,
2285 "Unsupported interface: %d for port %d\n",
2286 state->interface, port);
2287 return;
2288 }
2289
2290 /* Allow all the expected bits */
2291 phylink_set(mask, Autoneg);
2292 phylink_set_port_modes(mask);
2293 phylink_set(mask, Pause);
2294 phylink_set(mask, Asym_Pause);
2295
2296 /* With the exclusion of MII and Reverse MII, we support Gigabit,
2297 * including Half duplex
2298 */
2299 if (state->interface != PHY_INTERFACE_MODE_MII &&
2300 state->interface != PHY_INTERFACE_MODE_REVMII) {
2301 phylink_set(mask, 1000baseT_Full);
2302 phylink_set(mask, 1000baseT_Half);
2303 }
2304
2305 /* On both the 8380 and 8382, ports 24-27 are SFP ports */
2306 if (port >= 24 && port <= 27 && priv->family_id == RTL8380_FAMILY_ID)
2307 phylink_set(mask, 1000baseX_Full);
2308
2309 phylink_set(mask, 10baseT_Half);
2310 phylink_set(mask, 10baseT_Full);
2311 phylink_set(mask, 100baseT_Half);
2312 phylink_set(mask, 100baseT_Full);
2313
2314 bitmap_and(supported, supported, mask,
2315 __ETHTOOL_LINK_MODE_MASK_NBITS);
2316 bitmap_and(state->advertising, state->advertising, mask,
2317 __ETHTOOL_LINK_MODE_MASK_NBITS);
2318 }
2319
2320 static int rtl838x_phylink_mac_link_state(struct dsa_switch *ds, int port,
2321 struct phylink_link_state *state)
2322 {
2323 struct rtl838x_switch_priv *priv = ds->priv;
2324 u64 speed;
2325
2326 if (port < 0 || port > priv->cpu_port)
2327 return -EINVAL;
2328
2329 state->link = 0;
2330 if (priv->r->get_port_reg_le(priv->r->mac_link_sts) & (1ULL << port))
2331 state->link = 1;
2332 state->duplex = 0;
2333 if (priv->r->get_port_reg_le(priv->r->mac_link_dup_sts) & (1ULL << port))
2334 state->duplex = 1;
2335
2336 speed = priv->r->get_port_reg_le(priv->r->mac_link_spd_sts(port));
2337 speed >>= (port % 16) << 1;
2338 switch (speed & 0x3) {
2339 case 0:
2340 state->speed = SPEED_10;
2341 break;
2342 case 1:
2343 state->speed = SPEED_100;
2344 break;
2345 case 2:
2346 state->speed = SPEED_1000;
2347 break;
2348 case 3:
2349 if (port == 24 || port == 26) /* Internal serdes */
2350 state->speed = SPEED_2500;
2351 else
2352 state->speed = SPEED_100; /* Is in fact 500Mbit */
2353 }
2354
2355 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
2356 if (priv->r->get_port_reg_le(priv->r->mac_rx_pause_sts) & (1ULL << port))
2357 state->pause |= MLO_PAUSE_RX;
2358 if (priv->r->get_port_reg_le(priv->r->mac_tx_pause_sts) & (1ULL << port))
2359 state->pause |= MLO_PAUSE_TX;
2360 return 1;
2361 }
2362
2363 static int rtl838x_mdio_probe(struct rtl838x_switch_priv *priv)
2364 {
2365 struct device *dev = priv->dev;
2366 struct device_node *dn, *mii_np = dev->of_node;
2367 struct mii_bus *bus;
2368 int ret;
2369 u32 pn;
2370
2371 pr_info("In %s\n", __func__);
2372 mii_np = of_find_compatible_node(NULL, NULL, "realtek,rtl838x-mdio");
2373 if (mii_np) {
2374 pr_info("Found compatible MDIO node!\n");
2375 } else {
2376 dev_err(priv->dev, "no %s child node found", "mdio-bus");
2377 return -ENODEV;
2378 }
2379
2380 priv->mii_bus = of_mdio_find_bus(mii_np);
2381 if (!priv->mii_bus) {
2382 pr_info("Deferring probe of mdio bus\n");
2383 return -EPROBE_DEFER;
2384 }
2385 if (!of_device_is_available(mii_np))
2386 ret = -ENODEV;
2387
2388 bus = devm_mdiobus_alloc(priv->ds->dev);
2389 if (!bus)
2390 return -ENOMEM;
2391
2392 bus->name = "rtl838x slave mii";
2393 bus->read = &rtl838x_mdio_read;
2394 bus->write = &rtl838x_mdio_write;
2395 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d", bus->name, dev->id);
2396 bus->parent = dev;
2397 priv->ds->slave_mii_bus = bus;
2398 priv->ds->slave_mii_bus->priv = priv;
2399
2400 ret = mdiobus_register(priv->ds->slave_mii_bus);
2401 if (ret && mii_np) {
2402 of_node_put(dn);
2403 return ret;
2404 }
2405
2406 dn = mii_np;
2407 for_each_node_by_name(dn, "ethernet-phy") {
2408 if (of_property_read_u32(dn, "reg", &pn))
2409 continue;
2410
2411 // Check for the integrated SerDes of the RTL8380M first
2412 if (of_property_read_bool(dn, "phy-is-integrated")
2413 && priv->id == 0x8380 && pn >= 24) {
2414 pr_info("----> FÓUND A SERDES\n");
2415 priv->ports[pn].phy = PHY_RTL838X_SDS;
2416 continue;
2417 }
2418
2419 if (of_property_read_bool(dn, "phy-is-integrated")
2420 && !of_property_read_bool(dn, "sfp")) {
2421 priv->ports[pn].phy = PHY_RTL8218B_INT;
2422 continue;
2423 }
2424
2425 if (!of_property_read_bool(dn, "phy-is-integrated")
2426 && of_property_read_bool(dn, "sfp")) {
2427 priv->ports[pn].phy = PHY_RTL8214FC;
2428 continue;
2429 }
2430
2431 if (!of_property_read_bool(dn, "phy-is-integrated")
2432 && !of_property_read_bool(dn, "sfp")) {
2433 priv->ports[pn].phy = PHY_RTL8218B_EXT;
2434 continue;
2435 }
2436 }
2437
2438 /* Disable MAC polling the PHY so that we can start configuration */
2439 priv->r->set_port_reg_le(0ULL, priv->r->smi_poll_ctrl);
2440
2441 /* Enable PHY control via SoC */
2442 if (priv->family_id == RTL8380_FAMILY_ID) {
2443 /* Enable PHY control via SoC */
2444 sw_w32_mask(0, 1 << 15, RTL838X_SMI_GLB_CTRL);
2445 } else {
2446 /* Disable PHY polling via SoC */
2447 sw_w32_mask(1 << 7, 0, RTL839X_SMI_GLB_CTRL);
2448 }
2449
2450 /* Power on fibre ports and reset them if necessary */
2451 if (priv->ports[24].phy == PHY_RTL838X_SDS) {
2452 pr_info("Powering on fibre ports & reset\n");
2453 rtl8380_sds_power(24, 1);
2454 rtl8380_sds_power(26, 1);
2455 }
2456
2457 pr_info("%s done\n", __func__);
2458 return 0;
2459 }
2460
2461 static const struct dsa_switch_ops rtl838x_switch_ops = {
2462 .get_tag_protocol = rtl838x_get_tag_protocol,
2463 .setup = rtl838x_setup,
2464 .port_vlan_filtering = rtl838x_vlan_filtering,
2465 .port_vlan_prepare = rtl838x_vlan_prepare,
2466 .port_vlan_add = rtl838x_vlan_add,
2467 .port_vlan_del = rtl838x_vlan_del,
2468 .port_bridge_join = rtl838x_port_bridge_join,
2469 .port_bridge_leave = rtl838x_port_bridge_leave,
2470 .port_stp_state_set = rtl838x_port_stp_state_set,
2471 .set_ageing_time = rtl838x_set_l2aging,
2472 .port_fast_age = rtl838x_fast_age,
2473 .port_fdb_add = rtl838x_port_fdb_add,
2474 .port_fdb_del = rtl838x_port_fdb_del,
2475 .port_fdb_dump = rtl838x_port_fdb_dump,
2476 .port_enable = rtl838x_port_enable,
2477 .port_disable = rtl838x_port_disable,
2478 .port_mirror_add = rtl838x_port_mirror_add,
2479 .port_mirror_del = rtl838x_port_mirror_del,
2480 .phy_read = dsa_phy_read,
2481 .phy_write = dsa_phy_write,
2482 .get_strings = rtl838x_get_strings,
2483 .get_ethtool_stats = rtl838x_get_ethtool_stats,
2484 .get_sset_count = rtl838x_get_sset_count,
2485 .phylink_validate = rtl838x_phylink_validate,
2486 .phylink_mac_link_state = rtl838x_phylink_mac_link_state,
2487 .phylink_mac_config = rtl838x_phylink_mac_config,
2488 .phylink_mac_link_down = rtl838x_phylink_mac_link_down,
2489 .phylink_mac_link_up = rtl838x_phylink_mac_link_up,
2490 .set_mac_eee = rtl838x_set_mac_eee,
2491 .get_mac_eee = rtl838x_get_mac_eee,
2492 };
2493
2494 static int __init rtl838x_sw_probe(struct platform_device *pdev)
2495 {
2496 int err = 0, i;
2497 struct rtl838x_switch_priv *priv;
2498 struct device *dev = &pdev->dev;
2499 u64 irq_mask;
2500
2501 pr_info("Probing RTL838X switch device\n");
2502 if (!pdev->dev.of_node) {
2503 dev_err(dev, "No DT found\n");
2504 return -EINVAL;
2505 }
2506
2507 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
2508 if (!priv)
2509 return -ENOMEM;
2510
2511 priv->ds = dsa_switch_alloc(dev, DSA_MAX_PORTS);
2512
2513 if (!priv->ds)
2514 return -ENOMEM;
2515 priv->ds->dev = dev;
2516 priv->ds->priv = priv;
2517 priv->ds->ops = &rtl838x_switch_ops;
2518 priv->dev = dev;
2519
2520 priv->family_id = soc_info.family;
2521 priv->id = soc_info.id;
2522 if (soc_info.family == RTL8380_FAMILY_ID) {
2523 priv->cpu_port = RTL838X_CPU_PORT;
2524 priv->port_mask = 0x1f;
2525 priv->r = &rtl838x_reg;
2526 priv->ds->num_ports = 30;
2527 priv->fib_entries = 8192;
2528 rtl8380_get_version(priv);
2529 } else {
2530 priv->cpu_port = RTL839X_CPU_PORT;
2531 priv->port_mask = 0x3f;
2532 priv->r = &rtl839x_reg;
2533 priv->ds->num_ports = 53;
2534 priv->fib_entries = 16384;
2535 rtl8390_get_version(priv);
2536 }
2537 pr_info("Chip version %c\n", priv->version);
2538
2539 err = rtl838x_mdio_probe(priv);
2540 if (err) {
2541 /* Probing fails the 1st time because of missing ethernet driver
2542 * initialization. Use this to disable traffic in case the bootloader left if on
2543 */
2544 return err;
2545 }
2546 err = dsa_register_switch(priv->ds);
2547 if (err) {
2548 dev_err(dev, "Error registering switch: %d\n", err);
2549 return err;
2550 }
2551
2552 /* Enable link and media change interrupts. Are the SERDES masks needed? */
2553 sw_w32_mask(0, 3, priv->r->isr_glb_src);
2554 /* ... for all ports */
2555 irq_mask = soc_info.family == RTL8380_FAMILY_ID ? 0x0FFFFFFF : 0xFFFFFFFFFFFFFULL;
2556 priv->r->set_port_reg_le(irq_mask, priv->r->isr_port_link_sts_chg);
2557 priv->r->set_port_reg_le(irq_mask, priv->r->imr_port_link_sts_chg);
2558
2559 priv->link_state_irq = 20;
2560 if (priv->family_id == RTL8380_FAMILY_ID) {
2561 err = request_irq(priv->link_state_irq, rtl838x_switch_irq,
2562 IRQF_SHARED, "rtl838x-link-state", priv->ds);
2563 } else {
2564 err = request_irq(priv->link_state_irq, rtl839x_switch_irq,
2565 IRQF_SHARED, "rtl838x-link-state", priv->ds);
2566 }
2567 if (err) {
2568 dev_err(dev, "Error setting up switch interrupt.\n");
2569 /* Need to free allocated switch here */
2570 }
2571
2572 /* Enable interrupts for switch */
2573 sw_w32(0x1, priv->r->imr_glb);
2574
2575 rtl838x_get_l2aging(priv);
2576
2577 /* Clear all destination ports for mirror groups */
2578 for (i = 0; i < 4; i++)
2579 priv->mirror_group_ports[i] = -1;
2580
2581 return err;
2582 }
2583
2584 static int rtl838x_sw_remove(struct platform_device *pdev)
2585 {
2586 pr_info("Removing platform driver for rtl838x-sw\n");
2587 return 0;
2588 }
2589
2590 static const struct of_device_id rtl838x_switch_of_ids[] = {
2591 { .compatible = "realtek,rtl838x-switch"},
2592 { /* sentinel */ }
2593 };
2594
2595
2596 MODULE_DEVICE_TABLE(of, rtl838x_switch_of_ids);
2597
2598 static struct platform_driver rtl838x_switch_driver = {
2599 .probe = rtl838x_sw_probe,
2600 .remove = rtl838x_sw_remove,
2601 .driver = {
2602 .name = "rtl838x-switch",
2603 .pm = NULL,
2604 .of_match_table = rtl838x_switch_of_ids,
2605 },
2606 };
2607
2608 module_platform_driver(rtl838x_switch_driver);
2609
2610 MODULE_AUTHOR("B. Koblitz");
2611 MODULE_DESCRIPTION("RTL838X SoC Switch Driver");
2612 MODULE_LICENSE("GPL");
OpenWrt Source Repository