target/linux/sunxi/patches-4.1/128-3-mtd-nand-add-H27UBG8T2BTR-BC.patch

   1 diff --git a/drivers/mtd/nand/nand_ids.c b/drivers/mtd/nand/nand_ids.c
   2 index dd620c1..15b4a03 100644
   3 --- a/drivers/mtd/nand/nand_ids.c
   4 +++ b/drivers/mtd/nand/nand_ids.c
   5 @@ -19,6 +19,49 @@
   6  #define SP_OPTIONS16 (SP_OPTIONS | NAND_BUSWIDTH_16)
   7
   8  /*
   9 + * Hynix H27UBG8T2BTR timings
  10 + * This chip has an exceptionally large tADL, which results in only supporting
  11 + * ONFI timing mode 0. Using these timings, the clock can be raised from
  12 + * 12.5MHz to 50MHz.
  13 + */
  14 +const struct nand_sdr_timings hynix_h27ubg8t2btr_sdr_timing = {
  15 +       .tADL_min = 200000,
  16 +       .tALH_min = 5000,
  17 +       .tALS_min = 10000,
  18 +       .tAR_min = 10000,
  19 +       .tCEA_max = 100000,
  20 +       .tCEH_min = 20000,
  21 +       .tCH_min = 5000,
  22 +       .tCHZ_max = 50000,
  23 +       .tCLH_min = 5000,
  24 +       .tCLR_min = 10000,
  25 +       .tCLS_min = 10000,
  26 +       .tCOH_min = 15000,
  27 +       .tCS_min = 20000,
  28 +       .tDH_min = 5000,
  29 +       .tDS_min = 10000,
  30 +       .tFEAT_max = 1000000,
  31 +       .tIR_min = 0,
  32 +       .tITC_max = 1000000,
  33 +       .tRC_min = 20000,
  34 +       .tREA_max = 16000,
  35 +       .tREH_min = 8000,
  36 +       .tRHOH_min = 15000,
  37 +       .tRHW_min = 100000,
  38 +       .tRHZ_max = 100000,
  39 +       .tRLOH_min = 5000,
  40 +       .tRP_min = 10000,
  41 +       .tRST_max = 500000000,
  42 +       .tWB_max = 100000,
  43 +       .tRR_min = 20000,
  44 +       .tWC_min = 20000,
  45 +       .tWH_min = 10000,
  46 +       .tWHR_min = 80000,
  47 +       .tWP_min = 8000,
  48 +       .tWW_min = 100000,
  49 +};
  50 +
  51 +/*
  52   * The chip ID list:
  53   *    name, device ID, page size, chip size in MiB, eraseblock size, options
  54   *
  55 @@ -50,6 +93,10 @@ struct nand_flash_dev nand_flash_ids[] = {
  56                 { .id = {0xad, 0xde, 0x94, 0xda, 0x74, 0xc4} },
  57                   SZ_8K, SZ_8K, SZ_2M, 0, 6, 640, NAND_ECC_INFO(40, SZ_1K),
  58                   4 },
  59 +       {"H27UBG8T2BTR-BC 64G 3.3V 8-bit",
  60 +               { .id = {0xad, 0xd7, 0x94, 0xda, 0x74, 0xc3} },
  61 +                 SZ_8K, SZ_4K, SZ_2M, 0, 6, 640, NAND_ECC_INFO(40, SZ_1K),
  62 +                 0, &hynix_h27ubg8t2btr_sdr_timing },
  63
  64         LEGACY_ID_NAND("NAND 4MiB 5V 8-bit",   0x6B, 4, SZ_8K, SP_OPTIONS),
  65         LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE3, 4, SZ_8K, SP_OPTIONS),