target/linux/sunxi/patches-4.1/164-3-dt-sun7i-add-mod1-clocknodes.patch

   1 From e9051f5dbc26e78f91cf23ca79ae4c8471119667 Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
   3 Date: Fri, 18 Jul 2014 15:26:08 -0300
   4 Subject: [PATCH] ARM: sun7i: Add mod1 clock nodes
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
   7 Content-Transfer-Encoding: 8bit
   8
   9 This commit adds all the mod1 clocks available on A20 to its device
  10 tree. This list was created by looking at the A20 user manual.
  11
  12 Not-signed-off-by: Emilio López <emilio@elopez.com.ar>
  13 Signed-off-by: Hans de Goede <hdegoede@redhat.com>
  14 ---
  15  arch/arm/boot/dts/sun7i-a20.dtsi | 39 +++++++++++++++++++++++++++++++++++++++
  16  1 file changed, 39 insertions(+)
  17
  18 diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
  19 index 400e696..a0d18b2 100644
  20 --- a/arch/arm/boot/dts/sun7i-a20.dtsi
  21 +++ b/arch/arm/boot/dts/sun7i-a20.dtsi
  22 @@ -450,6 +450,29 @@
  23                         clock-output-names = "ir1";
  24                 };
  25
  26 +               iis0_clk: clk@01c200b8 {
  27 +                       #clock-cells = <0>;
  28 +                       compatible = "allwinner,sun4i-a10-mod1-clk";
  29 +                       reg = <0x01c200b8 0x4>;
  30 +                       clocks = <&pll2 0>, <&pll2 1>, <&pll2 2>, <&pll2 3>;
  31 +                       clock-output-names = "iis0";
  32 +               };
  33 +
  34 +               ac97_clk: clk@01c200bc {
  35 +                       #clock-cells = <0>;
  36 +                       compatible = "allwinner,sun4i-a10-mod1-clk";
  37 +                       reg = <0x01c200bc 0x4>;
  38 +                       clocks = <&pll2 3>, <&pll2 2>, <&pll2 1>, <&pll2 0>;
  39 +                       clock-output-names = "ac97";
  40 +               };
  41 +
  42 +               spdif_clk: clk@01c200c0 {
  43 +                       #clock-cells = <0>;
  44 +                       compatible = "allwinner,sun4i-a10-mod1-clk";
  45 +                       reg = <0x01c200c0 0x4>;
  46 +                       clocks = <&pll2 0>, <&pll2 1>, <&pll2 2>, <&pll2 3>;
  47 +                       clock-output-names = "spdif";
  48 +               };
  49                 usb_clk: clk@01c200cc {
  50                         #clock-cells = <1>;
  51                         #reset-cells = <1>;
  52 @@ -468,6 +491,22 @@
  53                         clock-output-names = "spi3";
  54                 };
  55
  56 +               iis1_clk: clk@01c200d8 {
  57 +                       #clock-cells = <0>;
  58 +                       compatible = "allwinner,sun4i-a10-mod1-clk";
  59 +                       reg = <0x01c200d8 0x4>;
  60 +                       clocks = <&pll2 0>, <&pll2 1>, <&pll2 2>, <&pll2 3>;
  61 +                       clock-output-names = "iis1";
  62 +               };
  63 +
  64 +               iis2_clk: clk@01c200dc {
  65 +                       #clock-cells = <0>;
  66 +                       compatible = "allwinner,sun4i-a10-mod1-clk";
  67 +                       reg = <0x01c200dc 0x4>;
  68 +                       clocks = <&pll2 0>, <&pll2 1>, <&pll2 2>, <&pll2 3>;
  69 +                       clock-output-names = "iis2";
  70 +               };
  71 +
  72                 codec_clk: clk@01c20140 {
  73                         #clock-cells = <0>;
  74                         compatible = "allwinner,sun4i-a10-codec-clk";