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sunxi: add support for 4.1
[openwrt/svn-archive/archive.git] / target / linux / sunxi / patches-4.1 / 192-crypto-add-ss.patch
1 From 6298e948215f2a3eb8a9af5c490d025deb66f179 Mon Sep 17 00:00:00 2001
2 From: LABBE Corentin <clabbe.montjoie@gmail.com>
3 Date: Fri, 17 Jul 2015 16:39:41 +0200
4 Subject: [PATCH] crypto: sunxi-ss - Add Allwinner Security System crypto
5 accelerator
6
7 Add support for the Security System included in Allwinner SoC A20.
8 The Security System is a hardware cryptographic accelerator that support:
9 - MD5 and SHA1 hash algorithms
10 - AES block cipher in CBC/ECB mode with 128/196/256bits keys.
11 - DES and 3DES block cipher in CBC/ECB mode
12
13 Signed-off-by: LABBE Corentin <clabbe.montjoie@gmail.com>
14 Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
15 ---
16 drivers/crypto/Kconfig | 17 +
17 drivers/crypto/Makefile | 1 +
18 drivers/crypto/sunxi-ss/Makefile | 2 +
19 drivers/crypto/sunxi-ss/sun4i-ss-cipher.c | 542 ++++++++++++++++++++++++++++++
20 drivers/crypto/sunxi-ss/sun4i-ss-core.c | 403 ++++++++++++++++++++++
21 drivers/crypto/sunxi-ss/sun4i-ss-hash.c | 492 +++++++++++++++++++++++++++
22 drivers/crypto/sunxi-ss/sun4i-ss.h | 199 +++++++++++
23 7 files changed, 1656 insertions(+)
24 create mode 100644 drivers/crypto/sunxi-ss/Makefile
25 create mode 100644 drivers/crypto/sunxi-ss/sun4i-ss-cipher.c
26 create mode 100644 drivers/crypto/sunxi-ss/sun4i-ss-core.c
27 create mode 100644 drivers/crypto/sunxi-ss/sun4i-ss-hash.c
28 create mode 100644 drivers/crypto/sunxi-ss/sun4i-ss.h
29
30 diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
31 index 4044125..07bc7aa 100644
32 --- a/drivers/crypto/Kconfig
33 +++ b/drivers/crypto/Kconfig
34 @@ -480,4 +480,21 @@ config CRYPTO_DEV_IMGTEC_HASH
35 hardware hash accelerator. Supporting MD5/SHA1/SHA224/SHA256
36 hashing algorithms.
37
38 +config CRYPTO_DEV_SUN4I_SS
39 + tristate "Support for Allwinner Security System cryptographic accelerator"
40 + depends on ARCH_SUNXI
41 + select CRYPTO_MD5
42 + select CRYPTO_SHA1
43 + select CRYPTO_AES
44 + select CRYPTO_DES
45 + select CRYPTO_BLKCIPHER
46 + help
47 + Some Allwinner SoC have a crypto accelerator named
48 + Security System. Select this if you want to use it.
49 + The Security System handle AES/DES/3DES ciphers in CBC mode
50 + and SHA1 and MD5 hash algorithms.
51 +
52 + To compile this driver as a module, choose M here: the module
53 + will be called sun4i-ss.
54 +
55 endif # CRYPTO_HW
56 diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
57 index e35c07a..c3ced6f 100644
58 --- a/drivers/crypto/Makefile
59 +++ b/drivers/crypto/Makefile
60 @@ -28,3 +28,4 @@ obj-$(CONFIG_CRYPTO_DEV_UX500) += ux500/
61 obj-$(CONFIG_CRYPTO_DEV_QAT) += qat/
62 obj-$(CONFIG_CRYPTO_DEV_QCE) += qce/
63 obj-$(CONFIG_CRYPTO_DEV_VMX) += vmx/
64 +obj-$(CONFIG_CRYPTO_DEV_SUN4I_SS) += sunxi-ss/
65 diff --git a/drivers/crypto/sunxi-ss/Makefile b/drivers/crypto/sunxi-ss/Makefile
66 new file mode 100644
67 index 0000000..8f4c7a2
68 --- /dev/null
69 +++ b/drivers/crypto/sunxi-ss/Makefile
70 @@ -0,0 +1,2 @@
71 +obj-$(CONFIG_CRYPTO_DEV_SUN4I_SS) += sun4i-ss.o
72 +sun4i-ss-y += sun4i-ss-core.o sun4i-ss-hash.o sun4i-ss-cipher.o
73 diff --git a/drivers/crypto/sunxi-ss/sun4i-ss-cipher.c b/drivers/crypto/sunxi-ss/sun4i-ss-cipher.c
74 new file mode 100644
75 index 0000000..e070c31
76 --- /dev/null
77 +++ b/drivers/crypto/sunxi-ss/sun4i-ss-cipher.c
78 @@ -0,0 +1,542 @@
79 +/*
80 + * sun4i-ss-cipher.c - hardware cryptographic accelerator for Allwinner A20 SoC
81 + *
82 + * Copyright (C) 2013-2015 Corentin LABBE <clabbe.montjoie@gmail.com>
83 + *
84 + * This file add support for AES cipher with 128,192,256 bits
85 + * keysize in CBC and ECB mode.
86 + * Add support also for DES and 3DES in CBC and ECB mode.
87 + *
88 + * You could find the datasheet in Documentation/arm/sunxi/README
89 + *
90 + * This program is free software; you can redistribute it and/or modify
91 + * it under the terms of the GNU General Public License as published by
92 + * the Free Software Foundation; either version 2 of the License, or
93 + * (at your option) any later version.
94 + */
95 +#include "sun4i-ss.h"
96 +
97 +static int sun4i_ss_opti_poll(struct ablkcipher_request *areq)
98 +{
99 + struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(areq);
100 + struct sun4i_tfm_ctx *op = crypto_ablkcipher_ctx(tfm);
101 + struct sun4i_ss_ctx *ss = op->ss;
102 + unsigned int ivsize = crypto_ablkcipher_ivsize(tfm);
103 + struct sun4i_cipher_req_ctx *ctx = ablkcipher_request_ctx(areq);
104 + u32 mode = ctx->mode;
105 + /* when activating SS, the default FIFO space is SS_RX_DEFAULT(32) */
106 + u32 rx_cnt = SS_RX_DEFAULT;
107 + u32 tx_cnt = 0;
108 + u32 spaces;
109 + u32 v;
110 + int i, err = 0;
111 + unsigned int ileft = areq->nbytes;
112 + unsigned int oleft = areq->nbytes;
113 + unsigned int todo;
114 + struct sg_mapping_iter mi, mo;
115 + unsigned int oi, oo; /* offset for in and out */
116 +
117 + if (areq->nbytes == 0)
118 + return 0;
119 +
120 + if (!areq->info) {
121 + dev_err_ratelimited(ss->dev, "ERROR: Empty IV\n");
122 + return -EINVAL;
123 + }
124 +
125 + if (!areq->src || !areq->dst) {
126 + dev_err_ratelimited(ss->dev, "ERROR: Some SGs are NULL\n");
127 + return -EINVAL;
128 + }
129 +
130 + spin_lock_bh(&ss->slock);
131 +
132 + for (i = 0; i < op->keylen; i += 4)
133 + writel(*(op->key + i / 4), ss->base + SS_KEY0 + i);
134 +
135 + if (areq->info) {
136 + for (i = 0; i < 4 && i < ivsize / 4; i++) {
137 + v = *(u32 *)(areq->info + i * 4);
138 + writel(v, ss->base + SS_IV0 + i * 4);
139 + }
140 + }
141 + writel(mode, ss->base + SS_CTL);
142 +
143 + sg_miter_start(&mi, areq->src, sg_nents(areq->src),
144 + SG_MITER_FROM_SG | SG_MITER_ATOMIC);
145 + sg_miter_start(&mo, areq->dst, sg_nents(areq->dst),
146 + SG_MITER_TO_SG | SG_MITER_ATOMIC);
147 + sg_miter_next(&mi);
148 + sg_miter_next(&mo);
149 + if (!mi.addr || !mo.addr) {
150 + dev_err_ratelimited(ss->dev, "ERROR: sg_miter return null\n");
151 + err = -EINVAL;
152 + goto release_ss;
153 + }
154 +
155 + ileft = areq->nbytes / 4;
156 + oleft = areq->nbytes / 4;
157 + oi = 0;
158 + oo = 0;
159 + do {
160 + todo = min3(rx_cnt, ileft, (mi.length - oi) / 4);
161 + if (todo > 0) {
162 + ileft -= todo;
163 + writesl(ss->base + SS_RXFIFO, mi.addr + oi, todo);
164 + oi += todo * 4;
165 + }
166 + if (oi == mi.length) {
167 + sg_miter_next(&mi);
168 + oi = 0;
169 + }
170 +
171 + spaces = readl(ss->base + SS_FCSR);
172 + rx_cnt = SS_RXFIFO_SPACES(spaces);
173 + tx_cnt = SS_TXFIFO_SPACES(spaces);
174 +
175 + todo = min3(tx_cnt, oleft, (mo.length - oo) / 4);
176 + if (todo > 0) {
177 + oleft -= todo;
178 + readsl(ss->base + SS_TXFIFO, mo.addr + oo, todo);
179 + oo += todo * 4;
180 + }
181 + if (oo == mo.length) {
182 + sg_miter_next(&mo);
183 + oo = 0;
184 + }
185 + } while (mo.length > 0);
186 +
187 + if (areq->info) {
188 + for (i = 0; i < 4 && i < ivsize / 4; i++) {
189 + v = readl(ss->base + SS_IV0 + i * 4);
190 + *(u32 *)(areq->info + i * 4) = v;
191 + }
192 + }
193 +
194 +release_ss:
195 + sg_miter_stop(&mi);
196 + sg_miter_stop(&mo);
197 + writel(0, ss->base + SS_CTL);
198 + spin_unlock_bh(&ss->slock);
199 + return err;
200 +}
201 +
202 +/* Generic function that support SG with size not multiple of 4 */
203 +static int sun4i_ss_cipher_poll(struct ablkcipher_request *areq)
204 +{
205 + struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(areq);
206 + struct sun4i_tfm_ctx *op = crypto_ablkcipher_ctx(tfm);
207 + struct sun4i_ss_ctx *ss = op->ss;
208 + int no_chunk = 1;
209 + struct scatterlist *in_sg = areq->src;
210 + struct scatterlist *out_sg = areq->dst;
211 + unsigned int ivsize = crypto_ablkcipher_ivsize(tfm);
212 + struct sun4i_cipher_req_ctx *ctx = ablkcipher_request_ctx(areq);
213 + u32 mode = ctx->mode;
214 + /* when activating SS, the default FIFO space is SS_RX_DEFAULT(32) */
215 + u32 rx_cnt = SS_RX_DEFAULT;
216 + u32 tx_cnt = 0;
217 + u32 v;
218 + u32 spaces;
219 + int i, err = 0;
220 + unsigned int ileft = areq->nbytes;
221 + unsigned int oleft = areq->nbytes;
222 + unsigned int todo;
223 + struct sg_mapping_iter mi, mo;
224 + unsigned int oi, oo; /* offset for in and out */
225 + char buf[4 * SS_RX_MAX];/* buffer for linearize SG src */
226 + char bufo[4 * SS_TX_MAX]; /* buffer for linearize SG dst */
227 + unsigned int ob = 0; /* offset in buf */
228 + unsigned int obo = 0; /* offset in bufo*/
229 + unsigned int obl = 0; /* length of data in bufo */
230 +
231 + if (areq->nbytes == 0)
232 + return 0;
233 +
234 + if (!areq->info) {
235 + dev_err_ratelimited(ss->dev, "ERROR: Empty IV\n");
236 + return -EINVAL;
237 + }
238 +
239 + if (!areq->src || !areq->dst) {
240 + dev_err_ratelimited(ss->dev, "ERROR: Some SGs are NULL\n");
241 + return -EINVAL;
242 + }
243 +
244 + /*
245 + * if we have only SGs with size multiple of 4,
246 + * we can use the SS optimized function
247 + */
248 + while (in_sg && no_chunk == 1) {
249 + if ((in_sg->length % 4) != 0)
250 + no_chunk = 0;
251 + in_sg = sg_next(in_sg);
252 + }
253 + while (out_sg && no_chunk == 1) {
254 + if ((out_sg->length % 4) != 0)
255 + no_chunk = 0;
256 + out_sg = sg_next(out_sg);
257 + }
258 +
259 + if (no_chunk == 1)
260 + return sun4i_ss_opti_poll(areq);
261 +
262 + spin_lock_bh(&ss->slock);
263 +
264 + for (i = 0; i < op->keylen; i += 4)
265 + writel(*(op->key + i / 4), ss->base + SS_KEY0 + i);
266 +
267 + if (areq->info) {
268 + for (i = 0; i < 4 && i < ivsize / 4; i++) {
269 + v = *(u32 *)(areq->info + i * 4);
270 + writel(v, ss->base + SS_IV0 + i * 4);
271 + }
272 + }
273 + writel(mode, ss->base + SS_CTL);
274 +
275 + sg_miter_start(&mi, areq->src, sg_nents(areq->src),
276 + SG_MITER_FROM_SG | SG_MITER_ATOMIC);
277 + sg_miter_start(&mo, areq->dst, sg_nents(areq->dst),
278 + SG_MITER_TO_SG | SG_MITER_ATOMIC);
279 + sg_miter_next(&mi);
280 + sg_miter_next(&mo);
281 + if (!mi.addr || !mo.addr) {
282 + dev_err_ratelimited(ss->dev, "ERROR: sg_miter return null\n");
283 + err = -EINVAL;
284 + goto release_ss;
285 + }
286 + ileft = areq->nbytes;
287 + oleft = areq->nbytes;
288 + oi = 0;
289 + oo = 0;
290 +
291 + while (oleft > 0) {
292 + if (ileft > 0) {
293 + /*
294 + * todo is the number of consecutive 4byte word that we
295 + * can read from current SG
296 + */
297 + todo = min3(rx_cnt, ileft / 4, (mi.length - oi) / 4);
298 + if (todo > 0 && ob == 0) {
299 + writesl(ss->base + SS_RXFIFO, mi.addr + oi,
300 + todo);
301 + ileft -= todo * 4;
302 + oi += todo * 4;
303 + } else {
304 + /*
305 + * not enough consecutive bytes, so we need to
306 + * linearize in buf. todo is in bytes
307 + * After that copy, if we have a multiple of 4
308 + * we need to be able to write all buf in one
309 + * pass, so it is why we min() with rx_cnt
310 + */
311 + todo = min3(rx_cnt * 4 - ob, ileft,
312 + mi.length - oi);
313 + memcpy(buf + ob, mi.addr + oi, todo);
314 + ileft -= todo;
315 + oi += todo;
316 + ob += todo;
317 + if (ob % 4 == 0) {
318 + writesl(ss->base + SS_RXFIFO, buf,
319 + ob / 4);
320 + ob = 0;
321 + }
322 + }
323 + if (oi == mi.length) {
324 + sg_miter_next(&mi);
325 + oi = 0;
326 + }
327 + }
328 +
329 + spaces = readl(ss->base + SS_FCSR);
330 + rx_cnt = SS_RXFIFO_SPACES(spaces);
331 + tx_cnt = SS_TXFIFO_SPACES(spaces);
332 + dev_dbg(ss->dev, "%x %u/%u %u/%u cnt=%u %u/%u %u/%u cnt=%u %u %u\n",
333 + mode,
334 + oi, mi.length, ileft, areq->nbytes, rx_cnt,
335 + oo, mo.length, oleft, areq->nbytes, tx_cnt,
336 + todo, ob);
337 +
338 + if (tx_cnt == 0)
339 + continue;
340 + /* todo in 4bytes word */
341 + todo = min3(tx_cnt, oleft / 4, (mo.length - oo) / 4);
342 + if (todo > 0) {
343 + readsl(ss->base + SS_TXFIFO, mo.addr + oo, todo);
344 + oleft -= todo * 4;
345 + oo += todo * 4;
346 + if (oo == mo.length) {
347 + sg_miter_next(&mo);
348 + oo = 0;
349 + }
350 + } else {
351 + /*
352 + * read obl bytes in bufo, we read at maximum for
353 + * emptying the device
354 + */
355 + readsl(ss->base + SS_TXFIFO, bufo, tx_cnt);
356 + obl = tx_cnt * 4;
357 + obo = 0;
358 + do {
359 + /*
360 + * how many bytes we can copy ?
361 + * no more than remaining SG size
362 + * no more than remaining buffer
363 + * no need to test against oleft
364 + */
365 + todo = min(mo.length - oo, obl - obo);
366 + memcpy(mo.addr + oo, bufo + obo, todo);
367 + oleft -= todo;
368 + obo += todo;
369 + oo += todo;
370 + if (oo == mo.length) {
371 + sg_miter_next(&mo);
372 + oo = 0;
373 + }
374 + } while (obo < obl);
375 + /* bufo must be fully used here */
376 + }
377 + }
378 + if (areq->info) {
379 + for (i = 0; i < 4 && i < ivsize / 4; i++) {
380 + v = readl(ss->base + SS_IV0 + i * 4);
381 + *(u32 *)(areq->info + i * 4) = v;
382 + }
383 + }
384 +
385 +release_ss:
386 + sg_miter_stop(&mi);
387 + sg_miter_stop(&mo);
388 + writel(0, ss->base + SS_CTL);
389 + spin_unlock_bh(&ss->slock);
390 +
391 + return err;
392 +}
393 +
394 +/* CBC AES */
395 +int sun4i_ss_cbc_aes_encrypt(struct ablkcipher_request *areq)
396 +{
397 + struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(areq);
398 + struct sun4i_tfm_ctx *op = crypto_ablkcipher_ctx(tfm);
399 + struct sun4i_cipher_req_ctx *rctx = ablkcipher_request_ctx(areq);
400 +
401 + rctx->mode = SS_OP_AES | SS_CBC | SS_ENABLED | SS_ENCRYPTION |
402 + op->keymode;
403 + return sun4i_ss_cipher_poll(areq);
404 +}
405 +
406 +int sun4i_ss_cbc_aes_decrypt(struct ablkcipher_request *areq)
407 +{
408 + struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(areq);
409 + struct sun4i_tfm_ctx *op = crypto_ablkcipher_ctx(tfm);
410 + struct sun4i_cipher_req_ctx *rctx = ablkcipher_request_ctx(areq);
411 +
412 + rctx->mode = SS_OP_AES | SS_CBC | SS_ENABLED | SS_DECRYPTION |
413 + op->keymode;
414 + return sun4i_ss_cipher_poll(areq);
415 +}
416 +
417 +/* ECB AES */
418 +int sun4i_ss_ecb_aes_encrypt(struct ablkcipher_request *areq)
419 +{
420 + struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(areq);
421 + struct sun4i_tfm_ctx *op = crypto_ablkcipher_ctx(tfm);
422 + struct sun4i_cipher_req_ctx *rctx = ablkcipher_request_ctx(areq);
423 +
424 + rctx->mode = SS_OP_AES | SS_ECB | SS_ENABLED | SS_ENCRYPTION |
425 + op->keymode;
426 + return sun4i_ss_cipher_poll(areq);
427 +}
428 +
429 +int sun4i_ss_ecb_aes_decrypt(struct ablkcipher_request *areq)
430 +{
431 + struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(areq);
432 + struct sun4i_tfm_ctx *op = crypto_ablkcipher_ctx(tfm);
433 + struct sun4i_cipher_req_ctx *rctx = ablkcipher_request_ctx(areq);
434 +
435 + rctx->mode = SS_OP_AES | SS_ECB | SS_ENABLED | SS_DECRYPTION |
436 + op->keymode;
437 + return sun4i_ss_cipher_poll(areq);
438 +}
439 +
440 +/* CBC DES */
441 +int sun4i_ss_cbc_des_encrypt(struct ablkcipher_request *areq)
442 +{
443 + struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(areq);
444 + struct sun4i_tfm_ctx *op = crypto_ablkcipher_ctx(tfm);
445 + struct sun4i_cipher_req_ctx *rctx = ablkcipher_request_ctx(areq);
446 +
447 + rctx->mode = SS_OP_DES | SS_CBC | SS_ENABLED | SS_ENCRYPTION |
448 + op->keymode;
449 + return sun4i_ss_cipher_poll(areq);
450 +}
451 +
452 +int sun4i_ss_cbc_des_decrypt(struct ablkcipher_request *areq)
453 +{
454 + struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(areq);
455 + struct sun4i_tfm_ctx *op = crypto_ablkcipher_ctx(tfm);
456 + struct sun4i_cipher_req_ctx *rctx = ablkcipher_request_ctx(areq);
457 +
458 + rctx->mode = SS_OP_DES | SS_CBC | SS_ENABLED | SS_DECRYPTION |
459 + op->keymode;
460 + return sun4i_ss_cipher_poll(areq);
461 +}
462 +
463 +/* ECB DES */
464 +int sun4i_ss_ecb_des_encrypt(struct ablkcipher_request *areq)
465 +{
466 + struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(areq);
467 + struct sun4i_tfm_ctx *op = crypto_ablkcipher_ctx(tfm);
468 + struct sun4i_cipher_req_ctx *rctx = ablkcipher_request_ctx(areq);
469 +
470 + rctx->mode = SS_OP_DES | SS_ECB | SS_ENABLED | SS_ENCRYPTION |
471 + op->keymode;
472 + return sun4i_ss_cipher_poll(areq);
473 +}
474 +
475 +int sun4i_ss_ecb_des_decrypt(struct ablkcipher_request *areq)
476 +{
477 + struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(areq);
478 + struct sun4i_tfm_ctx *op = crypto_ablkcipher_ctx(tfm);
479 + struct sun4i_cipher_req_ctx *rctx = ablkcipher_request_ctx(areq);
480 +
481 + rctx->mode = SS_OP_DES | SS_ECB | SS_ENABLED | SS_DECRYPTION |
482 + op->keymode;
483 + return sun4i_ss_cipher_poll(areq);
484 +}
485 +
486 +/* CBC 3DES */
487 +int sun4i_ss_cbc_des3_encrypt(struct ablkcipher_request *areq)
488 +{
489 + struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(areq);
490 + struct sun4i_tfm_ctx *op = crypto_ablkcipher_ctx(tfm);
491 + struct sun4i_cipher_req_ctx *rctx = ablkcipher_request_ctx(areq);
492 +
493 + rctx->mode = SS_OP_3DES | SS_CBC | SS_ENABLED | SS_ENCRYPTION |
494 + op->keymode;
495 + return sun4i_ss_cipher_poll(areq);
496 +}
497 +
498 +int sun4i_ss_cbc_des3_decrypt(struct ablkcipher_request *areq)
499 +{
500 + struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(areq);
501 + struct sun4i_tfm_ctx *op = crypto_ablkcipher_ctx(tfm);
502 + struct sun4i_cipher_req_ctx *rctx = ablkcipher_request_ctx(areq);
503 +
504 + rctx->mode = SS_OP_3DES | SS_CBC | SS_ENABLED | SS_DECRYPTION |
505 + op->keymode;
506 + return sun4i_ss_cipher_poll(areq);
507 +}
508 +
509 +/* ECB 3DES */
510 +int sun4i_ss_ecb_des3_encrypt(struct ablkcipher_request *areq)
511 +{
512 + struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(areq);
513 + struct sun4i_tfm_ctx *op = crypto_ablkcipher_ctx(tfm);
514 + struct sun4i_cipher_req_ctx *rctx = ablkcipher_request_ctx(areq);
515 +
516 + rctx->mode = SS_OP_3DES | SS_ECB | SS_ENABLED | SS_ENCRYPTION |
517 + op->keymode;
518 + return sun4i_ss_cipher_poll(areq);
519 +}
520 +
521 +int sun4i_ss_ecb_des3_decrypt(struct ablkcipher_request *areq)
522 +{
523 + struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(areq);
524 + struct sun4i_tfm_ctx *op = crypto_ablkcipher_ctx(tfm);
525 + struct sun4i_cipher_req_ctx *rctx = ablkcipher_request_ctx(areq);
526 +
527 + rctx->mode = SS_OP_3DES | SS_ECB | SS_ENABLED | SS_DECRYPTION |
528 + op->keymode;
529 + return sun4i_ss_cipher_poll(areq);
530 +}
531 +
532 +int sun4i_ss_cipher_init(struct crypto_tfm *tfm)
533 +{
534 + struct sun4i_tfm_ctx *op = crypto_tfm_ctx(tfm);
535 + struct crypto_alg *alg = tfm->__crt_alg;
536 + struct sun4i_ss_alg_template *algt;
537 +
538 + memset(op, 0, sizeof(struct sun4i_tfm_ctx));
539 +
540 + algt = container_of(alg, struct sun4i_ss_alg_template, alg.crypto);
541 + op->ss = algt->ss;
542 +
543 + tfm->crt_ablkcipher.reqsize = sizeof(struct sun4i_cipher_req_ctx);
544 +
545 + return 0;
546 +}
547 +
548 +/* check and set the AES key, prepare the mode to be used */
549 +int sun4i_ss_aes_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
550 + unsigned int keylen)
551 +{
552 + struct sun4i_tfm_ctx *op = crypto_ablkcipher_ctx(tfm);
553 + struct sun4i_ss_ctx *ss = op->ss;
554 +
555 + switch (keylen) {
556 + case 128 / 8:
557 + op->keymode = SS_AES_128BITS;
558 + break;
559 + case 192 / 8:
560 + op->keymode = SS_AES_192BITS;
561 + break;
562 + case 256 / 8:
563 + op->keymode = SS_AES_256BITS;
564 + break;
565 + default:
566 + dev_err(ss->dev, "ERROR: Invalid keylen %u\n", keylen);
567 + crypto_ablkcipher_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
568 + return -EINVAL;
569 + }
570 + op->keylen = keylen;
571 + memcpy(op->key, key, keylen);
572 + return 0;
573 +}
574 +
575 +/* check and set the DES key, prepare the mode to be used */
576 +int sun4i_ss_des_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
577 + unsigned int keylen)
578 +{
579 + struct sun4i_tfm_ctx *op = crypto_ablkcipher_ctx(tfm);
580 + struct sun4i_ss_ctx *ss = op->ss;
581 + u32 flags;
582 + u32 tmp[DES_EXPKEY_WORDS];
583 + int ret;
584 +
585 + if (unlikely(keylen != DES_KEY_SIZE)) {
586 + dev_err(ss->dev, "Invalid keylen %u\n", keylen);
587 + crypto_ablkcipher_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
588 + return -EINVAL;
589 + }
590 +
591 + flags = crypto_ablkcipher_get_flags(tfm);
592 +
593 + ret = des_ekey(tmp, key);
594 + if (unlikely(ret == 0) && (flags & CRYPTO_TFM_REQ_WEAK_KEY)) {
595 + crypto_ablkcipher_set_flags(tfm, CRYPTO_TFM_RES_WEAK_KEY);
596 + dev_dbg(ss->dev, "Weak key %u\n", keylen);
597 + return -EINVAL;
598 + }
599 +
600 + op->keylen = keylen;
601 + memcpy(op->key, key, keylen);
602 + return 0;
603 +}
604 +
605 +/* check and set the 3DES key, prepare the mode to be used */
606 +int sun4i_ss_des3_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
607 + unsigned int keylen)
608 +{
609 + struct sun4i_tfm_ctx *op = crypto_ablkcipher_ctx(tfm);
610 + struct sun4i_ss_ctx *ss = op->ss;
611 +
612 + if (unlikely(keylen != 3 * DES_KEY_SIZE)) {
613 + dev_err(ss->dev, "Invalid keylen %u\n", keylen);
614 + crypto_ablkcipher_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
615 + return -EINVAL;
616 + }
617 + op->keylen = keylen;
618 + memcpy(op->key, key, keylen);
619 + return 0;
620 +}
621 diff --git a/drivers/crypto/sunxi-ss/sun4i-ss-core.c b/drivers/crypto/sunxi-ss/sun4i-ss-core.c
622 new file mode 100644
623 index 0000000..0b79b58
624 --- /dev/null
625 +++ b/drivers/crypto/sunxi-ss/sun4i-ss-core.c
626 @@ -0,0 +1,403 @@
627 +/*
628 + * sun4i-ss-core.c - hardware cryptographic accelerator for Allwinner A20 SoC
629 + *
630 + * Copyright (C) 2013-2015 Corentin LABBE <clabbe.montjoie@gmail.com>
631 + *
632 + * Core file which registers crypto algorithms supported by the SS.
633 + *
634 + * You could find a link for the datasheet in Documentation/arm/sunxi/README
635 + *
636 + * This program is free software; you can redistribute it and/or modify
637 + * it under the terms of the GNU General Public License as published by
638 + * the Free Software Foundation; either version 2 of the License, or
639 + * (at your option) any later version.
640 + */
641 +#include <linux/clk.h>
642 +#include <linux/crypto.h>
643 +#include <linux/io.h>
644 +#include <linux/module.h>
645 +#include <linux/of.h>
646 +#include <linux/platform_device.h>
647 +#include <crypto/scatterwalk.h>
648 +#include <linux/scatterlist.h>
649 +#include <linux/interrupt.h>
650 +#include <linux/delay.h>
651 +
652 +#include "sun4i-ss.h"
653 +
654 +static struct sun4i_ss_alg_template ss_algs[] = {
655 +{ .type = CRYPTO_ALG_TYPE_AHASH,
656 + .mode = SS_OP_MD5,
657 + .alg.hash = {
658 + .init = sun4i_hash_init,
659 + .update = sun4i_hash_update,
660 + .final = sun4i_hash_final,
661 + .finup = sun4i_hash_finup,
662 + .digest = sun4i_hash_digest,
663 + .export = sun4i_hash_export_md5,
664 + .import = sun4i_hash_import_md5,
665 + .halg = {
666 + .digestsize = MD5_DIGEST_SIZE,
667 + .base = {
668 + .cra_name = "md5",
669 + .cra_driver_name = "md5-sun4i-ss",
670 + .cra_priority = 300,
671 + .cra_alignmask = 3,
672 + .cra_flags = CRYPTO_ALG_TYPE_AHASH,
673 + .cra_blocksize = MD5_HMAC_BLOCK_SIZE,
674 + .cra_ctxsize = sizeof(struct sun4i_req_ctx),
675 + .cra_module = THIS_MODULE,
676 + .cra_type = &crypto_ahash_type,
677 + .cra_init = sun4i_hash_crainit
678 + }
679 + }
680 + }
681 +},
682 +{ .type = CRYPTO_ALG_TYPE_AHASH,
683 + .mode = SS_OP_SHA1,
684 + .alg.hash = {
685 + .init = sun4i_hash_init,
686 + .update = sun4i_hash_update,
687 + .final = sun4i_hash_final,
688 + .finup = sun4i_hash_finup,
689 + .digest = sun4i_hash_digest,
690 + .export = sun4i_hash_export_sha1,
691 + .import = sun4i_hash_import_sha1,
692 + .halg = {
693 + .digestsize = SHA1_DIGEST_SIZE,
694 + .base = {
695 + .cra_name = "sha1",
696 + .cra_driver_name = "sha1-sun4i-ss",
697 + .cra_priority = 300,
698 + .cra_alignmask = 3,
699 + .cra_flags = CRYPTO_ALG_TYPE_AHASH,
700 + .cra_blocksize = SHA1_BLOCK_SIZE,
701 + .cra_ctxsize = sizeof(struct sun4i_req_ctx),
702 + .cra_module = THIS_MODULE,
703 + .cra_type = &crypto_ahash_type,
704 + .cra_init = sun4i_hash_crainit
705 + }
706 + }
707 + }
708 +},
709 +{ .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
710 + .alg.crypto = {
711 + .cra_name = "cbc(aes)",
712 + .cra_driver_name = "cbc-aes-sun4i-ss",
713 + .cra_priority = 300,
714 + .cra_blocksize = AES_BLOCK_SIZE,
715 + .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER,
716 + .cra_ctxsize = sizeof(struct sun4i_tfm_ctx),
717 + .cra_module = THIS_MODULE,
718 + .cra_alignmask = 3,
719 + .cra_type = &crypto_ablkcipher_type,
720 + .cra_init = sun4i_ss_cipher_init,
721 + .cra_ablkcipher = {
722 + .min_keysize = AES_MIN_KEY_SIZE,
723 + .max_keysize = AES_MAX_KEY_SIZE,
724 + .ivsize = AES_BLOCK_SIZE,
725 + .setkey = sun4i_ss_aes_setkey,
726 + .encrypt = sun4i_ss_cbc_aes_encrypt,
727 + .decrypt = sun4i_ss_cbc_aes_decrypt,
728 + }
729 + }
730 +},
731 +{ .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
732 + .alg.crypto = {
733 + .cra_name = "ecb(aes)",
734 + .cra_driver_name = "ecb-aes-sun4i-ss",
735 + .cra_priority = 300,
736 + .cra_blocksize = AES_BLOCK_SIZE,
737 + .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER,
738 + .cra_ctxsize = sizeof(struct sun4i_tfm_ctx),
739 + .cra_module = THIS_MODULE,
740 + .cra_alignmask = 3,
741 + .cra_type = &crypto_ablkcipher_type,
742 + .cra_init = sun4i_ss_cipher_init,
743 + .cra_ablkcipher = {
744 + .min_keysize = AES_MIN_KEY_SIZE,
745 + .max_keysize = AES_MAX_KEY_SIZE,
746 + .ivsize = AES_BLOCK_SIZE,
747 + .setkey = sun4i_ss_aes_setkey,
748 + .encrypt = sun4i_ss_ecb_aes_encrypt,
749 + .decrypt = sun4i_ss_ecb_aes_decrypt,
750 + }
751 + }
752 +},
753 +{ .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
754 + .alg.crypto = {
755 + .cra_name = "cbc(des)",
756 + .cra_driver_name = "cbc-des-sun4i-ss",
757 + .cra_priority = 300,
758 + .cra_blocksize = DES_BLOCK_SIZE,
759 + .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER,
760 + .cra_ctxsize = sizeof(struct sun4i_req_ctx),
761 + .cra_module = THIS_MODULE,
762 + .cra_alignmask = 3,
763 + .cra_type = &crypto_ablkcipher_type,
764 + .cra_init = sun4i_ss_cipher_init,
765 + .cra_u.ablkcipher = {
766 + .min_keysize = DES_KEY_SIZE,
767 + .max_keysize = DES_KEY_SIZE,
768 + .ivsize = DES_BLOCK_SIZE,
769 + .setkey = sun4i_ss_des_setkey,
770 + .encrypt = sun4i_ss_cbc_des_encrypt,
771 + .decrypt = sun4i_ss_cbc_des_decrypt,
772 + }
773 + }
774 +},
775 +{ .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
776 + .alg.crypto = {
777 + .cra_name = "ecb(des)",
778 + .cra_driver_name = "ecb-des-sun4i-ss",
779 + .cra_priority = 300,
780 + .cra_blocksize = DES_BLOCK_SIZE,
781 + .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER,
782 + .cra_ctxsize = sizeof(struct sun4i_req_ctx),
783 + .cra_module = THIS_MODULE,
784 + .cra_alignmask = 3,
785 + .cra_type = &crypto_ablkcipher_type,
786 + .cra_init = sun4i_ss_cipher_init,
787 + .cra_u.ablkcipher = {
788 + .min_keysize = DES_KEY_SIZE,
789 + .max_keysize = DES_KEY_SIZE,
790 + .setkey = sun4i_ss_des_setkey,
791 + .encrypt = sun4i_ss_ecb_des_encrypt,
792 + .decrypt = sun4i_ss_ecb_des_decrypt,
793 + }
794 + }
795 +},
796 +{ .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
797 + .alg.crypto = {
798 + .cra_name = "cbc(des3_ede)",
799 + .cra_driver_name = "cbc-des3-sun4i-ss",
800 + .cra_priority = 300,
801 + .cra_blocksize = DES3_EDE_BLOCK_SIZE,
802 + .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER,
803 + .cra_ctxsize = sizeof(struct sun4i_req_ctx),
804 + .cra_module = THIS_MODULE,
805 + .cra_alignmask = 3,
806 + .cra_type = &crypto_ablkcipher_type,
807 + .cra_init = sun4i_ss_cipher_init,
808 + .cra_u.ablkcipher = {
809 + .min_keysize = DES3_EDE_KEY_SIZE,
810 + .max_keysize = DES3_EDE_KEY_SIZE,
811 + .ivsize = DES3_EDE_BLOCK_SIZE,
812 + .setkey = sun4i_ss_des3_setkey,
813 + .encrypt = sun4i_ss_cbc_des3_encrypt,
814 + .decrypt = sun4i_ss_cbc_des3_decrypt,
815 + }
816 + }
817 +},
818 +{ .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
819 + .alg.crypto = {
820 + .cra_name = "ecb(des3_ede)",
821 + .cra_driver_name = "ecb-des3-sun4i-ss",
822 + .cra_priority = 300,
823 + .cra_blocksize = DES3_EDE_BLOCK_SIZE,
824 + .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER,
825 + .cra_ctxsize = sizeof(struct sun4i_req_ctx),
826 + .cra_module = THIS_MODULE,
827 + .cra_alignmask = 3,
828 + .cra_type = &crypto_ablkcipher_type,
829 + .cra_init = sun4i_ss_cipher_init,
830 + .cra_u.ablkcipher = {
831 + .min_keysize = DES3_EDE_KEY_SIZE,
832 + .max_keysize = DES3_EDE_KEY_SIZE,
833 + .ivsize = DES3_EDE_BLOCK_SIZE,
834 + .setkey = sun4i_ss_des3_setkey,
835 + .encrypt = sun4i_ss_ecb_des3_encrypt,
836 + .decrypt = sun4i_ss_ecb_des3_decrypt,
837 + }
838 + }
839 +},
840 +};
841 +
842 +static int sun4i_ss_probe(struct platform_device *pdev)
843 +{
844 + struct resource *res;
845 + u32 v;
846 + int err, i;
847 + unsigned long cr;
848 + const unsigned long cr_ahb = 24 * 1000 * 1000;
849 + const unsigned long cr_mod = 150 * 1000 * 1000;
850 + struct sun4i_ss_ctx *ss;
851 +
852 + if (!pdev->dev.of_node)
853 + return -ENODEV;
854 +
855 + ss = devm_kzalloc(&pdev->dev, sizeof(*ss), GFP_KERNEL);
856 + if (!ss)
857 + return -ENOMEM;
858 +
859 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
860 + ss->base = devm_ioremap_resource(&pdev->dev, res);
861 + if (IS_ERR(ss->base)) {
862 + dev_err(&pdev->dev, "Cannot request MMIO\n");
863 + return PTR_ERR(ss->base);
864 + }
865 +
866 + ss->ssclk = devm_clk_get(&pdev->dev, "mod");
867 + if (IS_ERR(ss->ssclk)) {
868 + err = PTR_ERR(ss->ssclk);
869 + dev_err(&pdev->dev, "Cannot get SS clock err=%d\n", err);
870 + return err;
871 + }
872 + dev_dbg(&pdev->dev, "clock ss acquired\n");
873 +
874 + ss->busclk = devm_clk_get(&pdev->dev, "ahb");
875 + if (IS_ERR(ss->busclk)) {
876 + err = PTR_ERR(ss->busclk);
877 + dev_err(&pdev->dev, "Cannot get AHB SS clock err=%d\n", err);
878 + return err;
879 + }
880 + dev_dbg(&pdev->dev, "clock ahb_ss acquired\n");
881 +
882 + /* Enable both clocks */
883 + err = clk_prepare_enable(ss->busclk);
884 + if (err != 0) {
885 + dev_err(&pdev->dev, "Cannot prepare_enable busclk\n");
886 + return err;
887 + }
888 + err = clk_prepare_enable(ss->ssclk);
889 + if (err != 0) {
890 + dev_err(&pdev->dev, "Cannot prepare_enable ssclk\n");
891 + goto error_ssclk;
892 + }
893 +
894 + /*
895 + * Check that clock have the correct rates given in the datasheet
896 + * Try to set the clock to the maximum allowed
897 + */
898 + err = clk_set_rate(ss->ssclk, cr_mod);
899 + if (err != 0) {
900 + dev_err(&pdev->dev, "Cannot set clock rate to ssclk\n");
901 + goto error_clk;
902 + }
903 +
904 + /*
905 + * The only impact on clocks below requirement are bad performance,
906 + * so do not print "errors"
907 + * warn on Overclocked clocks
908 + */
909 + cr = clk_get_rate(ss->busclk);
910 + if (cr >= cr_ahb)
911 + dev_dbg(&pdev->dev, "Clock bus %lu (%lu MHz) (must be >= %lu)\n",
912 + cr, cr / 1000000, cr_ahb);
913 + else
914 + dev_warn(&pdev->dev, "Clock bus %lu (%lu MHz) (must be >= %lu)\n",
915 + cr, cr / 1000000, cr_ahb);
916 +
917 + cr = clk_get_rate(ss->ssclk);
918 + if (cr <= cr_mod)
919 + if (cr < cr_mod)
920 + dev_warn(&pdev->dev, "Clock ss %lu (%lu MHz) (must be <= %lu)\n",
921 + cr, cr / 1000000, cr_mod);
922 + else
923 + dev_dbg(&pdev->dev, "Clock ss %lu (%lu MHz) (must be <= %lu)\n",
924 + cr, cr / 1000000, cr_mod);
925 + else
926 + dev_warn(&pdev->dev, "Clock ss is at %lu (%lu MHz) (must be <= %lu)\n",
927 + cr, cr / 1000000, cr_mod);
928 +
929 + /*
930 + * Datasheet named it "Die Bonding ID"
931 + * I expect to be a sort of Security System Revision number.
932 + * Since the A80 seems to have an other version of SS
933 + * this info could be useful
934 + */
935 + writel(SS_ENABLED, ss->base + SS_CTL);
936 + v = readl(ss->base + SS_CTL);
937 + v >>= 16;
938 + v &= 0x07;
939 + dev_info(&pdev->dev, "Die ID %d\n", v);
940 + writel(0, ss->base + SS_CTL);
941 +
942 + ss->dev = &pdev->dev;
943 +
944 + spin_lock_init(&ss->slock);
945 +
946 + for (i = 0; i < ARRAY_SIZE(ss_algs); i++) {
947 + ss_algs[i].ss = ss;
948 + switch (ss_algs[i].type) {
949 + case CRYPTO_ALG_TYPE_ABLKCIPHER:
950 + err = crypto_register_alg(&ss_algs[i].alg.crypto);
951 + if (err != 0) {
952 + dev_err(ss->dev, "Fail to register %s\n",
953 + ss_algs[i].alg.crypto.cra_name);
954 + goto error_alg;
955 + }
956 + break;
957 + case CRYPTO_ALG_TYPE_AHASH:
958 + err = crypto_register_ahash(&ss_algs[i].alg.hash);
959 + if (err != 0) {
960 + dev_err(ss->dev, "Fail to register %s\n",
961 + ss_algs[i].alg.hash.halg.base.cra_name);
962 + goto error_alg;
963 + }
964 + break;
965 + }
966 + }
967 + platform_set_drvdata(pdev, ss);
968 + return 0;
969 +error_alg:
970 + i--;
971 + for (; i >= 0; i--) {
972 + switch (ss_algs[i].type) {
973 + case CRYPTO_ALG_TYPE_ABLKCIPHER:
974 + crypto_unregister_alg(&ss_algs[i].alg.crypto);
975 + break;
976 + case CRYPTO_ALG_TYPE_AHASH:
977 + crypto_unregister_ahash(&ss_algs[i].alg.hash);
978 + break;
979 + }
980 + }
981 +error_clk:
982 + clk_disable_unprepare(ss->ssclk);
983 +error_ssclk:
984 + clk_disable_unprepare(ss->busclk);
985 + return err;
986 +}
987 +
988 +static int sun4i_ss_remove(struct platform_device *pdev)
989 +{
990 + int i;
991 + struct sun4i_ss_ctx *ss = platform_get_drvdata(pdev);
992 +
993 + for (i = 0; i < ARRAY_SIZE(ss_algs); i++) {
994 + switch (ss_algs[i].type) {
995 + case CRYPTO_ALG_TYPE_ABLKCIPHER:
996 + crypto_unregister_alg(&ss_algs[i].alg.crypto);
997 + break;
998 + case CRYPTO_ALG_TYPE_AHASH:
999 + crypto_unregister_ahash(&ss_algs[i].alg.hash);
1000 + break;
1001 + }
1002 + }
1003 +
1004 + writel(0, ss->base + SS_CTL);
1005 + clk_disable_unprepare(ss->busclk);
1006 + clk_disable_unprepare(ss->ssclk);
1007 + return 0;
1008 +}
1009 +
1010 +static const struct of_device_id a20ss_crypto_of_match_table[] = {
1011 + { .compatible = "allwinner,sun4i-a10-crypto" },
1012 + {}
1013 +};
1014 +MODULE_DEVICE_TABLE(of, a20ss_crypto_of_match_table);
1015 +
1016 +static struct platform_driver sun4i_ss_driver = {
1017 + .probe = sun4i_ss_probe,
1018 + .remove = sun4i_ss_remove,
1019 + .driver = {
1020 + .name = "sun4i-ss",
1021 + .of_match_table = a20ss_crypto_of_match_table,
1022 + },
1023 +};
1024 +
1025 +module_platform_driver(sun4i_ss_driver);
1026 +
1027 +MODULE_DESCRIPTION("Allwinner Security System cryptographic accelerator");
1028 +MODULE_LICENSE("GPL");
1029 +MODULE_AUTHOR("Corentin LABBE <clabbe.montjoie@gmail.com>");
1030 diff --git a/drivers/crypto/sunxi-ss/sun4i-ss-hash.c b/drivers/crypto/sunxi-ss/sun4i-ss-hash.c
1031 new file mode 100644
1032 index 0000000..ff80314
1033 --- /dev/null
1034 +++ b/drivers/crypto/sunxi-ss/sun4i-ss-hash.c
1035 @@ -0,0 +1,492 @@
1036 +/*
1037 + * sun4i-ss-hash.c - hardware cryptographic accelerator for Allwinner A20 SoC
1038 + *
1039 + * Copyright (C) 2013-2015 Corentin LABBE <clabbe.montjoie@gmail.com>
1040 + *
1041 + * This file add support for MD5 and SHA1.
1042 + *
1043 + * You could find the datasheet in Documentation/arm/sunxi/README
1044 + *
1045 + * This program is free software; you can redistribute it and/or modify
1046 + * it under the terms of the GNU General Public License as published by
1047 + * the Free Software Foundation; either version 2 of the License, or
1048 + * (at your option) any later version.
1049 + */
1050 +#include "sun4i-ss.h"
1051 +#include <linux/scatterlist.h>
1052 +
1053 +/* This is a totally arbitrary value */
1054 +#define SS_TIMEOUT 100
1055 +
1056 +int sun4i_hash_crainit(struct crypto_tfm *tfm)
1057 +{
1058 + crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
1059 + sizeof(struct sun4i_req_ctx));
1060 + return 0;
1061 +}
1062 +
1063 +/* sun4i_hash_init: initialize request context */
1064 +int sun4i_hash_init(struct ahash_request *areq)
1065 +{
1066 + struct sun4i_req_ctx *op = ahash_request_ctx(areq);
1067 + struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1068 + struct ahash_alg *alg = __crypto_ahash_alg(tfm->base.__crt_alg);
1069 + struct sun4i_ss_alg_template *algt;
1070 + struct sun4i_ss_ctx *ss;
1071 +
1072 + memset(op, 0, sizeof(struct sun4i_req_ctx));
1073 +
1074 + algt = container_of(alg, struct sun4i_ss_alg_template, alg.hash);
1075 + ss = algt->ss;
1076 + op->ss = algt->ss;
1077 + op->mode = algt->mode;
1078 +
1079 + return 0;
1080 +}
1081 +
1082 +int sun4i_hash_export_md5(struct ahash_request *areq, void *out)
1083 +{
1084 + struct sun4i_req_ctx *op = ahash_request_ctx(areq);
1085 + struct md5_state *octx = out;
1086 + int i;
1087 +
1088 + octx->byte_count = op->byte_count + op->len;
1089 +
1090 + memcpy(octx->block, op->buf, op->len);
1091 +
1092 + if (op->byte_count > 0) {
1093 + for (i = 0; i < 4; i++)
1094 + octx->hash[i] = op->hash[i];
1095 + } else {
1096 + octx->hash[0] = SHA1_H0;
1097 + octx->hash[1] = SHA1_H1;
1098 + octx->hash[2] = SHA1_H2;
1099 + octx->hash[3] = SHA1_H3;
1100 + }
1101 +
1102 + return 0;
1103 +}
1104 +
1105 +int sun4i_hash_import_md5(struct ahash_request *areq, const void *in)
1106 +{
1107 + struct sun4i_req_ctx *op = ahash_request_ctx(areq);
1108 + const struct md5_state *ictx = in;
1109 + int i;
1110 +
1111 + sun4i_hash_init(areq);
1112 +
1113 + op->byte_count = ictx->byte_count & ~0x3F;
1114 + op->len = ictx->byte_count & 0x3F;
1115 +
1116 + memcpy(op->buf, ictx->block, op->len);
1117 +
1118 + for (i = 0; i < 4; i++)
1119 + op->hash[i] = ictx->hash[i];
1120 +
1121 + return 0;
1122 +}
1123 +
1124 +int sun4i_hash_export_sha1(struct ahash_request *areq, void *out)
1125 +{
1126 + struct sun4i_req_ctx *op = ahash_request_ctx(areq);
1127 + struct sha1_state *octx = out;
1128 + int i;
1129 +
1130 + octx->count = op->byte_count + op->len;
1131 +
1132 + memcpy(octx->buffer, op->buf, op->len);
1133 +
1134 + if (op->byte_count > 0) {
1135 + for (i = 0; i < 5; i++)
1136 + octx->state[i] = op->hash[i];
1137 + } else {
1138 + octx->state[0] = SHA1_H0;
1139 + octx->state[1] = SHA1_H1;
1140 + octx->state[2] = SHA1_H2;
1141 + octx->state[3] = SHA1_H3;
1142 + octx->state[4] = SHA1_H4;
1143 + }
1144 +
1145 + return 0;
1146 +}
1147 +
1148 +int sun4i_hash_import_sha1(struct ahash_request *areq, const void *in)
1149 +{
1150 + struct sun4i_req_ctx *op = ahash_request_ctx(areq);
1151 + const struct sha1_state *ictx = in;
1152 + int i;
1153 +
1154 + sun4i_hash_init(areq);
1155 +
1156 + op->byte_count = ictx->count & ~0x3F;
1157 + op->len = ictx->count & 0x3F;
1158 +
1159 + memcpy(op->buf, ictx->buffer, op->len);
1160 +
1161 + for (i = 0; i < 5; i++)
1162 + op->hash[i] = ictx->state[i];
1163 +
1164 + return 0;
1165 +}
1166 +
1167 +/*
1168 + * sun4i_hash_update: update hash engine
1169 + *
1170 + * Could be used for both SHA1 and MD5
1171 + * Write data by step of 32bits and put then in the SS.
1172 + *
1173 + * Since we cannot leave partial data and hash state in the engine,
1174 + * we need to get the hash state at the end of this function.
1175 + * We can get the hash state every 64 bytes
1176 + *
1177 + * So the first work is to get the number of bytes to write to SS modulo 64
1178 + * The extra bytes will go to a temporary buffer op->buf storing op->len bytes
1179 + *
1180 + * So at the begin of update()
1181 + * if op->len + areq->nbytes < 64
1182 + * => all data will be written to wait buffer (op->buf) and end=0
1183 + * if not, write all data from op->buf to the device and position end to
1184 + * complete to 64bytes
1185 + *
1186 + * example 1:
1187 + * update1 60o => op->len=60
1188 + * update2 60o => need one more word to have 64 bytes
1189 + * end=4
1190 + * so write all data from op->buf and one word of SGs
1191 + * write remaining data in op->buf
1192 + * final state op->len=56
1193 + */
1194 +int sun4i_hash_update(struct ahash_request *areq)
1195 +{
1196 + u32 v, ivmode = 0;
1197 + unsigned int i = 0;
1198 + /*
1199 + * i is the total bytes read from SGs, to be compared to areq->nbytes
1200 + * i is important because we cannot rely on SG length since the sum of
1201 + * SG->length could be greater than areq->nbytes
1202 + */
1203 +
1204 + struct sun4i_req_ctx *op = ahash_request_ctx(areq);
1205 + struct sun4i_ss_ctx *ss = op->ss;
1206 + struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1207 + unsigned int in_i = 0; /* advancement in the current SG */
1208 + unsigned int end;
1209 + /*
1210 + * end is the position when we need to stop writing to the device,
1211 + * to be compared to i
1212 + */
1213 + int in_r, err = 0;
1214 + unsigned int todo;
1215 + u32 spaces, rx_cnt = SS_RX_DEFAULT;
1216 + size_t copied = 0;
1217 + struct sg_mapping_iter mi;
1218 +
1219 + dev_dbg(ss->dev, "%s %s bc=%llu len=%u mode=%x wl=%u h0=%0x",
1220 + __func__, crypto_tfm_alg_name(areq->base.tfm),
1221 + op->byte_count, areq->nbytes, op->mode,
1222 + op->len, op->hash[0]);
1223 +
1224 + if (areq->nbytes == 0)
1225 + return 0;
1226 +
1227 + /* protect against overflow */
1228 + if (areq->nbytes > UINT_MAX - op->len) {
1229 + dev_err(ss->dev, "Cannot process too large request\n");
1230 + return -EINVAL;
1231 + }
1232 +
1233 + if (op->len + areq->nbytes < 64) {
1234 + /* linearize data to op->buf */
1235 + copied = sg_pcopy_to_buffer(areq->src, sg_nents(areq->src),
1236 + op->buf + op->len, areq->nbytes, 0);
1237 + op->len += copied;
1238 + return 0;
1239 + }
1240 +
1241 + end = ((areq->nbytes + op->len) / 64) * 64 - op->len;
1242 +
1243 + if (end > areq->nbytes || areq->nbytes - end > 63) {
1244 + dev_err(ss->dev, "ERROR: Bound error %u %u\n",
1245 + end, areq->nbytes);
1246 + return -EINVAL;
1247 + }
1248 +
1249 + spin_lock_bh(&ss->slock);
1250 +
1251 + /*
1252 + * if some data have been processed before,
1253 + * we need to restore the partial hash state
1254 + */
1255 + if (op->byte_count > 0) {
1256 + ivmode = SS_IV_ARBITRARY;
1257 + for (i = 0; i < 5; i++)
1258 + writel(op->hash[i], ss->base + SS_IV0 + i * 4);
1259 + }
1260 + /* Enable the device */
1261 + writel(op->mode | SS_ENABLED | ivmode, ss->base + SS_CTL);
1262 +
1263 + i = 0;
1264 + sg_miter_start(&mi, areq->src, sg_nents(areq->src),
1265 + SG_MITER_FROM_SG | SG_MITER_ATOMIC);
1266 + sg_miter_next(&mi);
1267 + in_i = 0;
1268 +
1269 + do {
1270 + /*
1271 + * we need to linearize in two case:
1272 + * - the buffer is already used
1273 + * - the SG does not have enough byte remaining ( < 4)
1274 + */
1275 + if (op->len > 0 || (mi.length - in_i) < 4) {
1276 + /*
1277 + * if we have entered here we have two reason to stop
1278 + * - the buffer is full
1279 + * - reach the end
1280 + */
1281 + while (op->len < 64 && i < end) {
1282 + /* how many bytes we can read from current SG */
1283 + in_r = min3(mi.length - in_i, end - i,
1284 + 64 - op->len);
1285 + memcpy(op->buf + op->len, mi.addr + in_i, in_r);
1286 + op->len += in_r;
1287 + i += in_r;
1288 + in_i += in_r;
1289 + if (in_i == mi.length) {
1290 + sg_miter_next(&mi);
1291 + in_i = 0;
1292 + }
1293 + }
1294 + if (op->len > 3 && (op->len % 4) == 0) {
1295 + /* write buf to the device */
1296 + writesl(ss->base + SS_RXFIFO, op->buf,
1297 + op->len / 4);
1298 + op->byte_count += op->len;
1299 + op->len = 0;
1300 + }
1301 + }
1302 + if (mi.length - in_i > 3 && i < end) {
1303 + /* how many bytes we can read from current SG */
1304 + in_r = min3(mi.length - in_i, areq->nbytes - i,
1305 + ((mi.length - in_i) / 4) * 4);
1306 + /* how many bytes we can write in the device*/
1307 + todo = min3((u32)(end - i) / 4, rx_cnt, (u32)in_r / 4);
1308 + writesl(ss->base + SS_RXFIFO, mi.addr + in_i, todo);
1309 + op->byte_count += todo * 4;
1310 + i += todo * 4;
1311 + in_i += todo * 4;
1312 + rx_cnt -= todo;
1313 + if (rx_cnt == 0) {
1314 + spaces = readl(ss->base + SS_FCSR);
1315 + rx_cnt = SS_RXFIFO_SPACES(spaces);
1316 + }
1317 + if (in_i == mi.length) {
1318 + sg_miter_next(&mi);
1319 + in_i = 0;
1320 + }
1321 + }
1322 + } while (i < end);
1323 + /* final linear */
1324 + if ((areq->nbytes - i) < 64) {
1325 + while (i < areq->nbytes && in_i < mi.length && op->len < 64) {
1326 + /* how many bytes we can read from current SG */
1327 + in_r = min3(mi.length - in_i, areq->nbytes - i,
1328 + 64 - op->len);
1329 + memcpy(op->buf + op->len, mi.addr + in_i, in_r);
1330 + op->len += in_r;
1331 + i += in_r;
1332 + in_i += in_r;
1333 + if (in_i == mi.length) {
1334 + sg_miter_next(&mi);
1335 + in_i = 0;
1336 + }
1337 + }
1338 + }
1339 +
1340 + sg_miter_stop(&mi);
1341 +
1342 + writel(op->mode | SS_ENABLED | SS_DATA_END, ss->base + SS_CTL);
1343 + i = 0;
1344 + do {
1345 + v = readl(ss->base + SS_CTL);
1346 + i++;
1347 + } while (i < SS_TIMEOUT && (v & SS_DATA_END) > 0);
1348 + if (i >= SS_TIMEOUT) {
1349 + dev_err_ratelimited(ss->dev,
1350 + "ERROR: hash end timeout %d>%d ctl=%x len=%u\n",
1351 + i, SS_TIMEOUT, v, areq->nbytes);
1352 + err = -EIO;
1353 + goto release_ss;
1354 + }
1355 +
1356 + /* get the partial hash only if something was written */
1357 + for (i = 0; i < crypto_ahash_digestsize(tfm) / 4; i++)
1358 + op->hash[i] = readl(ss->base + SS_MD0 + i * 4);
1359 +
1360 +release_ss:
1361 + writel(0, ss->base + SS_CTL);
1362 + spin_unlock_bh(&ss->slock);
1363 + return err;
1364 +}
1365 +
1366 +/*
1367 + * sun4i_hash_final: finalize hashing operation
1368 + *
1369 + * If we have some remaining bytes, we write them.
1370 + * Then ask the SS for finalizing the hashing operation
1371 + *
1372 + * I do not check RX FIFO size in this function since the size is 32
1373 + * after each enabling and this function neither write more than 32 words.
1374 + */
1375 +int sun4i_hash_final(struct ahash_request *areq)
1376 +{
1377 + u32 v, ivmode = 0;
1378 + unsigned int i;
1379 + unsigned int j = 0;
1380 + int zeros, err = 0;
1381 + unsigned int index, padlen;
1382 + __be64 bits;
1383 + struct sun4i_req_ctx *op = ahash_request_ctx(areq);
1384 + struct sun4i_ss_ctx *ss = op->ss;
1385 + struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1386 + u32 bf[32];
1387 + u32 wb = 0;
1388 + unsigned int nwait, nbw = 0;
1389 +
1390 + dev_dbg(ss->dev, "%s: byte=%llu len=%u mode=%x wl=%u h=%x",
1391 + __func__, op->byte_count, areq->nbytes, op->mode,
1392 + op->len, op->hash[0]);
1393 +
1394 + spin_lock_bh(&ss->slock);
1395 +
1396 + /*
1397 + * if we have already written something,
1398 + * restore the partial hash state
1399 + */
1400 + if (op->byte_count > 0) {
1401 + ivmode = SS_IV_ARBITRARY;
1402 + for (i = 0; i < crypto_ahash_digestsize(tfm) / 4; i++)
1403 + writel(op->hash[i], ss->base + SS_IV0 + i * 4);
1404 + }
1405 + writel(op->mode | SS_ENABLED | ivmode, ss->base + SS_CTL);
1406 +
1407 + /* write the remaining words of the wait buffer */
1408 + if (op->len > 0) {
1409 + nwait = op->len / 4;
1410 + if (nwait > 0) {
1411 + writesl(ss->base + SS_RXFIFO, op->buf, nwait);
1412 + op->byte_count += 4 * nwait;
1413 + }
1414 + nbw = op->len - 4 * nwait;
1415 + wb = *(u32 *)(op->buf + nwait * 4);
1416 + wb &= (0xFFFFFFFF >> (4 - nbw) * 8);
1417 + }
1418 +
1419 + /* write the remaining bytes of the nbw buffer */
1420 + if (nbw > 0) {
1421 + wb |= ((1 << 7) << (nbw * 8));
1422 + bf[j++] = wb;
1423 + } else {
1424 + bf[j++] = 1 << 7;
1425 + }
1426 +
1427 + /*
1428 + * number of space to pad to obtain 64o minus 8(size) minus 4 (final 1)
1429 + * I take the operations from other MD5/SHA1 implementations
1430 + */
1431 +
1432 + /* we have already send 4 more byte of which nbw data */
1433 + if (op->mode == SS_OP_MD5) {
1434 + index = (op->byte_count + 4) & 0x3f;
1435 + op->byte_count += nbw;
1436 + if (index > 56)
1437 + zeros = (120 - index) / 4;
1438 + else
1439 + zeros = (56 - index) / 4;
1440 + } else {
1441 + op->byte_count += nbw;
1442 + index = op->byte_count & 0x3f;
1443 + padlen = (index < 56) ? (56 - index) : ((64 + 56) - index);
1444 + zeros = (padlen - 1) / 4;
1445 + }
1446 +
1447 + memset(bf + j, 0, 4 * zeros);
1448 + j += zeros;
1449 +
1450 + /* write the length of data */
1451 + if (op->mode == SS_OP_SHA1) {
1452 + bits = cpu_to_be64(op->byte_count << 3);
1453 + bf[j++] = bits & 0xffffffff;
1454 + bf[j++] = (bits >> 32) & 0xffffffff;
1455 + } else {
1456 + bf[j++] = (op->byte_count << 3) & 0xffffffff;
1457 + bf[j++] = (op->byte_count >> 29) & 0xffffffff;
1458 + }
1459 + writesl(ss->base + SS_RXFIFO, bf, j);
1460 +
1461 + /* Tell the SS to stop the hashing */
1462 + writel(op->mode | SS_ENABLED | SS_DATA_END, ss->base + SS_CTL);
1463 +
1464 + /*
1465 + * Wait for SS to finish the hash.
1466 + * The timeout could happen only in case of bad overcloking
1467 + * or driver bug.
1468 + */
1469 + i = 0;
1470 + do {
1471 + v = readl(ss->base + SS_CTL);
1472 + i++;
1473 + } while (i < SS_TIMEOUT && (v & SS_DATA_END) > 0);
1474 + if (i >= SS_TIMEOUT) {
1475 + dev_err_ratelimited(ss->dev,
1476 + "ERROR: hash end timeout %d>%d ctl=%x len=%u\n",
1477 + i, SS_TIMEOUT, v, areq->nbytes);
1478 + err = -EIO;
1479 + goto release_ss;
1480 + }
1481 +
1482 + /* Get the hash from the device */
1483 + if (op->mode == SS_OP_SHA1) {
1484 + for (i = 0; i < 5; i++) {
1485 + v = cpu_to_be32(readl(ss->base + SS_MD0 + i * 4));
1486 + memcpy(areq->result + i * 4, &v, 4);
1487 + }
1488 + } else {
1489 + for (i = 0; i < 4; i++) {
1490 + v = readl(ss->base + SS_MD0 + i * 4);
1491 + memcpy(areq->result + i * 4, &v, 4);
1492 + }
1493 + }
1494 +
1495 +release_ss:
1496 + writel(0, ss->base + SS_CTL);
1497 + spin_unlock_bh(&ss->slock);
1498 + return err;
1499 +}
1500 +
1501 +/* sun4i_hash_finup: finalize hashing operation after an update */
1502 +int sun4i_hash_finup(struct ahash_request *areq)
1503 +{
1504 + int err;
1505 +
1506 + err = sun4i_hash_update(areq);
1507 + if (err != 0)
1508 + return err;
1509 +
1510 + return sun4i_hash_final(areq);
1511 +}
1512 +
1513 +/* combo of init/update/final functions */
1514 +int sun4i_hash_digest(struct ahash_request *areq)
1515 +{
1516 + int err;
1517 +
1518 + err = sun4i_hash_init(areq);
1519 + if (err != 0)
1520 + return err;
1521 +
1522 + err = sun4i_hash_update(areq);
1523 + if (err != 0)
1524 + return err;
1525 +
1526 + return sun4i_hash_final(areq);
1527 +}
1528 diff --git a/drivers/crypto/sunxi-ss/sun4i-ss.h b/drivers/crypto/sunxi-ss/sun4i-ss.h
1529 new file mode 100644
1530 index 0000000..db18b255
1531 --- /dev/null
1532 +++ b/drivers/crypto/sunxi-ss/sun4i-ss.h
1533 @@ -0,0 +1,199 @@
1534 +/*
1535 + * sun4i-ss.h - hardware cryptographic accelerator for Allwinner A20 SoC
1536 + *
1537 + * Copyright (C) 2013-2015 Corentin LABBE <clabbe.montjoie@gmail.com>
1538 + *
1539 + * Support AES cipher with 128,192,256 bits keysize.
1540 + * Support MD5 and SHA1 hash algorithms.
1541 + * Support DES and 3DES
1542 + *
1543 + * You could find the datasheet in Documentation/arm/sunxi/README
1544 + *
1545 + * Licensed under the GPL-2.
1546 + */
1547 +
1548 +#include <linux/clk.h>
1549 +#include <linux/crypto.h>
1550 +#include <linux/io.h>
1551 +#include <linux/module.h>
1552 +#include <linux/of.h>
1553 +#include <linux/platform_device.h>
1554 +#include <crypto/scatterwalk.h>
1555 +#include <linux/scatterlist.h>
1556 +#include <linux/interrupt.h>
1557 +#include <linux/delay.h>
1558 +#include <crypto/md5.h>
1559 +#include <crypto/sha.h>
1560 +#include <crypto/hash.h>
1561 +#include <crypto/internal/hash.h>
1562 +#include <crypto/aes.h>
1563 +#include <crypto/des.h>
1564 +#include <crypto/internal/rng.h>
1565 +
1566 +#define SS_CTL 0x00
1567 +#define SS_KEY0 0x04
1568 +#define SS_KEY1 0x08
1569 +#define SS_KEY2 0x0C
1570 +#define SS_KEY3 0x10
1571 +#define SS_KEY4 0x14
1572 +#define SS_KEY5 0x18
1573 +#define SS_KEY6 0x1C
1574 +#define SS_KEY7 0x20
1575 +
1576 +#define SS_IV0 0x24
1577 +#define SS_IV1 0x28
1578 +#define SS_IV2 0x2C
1579 +#define SS_IV3 0x30
1580 +
1581 +#define SS_FCSR 0x44
1582 +
1583 +#define SS_MD0 0x4C
1584 +#define SS_MD1 0x50
1585 +#define SS_MD2 0x54
1586 +#define SS_MD3 0x58
1587 +#define SS_MD4 0x5C
1588 +
1589 +#define SS_RXFIFO 0x200
1590 +#define SS_TXFIFO 0x204
1591 +
1592 +/* SS_CTL configuration values */
1593 +
1594 +/* PRNG generator mode - bit 15 */
1595 +#define SS_PRNG_ONESHOT (0 << 15)
1596 +#define SS_PRNG_CONTINUE (1 << 15)
1597 +
1598 +/* IV mode for hash */
1599 +#define SS_IV_ARBITRARY (1 << 14)
1600 +
1601 +/* SS operation mode - bits 12-13 */
1602 +#define SS_ECB (0 << 12)
1603 +#define SS_CBC (1 << 12)
1604 +#define SS_CTS (3 << 12)
1605 +
1606 +/* Counter width for CNT mode - bits 10-11 */
1607 +#define SS_CNT_16BITS (0 << 10)
1608 +#define SS_CNT_32BITS (1 << 10)
1609 +#define SS_CNT_64BITS (2 << 10)
1610 +
1611 +/* Key size for AES - bits 8-9 */
1612 +#define SS_AES_128BITS (0 << 8)
1613 +#define SS_AES_192BITS (1 << 8)
1614 +#define SS_AES_256BITS (2 << 8)
1615 +
1616 +/* Operation direction - bit 7 */
1617 +#define SS_ENCRYPTION (0 << 7)
1618 +#define SS_DECRYPTION (1 << 7)
1619 +
1620 +/* SS Method - bits 4-6 */
1621 +#define SS_OP_AES (0 << 4)
1622 +#define SS_OP_DES (1 << 4)
1623 +#define SS_OP_3DES (2 << 4)
1624 +#define SS_OP_SHA1 (3 << 4)
1625 +#define SS_OP_MD5 (4 << 4)
1626 +#define SS_OP_PRNG (5 << 4)
1627 +
1628 +/* Data end bit - bit 2 */
1629 +#define SS_DATA_END (1 << 2)
1630 +
1631 +/* PRNG start bit - bit 1 */
1632 +#define SS_PRNG_START (1 << 1)
1633 +
1634 +/* SS Enable bit - bit 0 */
1635 +#define SS_DISABLED (0 << 0)
1636 +#define SS_ENABLED (1 << 0)
1637 +
1638 +/* SS_FCSR configuration values */
1639 +/* RX FIFO status - bit 30 */
1640 +#define SS_RXFIFO_FREE (1 << 30)
1641 +
1642 +/* RX FIFO empty spaces - bits 24-29 */
1643 +#define SS_RXFIFO_SPACES(val) (((val) >> 24) & 0x3f)
1644 +
1645 +/* TX FIFO status - bit 22 */
1646 +#define SS_TXFIFO_AVAILABLE (1 << 22)
1647 +
1648 +/* TX FIFO available spaces - bits 16-21 */
1649 +#define SS_TXFIFO_SPACES(val) (((val) >> 16) & 0x3f)
1650 +
1651 +#define SS_RX_MAX 32
1652 +#define SS_RX_DEFAULT SS_RX_MAX
1653 +#define SS_TX_MAX 33
1654 +
1655 +#define SS_RXFIFO_EMP_INT_PENDING (1 << 10)
1656 +#define SS_TXFIFO_AVA_INT_PENDING (1 << 8)
1657 +#define SS_RXFIFO_EMP_INT_ENABLE (1 << 2)
1658 +#define SS_TXFIFO_AVA_INT_ENABLE (1 << 0)
1659 +
1660 +struct sun4i_ss_ctx {
1661 + void __iomem *base;
1662 + int irq;
1663 + struct clk *busclk;
1664 + struct clk *ssclk;
1665 + struct device *dev;
1666 + struct resource *res;
1667 + spinlock_t slock; /* control the use of the device */
1668 +};
1669 +
1670 +struct sun4i_ss_alg_template {
1671 + u32 type;
1672 + u32 mode;
1673 + union {
1674 + struct crypto_alg crypto;
1675 + struct ahash_alg hash;
1676 + } alg;
1677 + struct sun4i_ss_ctx *ss;
1678 +};
1679 +
1680 +struct sun4i_tfm_ctx {
1681 + u32 key[AES_MAX_KEY_SIZE / 4];/* divided by sizeof(u32) */
1682 + u32 keylen;
1683 + u32 keymode;
1684 + struct sun4i_ss_ctx *ss;
1685 +};
1686 +
1687 +struct sun4i_cipher_req_ctx {
1688 + u32 mode;
1689 +};
1690 +
1691 +struct sun4i_req_ctx {
1692 + u32 mode;
1693 + u64 byte_count; /* number of bytes "uploaded" to the device */
1694 + u32 hash[5]; /* for storing SS_IVx register */
1695 + char buf[64];
1696 + unsigned int len;
1697 + struct sun4i_ss_ctx *ss;
1698 +};
1699 +
1700 +int sun4i_hash_crainit(struct crypto_tfm *tfm);
1701 +int sun4i_hash_init(struct ahash_request *areq);
1702 +int sun4i_hash_update(struct ahash_request *areq);
1703 +int sun4i_hash_final(struct ahash_request *areq);
1704 +int sun4i_hash_finup(struct ahash_request *areq);
1705 +int sun4i_hash_digest(struct ahash_request *areq);
1706 +int sun4i_hash_export_md5(struct ahash_request *areq, void *out);
1707 +int sun4i_hash_import_md5(struct ahash_request *areq, const void *in);
1708 +int sun4i_hash_export_sha1(struct ahash_request *areq, void *out);
1709 +int sun4i_hash_import_sha1(struct ahash_request *areq, const void *in);
1710 +
1711 +int sun4i_ss_cbc_aes_encrypt(struct ablkcipher_request *areq);
1712 +int sun4i_ss_cbc_aes_decrypt(struct ablkcipher_request *areq);
1713 +int sun4i_ss_ecb_aes_encrypt(struct ablkcipher_request *areq);
1714 +int sun4i_ss_ecb_aes_decrypt(struct ablkcipher_request *areq);
1715 +
1716 +int sun4i_ss_cbc_des_encrypt(struct ablkcipher_request *areq);
1717 +int sun4i_ss_cbc_des_decrypt(struct ablkcipher_request *areq);
1718 +int sun4i_ss_ecb_des_encrypt(struct ablkcipher_request *areq);
1719 +int sun4i_ss_ecb_des_decrypt(struct ablkcipher_request *areq);
1720 +
1721 +int sun4i_ss_cbc_des3_encrypt(struct ablkcipher_request *areq);
1722 +int sun4i_ss_cbc_des3_decrypt(struct ablkcipher_request *areq);
1723 +int sun4i_ss_ecb_des3_encrypt(struct ablkcipher_request *areq);
1724 +int sun4i_ss_ecb_des3_decrypt(struct ablkcipher_request *areq);
1725 +
1726 +int sun4i_ss_cipher_init(struct crypto_tfm *tfm);
1727 +int sun4i_ss_aes_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
1728 + unsigned int keylen);
1729 +int sun4i_ss_des_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
1730 + unsigned int keylen);
1731 +int sun4i_ss_des3_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
1732 + unsigned int keylen);
OpenWrt SVN history