target/linux/sunxi/patches-4.19/010-v5.3-drivers-ata-ahci_sunxi-Increased-SATA-AHCI-DMA-TX-RX.patch

   1 From 120357ea176e420d313cf8cf2ff35fbe233d3bab Mon Sep 17 00:00:00 2001
   2 From: Uenal Mutlu <um@mutluit.com>
   3 Date: Mon, 13 May 2019 16:24:10 +0200
   4 Subject: [PATCH] drivers: ata: ahci_sunxi: Increased SATA/AHCI DMA TX/RX FIFOs
   5
   6 Increasing the SATA/AHCI DMA TX/RX FIFOs (P0DMACR.TXTS and .RXTS, ie.
   7 TX_TRANSACTION_SIZE and RX_TRANSACTION_SIZE) from default 0x0 each
   8 to 0x3 each, gives a write performance boost of 120 MiB/s to 132 MiB/s
   9 from lame 36 MiB/s to 45 MiB/s previously.
  10 Read performance is above 200 MiB/s.
  11 [tested on SSD using dd bs=4K/8K/12K/16K/20K/24K/32K: peak-perf at 12K]
  12
  13 Tested on the SBCs Banana Pi R1 (aka Lamobo R1) and Banana Pi M1 which
  14 are based on the Allwinner A20 32bit-SoC (ARMv7-a / arm-linux-gnueabihf).
  15 These devices are RaspberryPi-like small devices.
  16
  17 This problem of slow SATA write-speed with these small devices lasts
  18 for about 7 years now (beginning with the A10 SoC). Many commentators
  19 throughout the years wrongly assumed the slow write speed was a
  20 hardware limitation. This patch finally solves the problem, which
  21 in fact was just a hard-to-find software problem due to lack of
  22 SATA/AHCI documentation by the SoC-maker Allwinner Technology.
  23
  24 Lists of the affected sunxi and other boards and SoCs with SATA using
  25 the ahci_sunxi driver:
  26   $ grep -i -e "^&ahci" arch/arm/boot/dts/sun*dts
  27   and http://linux-sunxi.org/SATA#Devices_with_SATA_ports
  28   See also http://linux-sunxi.org/Category:Devices_with_SATA_port
  29
  30 Tested-by: Chen-Yu Tsai <wens@csie.org>
  31 Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
  32 Reviewed-by: Hans de Goede <hdegoede@redhat.com>
  33 Signed-off-by: Uenal Mutlu <um@mutluit.com>
  34 Signed-off-by: Jens Axboe <axboe@kernel.dk>
  35 ---
  36  drivers/ata/ahci_sunxi.c | 47 ++++++++++++++++++++++++++++++++++++++--
  37  1 file changed, 45 insertions(+), 2 deletions(-)
  38
  39 --- a/drivers/ata/ahci_sunxi.c
  40 +++ b/drivers/ata/ahci_sunxi.c
  41 @@ -157,8 +157,51 @@ static void ahci_sunxi_start_engine(stru
  42         void __iomem *port_mmio = ahci_port_base(ap);
  43         struct ahci_host_priv *hpriv = ap->host->private_data;
  44
  45 -       /* Setup DMA before DMA start */
  46 -       sunxi_clrsetbits(hpriv->mmio + AHCI_P0DMACR, 0x0000ff00, 0x00004400);
  47 +       /* Setup DMA before DMA start
  48 +        *
  49 +        * NOTE: A similar SoC with SATA/AHCI by Texas Instruments documents
  50 +        *   this Vendor Specific Port (P0DMACR, aka PxDMACR) in its
  51 +        *   User's Guide document (TMS320C674x/OMAP-L1x Processor
  52 +        *   Serial ATA (SATA) Controller, Literature Number: SPRUGJ8C,
  53 +        *   March 2011, Chapter 4.33 Port DMA Control Register (P0DMACR),
  54 +        *   p.68, https://www.ti.com/lit/ug/sprugj8c/sprugj8c.pdf)
  55 +        *   as equivalent to the following struct:
  56 +        *
  57 +        *   struct AHCI_P0DMACR_t
  58 +        *   {
  59 +        *     unsigned TXTS     : 4;
  60 +        *     unsigned RXTS     : 4;
  61 +        *     unsigned TXABL    : 4;
  62 +        *     unsigned RXABL    : 4;
  63 +        *     unsigned Reserved : 16;
  64 +        *   };
  65 +        *
  66 +        *   TXTS: Transmit Transaction Size (TX_TRANSACTION_SIZE).
  67 +        *     This field defines the DMA transaction size in DWORDs for
  68 +        *     transmit (system bus read, device write) operation. [...]
  69 +        *
  70 +        *   RXTS: Receive Transaction Size (RX_TRANSACTION_SIZE).
  71 +        *     This field defines the Port DMA transaction size in DWORDs
  72 +        *     for receive (system bus write, device read) operation. [...]
  73 +        *
  74 +        *   TXABL: Transmit Burst Limit.
  75 +        *     This field allows software to limit the VBUSP master read
  76 +        *     burst size. [...]
  77 +        *
  78 +        *   RXABL: Receive Burst Limit.
  79 +        *     Allows software to limit the VBUSP master write burst
  80 +        *     size. [...]
  81 +        *
  82 +        *   Reserved: Reserved.
  83 +        *
  84 +        *
  85 +        * NOTE: According to the above document, the following alternative
  86 +        *   to the code below could perhaps be a better option
  87 +        *   (or preparation) for possible further improvements later:
  88 +        *     sunxi_clrsetbits(hpriv->mmio + AHCI_P0DMACR, 0x0000ffff,
  89 +        *              0x00000033);
  90 +        */
  91 +       sunxi_clrsetbits(hpriv->mmio + AHCI_P0DMACR, 0x0000ffff, 0x00004433);
  92
  93         /* Start DMA */
  94         sunxi_setbits(port_mmio + PORT_CMD, PORT_CMD_START);