Add Broadcom / Netgear changes from RAXE 1.0.0.48

[project/bcm63xx/u-boot.git] / arch / arm / include / asm / arch-bcm47622 / ethsw.h

diff --git a/arch/arm/include/asm/arch-bcm47622/ethsw.h b/arch/arm/include/asm/arch-bcm47622/ethsw.h
new file mode 100644 (file)
index 0000000..d871bfc
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm47622/ethsw.h
@@ -0,0 +1,40 @@
+
+#define ETHSW_QPHY_CTRL_PHYAD_BASE_SHIFT     12
+#define ETHSW_QPHY_CTRL_PHYAD_BASE_MASK      (0x1f<<ETHSW_QPHY_CTRL_PHYAD_BASE_SHIFT)
+#define ETHSW_QPHY_CTRL_RESET_SHIFT          8
+#define ETHSW_QPHY_CTRL_RESET_MASK           (0x1<<ETHSW_QPHY_CTRL_RESET_SHIFT )
+#define ETHSW_QPHY_CTRL_CK25_DIS_SHIFT       7
+#define ETHSW_QPHY_CTRL_CK25_DIS_MASK        (0x1<<ETHSW_QPHY_CTRL_CK25_DIS_SHIFT)
+#define ETHSW_QPHY_CTRL_EXT_PWR_DOWN_SHIFT   1
+#define ETHSW_QPHY_CTRL_EXT_PWR_DOWN_MASK    (0xf<<ETHSW_QPHY_CTRL_EXT_PWR_DOWN_SHIFT)
+#define ETHSW_QPHY_CTRL_IDDQ_BIAS_SHIFT      0
+#define ETHSW_QPHY_CTRL_IDDQ_BIAS_MASK       (0x1<<ETHSW_QPHY_CTRL_IDDQ_BIAS_SHIFT)
+#define ETHSW_QPHY_CTRL_IDDQ_GLOBAL_PWR_SHIFT      6
+#define ETHSW_QPHY_CTRL_IDDQ_GLOBAL_PWR_MASK       (0x1<<ETHSW_QPHY_CTRL_IDDQ_GLOBAL_PWR_SHIFT)
+
+#define ETHSW_SPHY_CTRL_PHYAD_SHIFT          8
+#define ETHSW_SPHY_CTRL_PHYAD_MASK           (0x1f<<ETHSW_SPHY_CTRL_PHYAD_SHIFT)
+#define ETHSW_SPHY_CTRL_RESET_SHIFT          5
+#define ETHSW_SPHY_CTRL_RESET_MASK           (0x1<<ETHSW_SPHY_CTRL_RESET_SHIFT )
+#define ETHSW_SPHY_CTRL_CK25_DIS_SHIFT       4
+#define ETHSW_SPHY_CTRL_CK25_DIS_MASK        (0x1<<ETHSW_SPHY_CTRL_CK25_DIS_SHIFT)
+#define ETHSW_SPHY_CTRL_EXT_PWR_DOWN_SHIFT   1
+#define ETHSW_SPHY_CTRL_EXT_PWR_DOWN_MASK    (0x1<<ETHSW_SPHY_CTRL_EXT_PWR_DOWN_SHIFT)
+#define ETHSW_SPHY_CTRL_IDDQ_BIAS_SHIFT      0
+#define ETHSW_SPHY_CTRL_IDDQ_BIAS_MASK       (0x1<<ETHSW_SPHY_CTRL_IDDQ_BIAS_SHIFT)
+#define ETHSW_SPHY_CTRL_IDDQ_GLOBAL_PWR_SHIFT      3
+#define ETHSW_SPHY_CTRL_IDDQ_GLOBAL_PWR_MASK       (0x1<<ETHSW_SPHY_CTRL_IDDQ_GLOBAL_PWR_SHIFT)
+
+#define ETHSW_MDIO_BUSY                       (1 << 29)
+#define ETHSW_MDIO_FAIL                       (1 << 28)
+#define ETHSW_MDIO_CMD_SHIFT                  26
+#define ETHSW_MDIO_CMD_MASK                   (0x3<<ETHSW_MDIO_CMD_SHIFT) 
+#define ETHSW_MDIO_CMD_C22_READ               2
+#define ETHSW_MDIO_CMD_C22_WRITE              1
+#define ETHSW_MDIO_C22_PHY_ADDR_SHIFT         21
+#define ETHSW_MDIO_C22_PHY_ADDR_MASK          (0x1f<<ETHSW_MDIO_C22_PHY_ADDR_SHIFT)
+#define ETHSW_MDIO_C22_PHY_REG_SHIFT          16
+#define ETHSW_MDIO_C22_PHY_REG_MASK           (0x1f<<ETHSW_MDIO_C22_PHY_REG_SHIFT)
+#define ETHSW_MDIO_PHY_DATA_SHIFT             0
+#define ETHSW_MDIO_PHY_DATA_MASK              (0xffff<<ETHSW_MDIO_PHY_DATA_SHIFT)
+