Add Broadcom / Netgear changes from RAXE 1.0.0.48

[project/bcm63xx/u-boot.git] / arch / arm / include / asm / arch-bcm6756 / pmc_addr.h

diff --git a/arch/arm/include/asm/arch-bcm6756/pmc_addr.h b/arch/arm/include/asm/arch-bcm6756/pmc_addr.h
new file mode 100644 (file)
index 0000000..5d940c8
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm6756/pmc_addr.h
@@ -0,0 +1,107 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 Broadcom
+ */
+/*
+ 
+*/
+
+#ifndef PMC_ADDR_6756_H__
+#define PMC_ADDR_6756_H__
+
+#define PMB_BUS_ID_SHIFT         12
+
+#define PMB_BUS_PERIPH           1
+#define PMB_ADDR_PERIPH          (16 | PMB_BUS_PERIPH << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PERIPH         4
+
+#define PMB_BUS_CRYPTO           0
+#define PMB_ADDR_CRYPTO          (1 | PMB_BUS_CRYPTO << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_CRYPTO         1
+
+#define PMB_BUS_PVTMON           0
+#define PMB_ADDR_PVTMON          (2 | PMB_BUS_PVTMON << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PVTMON         0
+
+#define PMB_BUS_CHIP_CLKRST      0
+#define PMB_ADDR_CHIP_CLKRST     (3 | PMB_BUS_CHIP_CLKRST << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_CHIP_CLKRST    0
+
+#define PMB_BUS_USB31_20         0
+#define PMB_ADDR_USB31_20        (4 | PMB_BUS_USB31_20 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_USB31_20       4
+
+#define PMB_BUS_WLAN0            0
+#define PMB_ADDR_WLAN0           (5 | PMB_BUS_WLAN0 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_WLAN0          1
+
+#define PMB_BUS_WLAN0_PHY1       0
+#define PMB_ADDR_WLAN0_PHY1      (6 | PMB_BUS_WLAN0_PHY1 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_WLAN0_PHY1     1
+
+#define PMB_BUS_WLAN0_PHY2       0
+#define PMB_ADDR_WLAN0_PHY2      (7 | PMB_BUS_WLAN0_PHY2 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_WLAN0_PHY2     1
+
+#define PMB_BUS_WLAN1            0
+#define PMB_ADDR_WLAN1           (8 | PMB_BUS_WLAN1 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_WLAN1          1
+
+#define PMB_BUS_WLAN1_PHY1       0
+#define PMB_ADDR_WLAN1_PHY1      (9 | PMB_BUS_WLAN1_PHY1 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_WLAN1_PHY1     1
+
+#define PMB_BUS_WLAN1_PHY2       0
+#define PMB_ADDR_WLAN1_PHY2      (10 | PMB_BUS_WLAN1_PHY2 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_WLAN1_PHY2     1
+
+#define PMB_BUS_MEMC             0
+#define PMB_ADDR_MEMC            (11 | PMB_BUS_MEMC << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_MEMC           1
+
+#define PMB_BUS_SWITCH           0
+#define PMB_ADDR_SWITCH          (12 | PMB_BUS_SWITCH << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_SWITCH         5
+
+#define PMB_BUS_PCIE0            1
+#define PMB_ADDR_PCIE0           (17 | PMB_BUS_PCIE0 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PCIE0          1
+
+#define PMB_BUS_ORION_CPU0       0
+#define PMB_ADDR_ORION_CPU0      (32 | PMB_BUS_ORION_CPU0 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_ORION_CPU0     1
+
+#define PMB_BUS_ORION_CPU1       0
+#define PMB_ADDR_ORION_CPU1      (33 | PMB_BUS_ORION_CPU1 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_ORION_CPU1     1
+
+#define PMB_BUS_ORION_CPU2       0
+#define PMB_ADDR_ORION_CPU2      (34 | PMB_BUS_ORION_CPU2 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_ORION_CPU2     1
+
+#define PMB_BUS_ORION_CPU3       0
+#define PMB_ADDR_ORION_CPU3      (35 | PMB_BUS_ORION_CPU3 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_ORION_CPU3     1
+
+#define PMB_BUS_ORION_NONCPU     0
+#define PMB_ADDR_ORION_NONCPU    (36 | PMB_BUS_ORION_NONCPU << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_ORION_NONCPU   1
+
+#define PMB_BUS_BIU_PLL          0
+#define PMB_ADDR_BIU_PLL         (38 | PMB_BUS_BIU_PLL << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_BIU_PLL        0
+
+#define PMB_BUS_BIU_BPCM         0
+#define PMB_ADDR_BIU_BPCM        (39 | PMB_BUS_BIU_BPCM << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_BIU_BPCM       1
+
+#define RCAL_0P25UM_HORZ          0
+#define RCAL_0P25UM_VERT          1
+#define RCAL_0P5UM_HORZ           2
+#define RCAL_0P5UM_VERT           3
+#define RCAL_1UM_HORZ             4
+#define RCAL_1UM_VERT             5
+#define PMMISC_RMON_EXT_REG       ((RCAL_1UM_VERT + 1)/2)
+#define PMMISC_RMON_VALID_MASK    (0x1<<16)
+
+#endif