layerscape: add 64b/32b target for ls1012ardb device

[openwrt/staging/yousong.git] / package / boot / uboot-layerscape / patches / 0019-armv8-ls1012a-Add-CSU-assignment-for-eSDHC2-SAI1-SAI.patch

diff --git a/package/boot/uboot-layerscape/patches/0019-armv8-ls1012a-Add-CSU-assignment-for-eSDHC2-SAI1-SAI.patch b/package/boot/uboot-layerscape/patches/0019-armv8-ls1012a-Add-CSU-assignment-for-eSDHC2-SAI1-SAI.patch
new file mode 100644 (file)
index 0000000..9b3219f
--- /dev/null
+++ b/package/boot/uboot-layerscape/patches/0019-armv8-ls1012a-Add-CSU-assignment-for-eSDHC2-SAI1-SAI.patch
@@ -0,0 +1,50 @@
+From 8aad7c4c5d8becaf6c60e1585c8e70010b3c0ce2 Mon Sep 17 00:00:00 2001
+From: Makarand Pawagi <makarand.pawagi@mindspeed.com>
+Date: Mon, 2 May 2016 09:33:45 +0530
+Subject: [PATCH 19/93] armv8: ls1012a: Add CSU assignment for eSDHC2, SAI1,
+ SAI2, SAI3, SAI4
+
+    Access settings for different IPs has to be enabled through CSU registers. Following
+    IP's are added for LS1012A:
+    Added CSU ID for eSDHC-2, reg: CSL40_REG[23:16]
+    Added CSU ID for SAI-1, reg: CSL41_REG[7:0]
+    Added CSU ID for SAI-2, reg: CSL41_REG[23:16]
+    Added CSU ID for SAI-3, reg: CSL42_REG[7:0]
+    Added CSU ID for SAI-4, reg: CSL42_REG[23:16
+---
+ .../include/asm/arch-fsl-layerscape/ns_access.h    |   10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
+index a3ccdb0..d6642a7 100644
+--- a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
++++ b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
+@@ -69,7 +69,12 @@ enum csu_cslx_ind {
+       CSU_CSLX_IIC4 = 77,
+       CSU_CSLX_WDT4,
+       CSU_CSLX_WDT3,
++    CSU_CSLX_ESDHC2 = 80,
+       CSU_CSLX_WDT5 = 81,
++      CSU_CSLX_SAI2,
++      CSU_CSLX_SAI1,
++      CSU_CSLX_SAI4,
++      CSU_CSLX_SAI3,
+       CSU_CSLX_FTM2 = 86,
+       CSU_CSLX_FTM1,
+       CSU_CSLX_FTM4,
+@@ -143,7 +148,12 @@ static struct csu_ns_dev ns_dev[] = {
+        {CSU_CSLX_IIC4, CSU_ALL_RW},
+        {CSU_CSLX_WDT4, CSU_ALL_RW},
+        {CSU_CSLX_WDT3, CSU_ALL_RW},
++     {CSU_CSLX_ESDHC2, CSU_ALL_RW},
+        {CSU_CSLX_WDT5, CSU_ALL_RW},
++       {CSU_CSLX_SAI2, CSU_ALL_RW},
++       {CSU_CSLX_SAI1, CSU_ALL_RW},
++       {CSU_CSLX_SAI4, CSU_ALL_RW},
++       {CSU_CSLX_SAI3, CSU_ALL_RW},
+        {CSU_CSLX_FTM2, CSU_ALL_RW},
+        {CSU_CSLX_FTM1, CSU_ALL_RW},
+        {CSU_CSLX_FTM4, CSU_ALL_RW},
+-- 
+1.7.9.5
+