layerscape: add 64b/32b target for ls1012ardb device

[openwrt/staging/yousong.git] / package / boot / uboot-layerscape / patches / 0044-armv8-fsl-layerscape-Add-support-of-GPIO-structure.patch

diff --git a/package/boot/uboot-layerscape/patches/0044-armv8-fsl-layerscape-Add-support-of-GPIO-structure.patch b/package/boot/uboot-layerscape/patches/0044-armv8-fsl-layerscape-Add-support-of-GPIO-structure.patch
new file mode 100644 (file)
index 0000000..67af942
--- /dev/null
+++ b/package/boot/uboot-layerscape/patches/0044-armv8-fsl-layerscape-Add-support-of-GPIO-structure.patch
@@ -0,0 +1,48 @@
+From fe0ffa96c83e318d6b99fe31b5d121bdb05247f7 Mon Sep 17 00:00:00 2001
+From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+Date: Tue, 24 May 2016 14:52:59 +0530
+Subject: [PATCH 44/93] armv8: fsl-layerscape: Add support of GPIO structure
+
+[context adjustment]
+
+Layerscape supports GPIO registers to conrol GPIO singals.
+
+Add support of GPIO structure to enable GPIO access.
+
+Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+Integrated-by: Jiang Yutang <yutang.jiang@nxp.com>
+---
+ .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |   10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+index a264f9a..58c7205 100644
+--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
++++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+@@ -44,6 +44,7 @@
+ #define CONFIG_SYS_PPFE_ADDR                  (CONFIG_SYS_IMMR + 0x3000000)
+ #define CONFIG_SYS_SEC_MON_ADDR                       (CONFIG_SYS_IMMR + 0xe90000)
+ #define CONFIG_SYS_SFP_ADDR                   (CONFIG_SYS_IMMR + 0xe80200)
++#define CONFIG_SYS_GPIO1_ADDR                 (CONFIG_SYS_IMMR + 0x300000)
+ 
+ #define CONFIG_SYS_FSL_TIMER_ADDR             0x02b00000
+ 
+@@ -650,6 +651,15 @@ struct ccsr_cci400 {
+       u8 res_e004[0x10000 - 0xe004];
+ };
+ 
++typedef struct ccsr_gpio {
++      u32     gpdir;
++      u32     gpodr;
++      u32     gpdat;
++      u32     gpier;
++      u32     gpimr;
++      u32     gpicr;
++} ccsr_gpio_t;
++
+ /* MMU 500 */
+ #define SMMU_SCR0                     (SMMU_BASE + 0x0)
+ #define SMMU_SCR1                     (SMMU_BASE + 0x4)
+-- 
+1.7.9.5
+