uboot-sunxi: add T113-S3 support

[openwrt/staging/wigyori.git] / package / boot / uboot-sunxi / patches / 4017-sunxi-clock-D1-R528-Enable-PLL-LDO-during-PLL1-setup.patch

diff --git a/package/boot/uboot-sunxi/patches/4017-sunxi-clock-D1-R528-Enable-PLL-LDO-during-PLL1-setup.patch b/package/boot/uboot-sunxi/patches/4017-sunxi-clock-D1-R528-Enable-PLL-LDO-during-PLL1-setup.patch
new file mode 100644 (file)
index 0000000..c4f040e
--- /dev/null
+++ b/package/boot/uboot-sunxi/patches/4017-sunxi-clock-D1-R528-Enable-PLL-LDO-during-PLL1-setup.patch
@@ -0,0 +1,53 @@
+From 1b5b04c85989c73be3da502ce788e847b83f8e10 Mon Sep 17 00:00:00 2001
+From: Andre Przywara <andre.przywara@arm.com>
+Date: Fri, 21 Jul 2023 14:45:57 +0100
+Subject: [PATCH 4017/4052] sunxi: clock: D1/R528: Enable PLL LDO during PLL1
+ setup
+
+The D1/R528/T113s SoCs introduce a new "LDO enable" bit in the CPUX_PLL.
+Just enable that when we program that PLL.
+
+Signed-off-by: Andre Przywara <andre.przywara@arm.com>
+---
+ arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h |  1 +
+ arch/arm/mach-sunxi/clock_sun50i_h6.c             | 12 +++++++-----
+ 2 files changed, 8 insertions(+), 5 deletions(-)
+
+diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
+index 37df4410ea..9895c2c220 100644
+--- a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
++++ b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
+@@ -228,6 +228,7 @@ struct sunxi_ccm_reg {
+ 
+ /* pll1 bit field */
+ #define CCM_PLL1_CTRL_EN              BIT(31)
++#define CCM_PLL1_LDO_EN                       BIT(30)
+ #define CCM_PLL1_LOCK_EN              BIT(29)
+ #define CCM_PLL1_LOCK                 BIT(28)
+ #define CCM_PLL1_OUT_EN                       BIT(27)
+diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c
+index 7926394cf7..90110eab10 100644
+--- a/arch/arm/mach-sunxi/clock_sun50i_h6.c
++++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c
+@@ -86,11 +86,13 @@ void clock_set_pll1(unsigned int clk)
+       writel(val, &ccm->cpu_axi_cfg);
+ 
+       /* clk = 24*n/p, p is ignored if clock is >288MHz */
+-      writel(CCM_PLL1_CTRL_EN | CCM_PLL1_LOCK_EN | CCM_PLL1_CLOCK_TIME_2 |
+-#ifdef CONFIG_MACH_SUN50I_H616
+-             CCM_PLL1_OUT_EN |
+-#endif
+-             CCM_PLL1_CTRL_N(clk / 24000000), &ccm->pll1_cfg);
++      val = CCM_PLL1_CTRL_EN | CCM_PLL1_LOCK_EN | CCM_PLL1_CLOCK_TIME_2;
++      val |= CCM_PLL1_CTRL_N(clk / 24000000);
++      if (IS_ENABLED(CONFIG_MACH_SUN50I_H616))
++             val |= CCM_PLL1_OUT_EN;
++      if (IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2))
++             val |= CCM_PLL1_OUT_EN | CCM_PLL1_LDO_EN;
++      writel(val, &ccm->pll1_cfg);
+       while (!(readl(&ccm->pll1_cfg) & CCM_PLL1_LOCK)) {}
+ 
+       /* Switch CPU to PLL1 */
+-- 
+2.20.1
+