uboot-sunxi: t113: refresh patches to fix clock issues

[openwrt/staging/wigyori.git] / package / boot / uboot-sunxi / patches / 4020-sunxi-add-uart0_pins-on-Port-E-PE2-PE3-on-D1s-T133.patch

diff --git a/package/boot/uboot-sunxi/patches/4020-sunxi-add-uart0_pins-on-Port-E-PE2-PE3-on-D1s-T133.patch b/package/boot/uboot-sunxi/patches/4020-sunxi-add-uart0_pins-on-Port-E-PE2-PE3-on-D1s-T133.patch
deleted file mode 100644 (file)
index 3c26b0d..0000000
--- a/package/boot/uboot-sunxi/patches/4020-sunxi-add-uart0_pins-on-Port-E-PE2-PE3-on-D1s-T133.patch
+++ /dev/null
@@ -1,30 +0,0 @@
-From c20401da0fe90a790f47e70cf79f43551adf76b9 Mon Sep 17 00:00:00 2001
-From: Zoltan HERPAI <wigyori@uid0.hu>
-Date: Sat, 3 Jun 2023 00:52:04 +0200
-Subject: [PATCH 4020/4031] sunxi: add uart0_pins on Port E PE2/PE3 on D1s/T133
-
-Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
----
- arch/riscv/dts/sunxi-d1s-t113.dtsi | 6 ++++++
- 1 file changed, 6 insertions(+)
-
-diff --git a/arch/riscv/dts/sunxi-d1s-t113.dtsi b/arch/riscv/dts/sunxi-d1s-t113.dtsi
-index 6fadcee780..2b7d54aab4 100644
---- a/arch/riscv/dts/sunxi-d1s-t113.dtsi
-+++ b/arch/riscv/dts/sunxi-d1s-t113.dtsi
-@@ -125,6 +125,12 @@
-                               pins = "PB6", "PB7";
-                               function = "uart3";
-                       };
-+
-+                      /omit-if-no-ref/
-+                      uart0_pins: uart0-pins {
-+                              pins = "PE2", "PE3";
-+                              function = "uart0";
-+                      };
-               };
- 
-               ccu: clock-controller@2001000 {
--- 
-2.20.1
-