uboot-sunxi: t113: refresh patches to fix clock issues

[openwrt/staging/wigyori.git] / package / boot / uboot-sunxi / patches / 4024-sunxi-add-support-for-UART3-on-PE-pins.patch

diff --git a/package/boot/uboot-sunxi/patches/4024-sunxi-add-support-for-UART3-on-PE-pins.patch b/package/boot/uboot-sunxi/patches/4024-sunxi-add-support-for-UART3-on-PE-pins.patch
deleted file mode 100644 (file)
index 9b57b68..0000000
--- a/package/boot/uboot-sunxi/patches/4024-sunxi-add-support-for-UART3-on-PE-pins.patch
+++ /dev/null
@@ -1,100 +0,0 @@
-From 9dd404ee6108f09894d5ff60feedb713284ca617 Mon Sep 17 00:00:00 2001
-From: Zoltan HERPAI <wigyori@uid0.hu>
-Date: Sat, 3 Jun 2023 23:57:46 +0200
-Subject: [PATCH 4024/4031] sunxi: add support for UART3 on PE pins
-
-Some boards use Port E pins for muxing the UART3 as console. Add a new
-Kconfig option allowing to select this (mimicking MMC_PINS_PH).
-
-Pinmux taken from https://bbs.aw-ol.com/assets/uploads/files/1648883311844-t113-s3_datasheet_v1.2.pdf
-
-Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
----
- arch/arm/mach-sunxi/Kconfig           |  6 ++++++
- arch/arm/mach-sunxi/board.c           | 10 ++++++++--
- arch/riscv/dts/sunxi-d1s-t113.dtsi    |  6 ++++++
- drivers/pinctrl/sunxi/pinctrl-sunxi.c |  4 ++++
- 4 files changed, 24 insertions(+), 2 deletions(-)
-
-diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
-index 142d86afc6..59fa62c8d5 100644
---- a/arch/arm/mach-sunxi/Kconfig
-+++ b/arch/arm/mach-sunxi/Kconfig
-@@ -665,6 +665,12 @@ config UART0_PORT_F
-       at the same time, the system can be only booted in the FEL mode.
-       Only enable this if you really know what you are doing.
- 
-+config UART3_PINS_PE
-+      bool "Pins for uart3 are on Port E"
-+      ---help---
-+      Select this option for boards where uart3 uses the Port E pinmux.
-+      (Some T113-S3 boards use uart3 as console.)
-+
- config OLD_SUNXI_KERNEL_COMPAT
-       bool "Enable workarounds for booting old kernels"
-       ---help---
-diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
-index 6a37b33767..5de490feda 100644
---- a/arch/arm/mach-sunxi/board.c
-+++ b/arch/arm/mach-sunxi/board.c
-@@ -168,16 +168,22 @@ static int gpio_init(void)
-       sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2);
-       sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
- #elif CONFIG_CONS_INDEX == 4 && defined(CONFIG_MACH_SUN8I_R528)
-+#if defined(CONFIG_UART3_PINS_PE)
-+      sunxi_gpio_set_cfgpin(SUNXI_GPE(8), 5);
-+      sunxi_gpio_set_cfgpin(SUNXI_GPE(9), 5);
-+      sunxi_gpio_set_pull(SUNXI_GPE(9), SUNXI_GPIO_PULL_UP);
-+#else
-       sunxi_gpio_set_cfgpin(SUNXI_GPB(6), 7);
-       sunxi_gpio_set_cfgpin(SUNXI_GPB(7), 7);
-       sunxi_gpio_set_pull(SUNXI_GPB(7), SUNXI_GPIO_PULL_UP);
-+#endif
- #elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
-       sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART);
-       sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART);
-       sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
- #elif CONFIG_CONS_INDEX == 6 && defined(CONFIG_MACH_SUN8I_R528)
--      sunxi_gpio_set_cfgpin(SUNXI_GPE(6), 9);
--      sunxi_gpio_set_cfgpin(SUNXI_GPE(7), 9);
-+      sunxi_gpio_set_cfgpin(SUNXI_GPE(6), 3);
-+      sunxi_gpio_set_cfgpin(SUNXI_GPE(7), 3);
-       sunxi_gpio_set_pull(SUNXI_GPE(7), SUNXI_GPIO_PULL_UP);
- #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN8I) && \
-                               !defined(CONFIG_MACH_SUN8I_R40)
-diff --git a/arch/riscv/dts/sunxi-d1s-t113.dtsi b/arch/riscv/dts/sunxi-d1s-t113.dtsi
-index 2b7d54aab4..d858f21fd2 100644
---- a/arch/riscv/dts/sunxi-d1s-t113.dtsi
-+++ b/arch/riscv/dts/sunxi-d1s-t113.dtsi
-@@ -126,6 +126,12 @@
-                               function = "uart3";
-                       };
- 
-+                      /omit-if-no-ref/
-+                      uart3_pe_pins: uart3-pe-pins {
-+                              pins = "PE8", "PE9";
-+                              function = "uart3";
-+                      };
-+
-                       /omit-if-no-ref/
-                       uart0_pins: uart0-pins {
-                               pins = "PE2", "PE3";
-diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
-index 2717d79bc3..e466808e4e 100644
---- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
-+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
-@@ -747,7 +747,11 @@ static const struct sunxi_pinctrl_function sun20i_d1_pinctrl_functions[] = {
- #else
-       { "uart0",      6 },    /* PB2-PB3 */
- #endif
-+#if IS_ENABLED(CONFIG_UART3_PINS_E)
-+      { "uart3",      5 },    /* PE8-PE9 */
-+else
-       { "uart3",      7 },    /* PB6-PB9 */
-+#endif
-       { "uart5",      3 },    /* PE6-PE7 */
- };
- 
--- 
-2.20.1
-