uboot-sunxi: add T113-S3 support

[openwrt/staging/wigyori.git] / package / boot / uboot-sunxi / patches / 4025-ARM-dts-sunxi-add-Allwinner-T113-s-SoC-.dtsi.patch

diff --git a/package/boot/uboot-sunxi/patches/4025-ARM-dts-sunxi-add-Allwinner-T113-s-SoC-.dtsi.patch b/package/boot/uboot-sunxi/patches/4025-ARM-dts-sunxi-add-Allwinner-T113-s-SoC-.dtsi.patch
new file mode 100644 (file)
index 0000000..944b19f
--- /dev/null
+++ b/package/boot/uboot-sunxi/patches/4025-ARM-dts-sunxi-add-Allwinner-T113-s-SoC-.dtsi.patch
@@ -0,0 +1,113 @@
+From 032126b42512e91b2c8e918fd33a3ed7e96ac8df Mon Sep 17 00:00:00 2001
+From: Andre Przywara <andre.przywara@arm.com>
+Date: Fri, 21 Jul 2023 14:46:05 +0100
+Subject: [PATCH 4025/4052] ARM: dts: sunxi: add Allwinner T113-s SoC .dtsi
+
+The Allwinner T113-s SoC is apparently using the same (or at least a very
+similar) die as the D1/D1s, but replaces the single RISC-V core with
+two Arm Cortex-A7 cores.
+Since the D1 core .dtsi already describes all common peripherals, we
+just need a DT describing the ARM specific peripherals: the CPU cores,
+the Generic Timer, the GIC and the PMU.
+We include the core .dtsi directly from the riscv DT directory.
+
+The ARM core version of the DT specifies the CPUX watchdog as
+"reserved", which means it won't be recognised by U-Boot. Override this
+in our generic sunxi-u-boot.dtsi, to let U-Boot pick up this watchdog,
+so that the generic reset driver will work.
+
+Signed-off-by: Andre Przywara <andre.przywara@arm.com>
+Reviewed-by: Sam Edwards <CFSworks@gmail.com>
+Tested-by: Sam Edwards <CFSworks@gmail.com>
+---
+ arch/arm/dts/sun8i-t113s.dtsi  | 59 ++++++++++++++++++++++++++++++++++
+ arch/arm/dts/sunxi-u-boot.dtsi |  7 ++++
+ 2 files changed, 66 insertions(+)
+ create mode 100644 arch/arm/dts/sun8i-t113s.dtsi
+
+diff --git a/arch/arm/dts/sun8i-t113s.dtsi b/arch/arm/dts/sun8i-t113s.dtsi
+new file mode 100644
+index 0000000000..ce00883130
+--- /dev/null
++++ b/arch/arm/dts/sun8i-t113s.dtsi
+@@ -0,0 +1,59 @@
++// SPDX-License-Identifier: (GPL-2.0+ or MIT)
++// Copyright (C) 2022 Arm Ltd.
++
++#define SOC_PERIPHERAL_IRQ(nr) GIC_SPI nr
++
++#include <dt-bindings/interrupt-controller/arm-gic.h>
++#include <../../riscv/dts/sunxi-d1s-t113.dtsi>
++#include <../../riscv/dts/sunxi-d1-t113.dtsi>
++
++/ {
++      interrupt-parent = <&gic>;
++
++      cpus {
++              #address-cells = <1>;
++              #size-cells = <0>;
++
++              cpu0: cpu@0 {
++                      compatible = "arm,cortex-a7";
++                      device_type = "cpu";
++                      reg = <0>;
++                      clocks = <&ccu CLK_CPUX>;
++                      clock-names = "cpu";
++              };
++
++              cpu1: cpu@1 {
++                      compatible = "arm,cortex-a7";
++                      device_type = "cpu";
++                      reg = <1>;
++                      clocks = <&ccu CLK_CPUX>;
++                      clock-names = "cpu";
++              };
++      };
++
++      gic: interrupt-controller@1c81000 {
++              compatible = "arm,gic-400";
++              reg = <0x03021000 0x1000>,
++                    <0x03022000 0x2000>,
++                    <0x03024000 0x2000>,
++                    <0x03026000 0x2000>;
++              interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
++              interrupt-controller;
++              #interrupt-cells = <3>;
++      };
++
++      timer {
++              compatible = "arm,armv7-timer";
++              interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
++                           <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
++                           <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
++                           <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
++      };
++
++      pmu {
++              compatible = "arm,cortex-a7-pmu";
++              interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
++                           <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
++              interrupt-affinity = <&cpu0>, <&cpu1>;
++      };
++};
+diff --git a/arch/arm/dts/sunxi-u-boot.dtsi b/arch/arm/dts/sunxi-u-boot.dtsi
+index e959eb2a40..27de5b8eac 100644
+--- a/arch/arm/dts/sunxi-u-boot.dtsi
++++ b/arch/arm/dts/sunxi-u-boot.dtsi
+@@ -23,6 +23,13 @@
+       };
+ };
+ 
++/* Let U-Boot be the firmware layer that controls the watchdog. */
++#ifdef CONFIG_MACH_SUN8I_R528
++&wdt {
++      status = "okay";
++};
++#endif
++
+ &binman {
+       u-boot-sunxi-with-spl {
+               filename = "u-boot-sunxi-with-spl.bin";
+-- 
+2.20.1
+