+++ /dev/null
-From ca8c5216cfd3ad3fda9867ed2d157ae5a209834b Mon Sep 17 00:00:00 2001
-From: Xiangfu <xiangfu@openmobilefree.net>
-Date: Wed, 10 Oct 2012 22:05:27 +0800
-Subject: [PATCH 5/6] add nanonote lcd support
-
----
- arch/mips/include/asm/global_data.h | 1 +
- arch/mips/include/asm/jz4740.h | 90 ++++++++
- arch/mips/lib/board.c | 6 +
- common/lcd.c | 9 +-
- drivers/video/Makefile | 1 +
- drivers/video/nanonote_gpm940b0.c | 400 +++++++++++++++++++++++++++++++++++
- drivers/video/nanonote_gpm940b0.h | 135 ++++++++++++
- include/configs/qi_lb60.h | 7 +
- include/lcd.h | 52 ++++-
- 9 files changed, 697 insertions(+), 4 deletions(-)
- create mode 100644 drivers/video/nanonote_gpm940b0.c
- create mode 100644 drivers/video/nanonote_gpm940b0.h
-
-diff --git a/arch/mips/include/asm/global_data.h b/arch/mips/include/asm/global_data.h
-index cd03d7e..7cec2de 100644
---- a/arch/mips/include/asm/global_data.h
-+++ b/arch/mips/include/asm/global_data.h
-@@ -44,6 +44,7 @@ typedef struct global_data {
- unsigned long per_clk; /* Peripheral bus clock */
- unsigned long mem_clk; /* Memory bus clock */
- unsigned long dev_clk; /* Device clock */
-+ unsigned long fb_base; /* base address of framebuffer */
- /* "static data" needed by most of timer.c */
- unsigned long tbl;
- unsigned long lastinc;
-diff --git a/arch/mips/include/asm/jz4740.h b/arch/mips/include/asm/jz4740.h
-index 68287fb..13724a2 100644
---- a/arch/mips/include/asm/jz4740.h
-+++ b/arch/mips/include/asm/jz4740.h
-@@ -1312,5 +1312,95 @@ do { \
- while (REG_MSC_STAT & MSC_STAT_IS_RESETTING); \
- } while (0)
-
-+/*************************************************************************
-+ * LCD (LCD Controller)
-+ *************************************************************************/
-+#define REG32(addr) *((volatile u32 *)(addr))
-+
-+#define CPM_BASE 0xB0000000
-+#define CPM_CPCCR (CPM_BASE+0x00)
-+#define REG_CPM_CPCCR REG32(CPM_CPCCR)
-+
-+#define LCD_BASE 0xB3050000
-+#define LCD_CFG (LCD_BASE + 0x00) /* LCD Configure Register */
-+#define LCD_VSYNC (LCD_BASE + 0x04) /* Vertical Synchronize Register */
-+#define LCD_HSYNC (LCD_BASE + 0x08) /* Horizontal Synchronize Register */
-+#define LCD_VAT (LCD_BASE + 0x0c) /* Virtual Area Setting Register */
-+#define LCD_DAH (LCD_BASE + 0x10) /* Display Area Horizontal Start/End Point */
-+#define LCD_DAV (LCD_BASE + 0x14) /* Display Area Vertical Start/End Point */
-+#define LCD_PS (LCD_BASE + 0x18) /* PS Signal Setting */
-+#define LCD_CLS (LCD_BASE + 0x1c) /* CLS Signal Setting */
-+#define LCD_SPL (LCD_BASE + 0x20) /* SPL Signal Setting */
-+#define LCD_REV (LCD_BASE + 0x24) /* REV Signal Setting */
-+#define LCD_CTRL (LCD_BASE + 0x30) /* LCD Control Register */
-+#define LCD_STATE (LCD_BASE + 0x34) /* LCD Status Register */
-+#define LCD_IID (LCD_BASE + 0x38) /* Interrupt ID Register */
-+#define LCD_DA0 (LCD_BASE + 0x40) /* Descriptor Address Register 0 */
-+#define LCD_SA0 (LCD_BASE + 0x44) /* Source Address Register 0 */
-+#define LCD_FID0 (LCD_BASE + 0x48) /* Frame ID Register 0 */
-+#define LCD_CMD0 (LCD_BASE + 0x4c) /* DMA Command Register 0 */
-+#define LCD_DA1 (LCD_BASE + 0x50) /* Descriptor Address Register 1 */
-+#define LCD_SA1 (LCD_BASE + 0x54) /* Source Address Register 1 */
-+#define LCD_FID1 (LCD_BASE + 0x58) /* Frame ID Register 1 */
-+#define LCD_CMD1 (LCD_BASE + 0x5c) /* DMA Command Register 1 */
-+
-+#define REG_LCD_CFG REG32(LCD_CFG)
-+#define REG_LCD_VSYNC REG32(LCD_VSYNC)
-+#define REG_LCD_HSYNC REG32(LCD_HSYNC)
-+#define REG_LCD_VAT REG32(LCD_VAT)
-+#define REG_LCD_DAH REG32(LCD_DAH)
-+#define REG_LCD_DAV REG32(LCD_DAV)
-+#define REG_LCD_PS REG32(LCD_PS)
-+#define REG_LCD_CLS REG32(LCD_CLS)
-+#define REG_LCD_SPL REG32(LCD_SPL)
-+#define REG_LCD_REV REG32(LCD_REV)
-+#define REG_LCD_CTRL REG32(LCD_CTRL)
-+#define REG_LCD_STATE REG32(LCD_STATE)
-+#define REG_LCD_IID REG32(LCD_IID)
-+#define REG_LCD_DA0 REG32(LCD_DA0)
-+#define REG_LCD_SA0 REG32(LCD_SA0)
-+#define REG_LCD_FID0 REG32(LCD_FID0)
-+#define REG_LCD_CMD0 REG32(LCD_CMD0)
-+#define REG_LCD_DA1 REG32(LCD_DA1)
-+#define REG_LCD_SA1 REG32(LCD_SA1)
-+#define REG_LCD_FID1 REG32(LCD_FID1)
-+#define REG_LCD_CMD1 REG32(LCD_CMD1)
-+
-+#define LCD_CTRL_BPP_BIT 0 /* Bits Per Pixel */
-+#define LCD_CTRL_BPP_MASK (0x07 << LCD_CTRL_BPP_BIT)
-+ #define LCD_CTRL_BPP_1 (0 << LCD_CTRL_BPP_BIT) /* 1 bpp */
-+ #define LCD_CTRL_BPP_2 (1 << LCD_CTRL_BPP_BIT) /* 2 bpp */
-+ #define LCD_CTRL_BPP_4 (2 << LCD_CTRL_BPP_BIT) /* 4 bpp */
-+ #define LCD_CTRL_BPP_8 (3 << LCD_CTRL_BPP_BIT) /* 8 bpp */
-+ #define LCD_CTRL_BPP_16 (4 << LCD_CTRL_BPP_BIT) /* 15/16 bpp */
-+ #define LCD_CTRL_BPP_18_24 (5 << LCD_CTRL_BPP_BIT) /* 18/24/32 bpp */
-+
-+#define LCD_CTRL_BST_BIT 28 /* Burst Length Selection */
-+#define LCD_CTRL_BST_MASK (0x03 << LCD_CTRL_BST_BIT)
-+ #define LCD_CTRL_BST_4 (0 << LCD_CTRL_BST_BIT) /* 4-word */
-+ #define LCD_CTRL_BST_8 (1 << LCD_CTRL_BST_BIT) /* 8-word */
-+ #define LCD_CTRL_BST_16 (2 << LCD_CTRL_BST_BIT) /* 16-word */
-+#define LCD_CTRL_RGB565 (0 << 27) /* RGB565 mode */
-+#define LCD_CTRL_RGB555 (1 << 27) /* RGB555 mode */
-+#define LCD_CTRL_OFUP (1 << 26) /* Output FIFO underrun protection enable */
-+#define LCD_CTRL_FRC_BIT 24 /* STN FRC Algorithm Selection */
-+#define LCD_CTRL_FRC_MASK (0x03 << LCD_CTRL_FRC_BIT)
-+ #define LCD_CTRL_FRC_16 (0 << LCD_CTRL_FRC_BIT) /* 16 grayscale */
-+ #define LCD_CTRL_FRC_4 (1 << LCD_CTRL_FRC_BIT) /* 4 grayscale */
-+ #define LCD_CTRL_FRC_2 (2 << LCD_CTRL_FRC_BIT) /* 2 grayscale */
-+
-+#define CPM_LPCDR (CPM_BASE+0x64)
-+#define CPM_CLKGR (CPM_BASE+0x20)
-+#define REG_CPM_LPCDR REG32(CPM_LPCDR)
-+#define REG_CPM_CLKGR REG32(CPM_CLKGR)
-+
-+#define __cpm_start_tcu() (REG_CPM_CLKGR &= ~CPM_CLKGR_TCU)
-+#define __cpm_stop_lcd() (REG_CPM_CLKGR |= CPM_CLKGR_LCD)
-+#define __cpm_set_pixdiv(v) \
-+ (REG_CPM_LPCDR = (REG_CPM_LPCDR & ~CPM_LPCDR_PIXDIV_MASK) | ((v) << (CPM_LPCDR_PIXDIV_BIT)))
-+#define __cpm_set_ldiv(v) \
-+ (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_LDIV_MASK) | ((v) << (CPM_CPCCR_LDIV_BIT)))
-+#define __cpm_start_lcd() (REG_CPM_CLKGR &= ~CPM_CLKGR_LCD)
-+
- #endif /* !__ASSEMBLY__ */
- #endif /* __JZ4740_H__ */
-diff --git a/arch/mips/lib/board.c b/arch/mips/lib/board.c
-index b14b33e..c2e64d9 100644
---- a/arch/mips/lib/board.c
-+++ b/arch/mips/lib/board.c
-@@ -172,6 +172,12 @@ void board_init_f(ulong bootflag)
- addr &= ~(4096 - 1);
- debug("Top of RAM usable for U-Boot at: %08lx\n", addr);
-
-+#ifdef CONFIG_LCD
-+ /* reserve memory for LCD display (always full pages) */
-+ addr = lcd_setmem (addr);
-+ gd->fb_base = addr;
-+#endif /* CONFIG_LCD */
-+
- /* Reserve memory for U-Boot code, data & bss
- * round down to next 16 kB limit
- */
-diff --git a/common/lcd.c b/common/lcd.c
-index b6be800..af1281a 100644
---- a/common/lcd.c
-+++ b/common/lcd.c
-@@ -263,6 +263,13 @@ static void lcd_drawchars(ushort x, ushort y, uchar *str, int count)
- lcd_color_fg : lcd_color_bg;
- bits <<= 1;
- }
-+#elif LCD_BPP == LCD_COLOR32
-+ uint *m = (uint *)d;
-+ for (c=0; c<32; ++c) {
-+ *m++ = (bits & 0x80) ?
-+ lcd_color_fg : lcd_color_bg;
-+ bits <<= 1;
-+ }
- #endif
- }
- #if LCD_BPP == LCD_MONOCHROME
-@@ -509,7 +516,7 @@ static inline ushort *configuration_get_cmap(void)
- return (ushort *)&(cp->lcd_cmap[255 * sizeof(ushort)]);
- #elif defined(CONFIG_ATMEL_LCD)
- return (ushort *)(panel_info.mmio + ATMEL_LCDC_LUT(0));
--#elif !defined(CONFIG_ATMEL_HLCD) && !defined(CONFIG_EXYNOS_FB)
-+#elif !defined(CONFIG_ATMEL_HLCD) && !defined(CONFIG_EXYNOS_FB) && !defined(CONFIG_VIDEO_GPM940B0)
- return panel_info.cmap;
- #else
- #if defined(CONFIG_LCD_LOGO)
-diff --git a/drivers/video/Makefile b/drivers/video/Makefile
-index ebb6da8..03625bc 100644
---- a/drivers/video/Makefile
-+++ b/drivers/video/Makefile
-@@ -50,6 +50,7 @@ COBJS-$(CONFIG_VIDEO_SED13806) += sed13806.o
- COBJS-$(CONFIG_VIDEO_SM501) += sm501.o
- COBJS-$(CONFIG_VIDEO_SMI_LYNXEM) += smiLynxEM.o videomodes.o
- COBJS-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o
-+COBJS-$(CONFIG_VIDEO_GPM940B0) += nanonote_gpm940b0.o
-
- COBJS := $(sort $(COBJS-y))
- SRCS := $(COBJS:.o=.c)
-diff --git a/drivers/video/nanonote_gpm940b0.c b/drivers/video/nanonote_gpm940b0.c
-new file mode 100644
-index 0000000..11efb72
---- /dev/null
-+++ b/drivers/video/nanonote_gpm940b0.c
-@@ -0,0 +1,400 @@
-+/*
-+ * JzRISC lcd controller
-+ *
-+ * Xiangfu Liu <xiangfu@sharism.cc>
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
-+ */
-+
-+#include <config.h>
-+#include <common.h>
-+#include <lcd.h>
-+
-+#include <asm/io.h> /* virt_to_phys() */
-+#include <asm/jz4740.h>
-+
-+#include "nanonote_gpm940b0.h"
-+
-+#define align2(n) (n)=((((n)+1)>>1)<<1)
-+#define align4(n) (n)=((((n)+3)>>2)<<2)
-+#define align8(n) (n)=((((n)+7)>>3)<<3)
-+
-+struct jzfb_info {
-+ unsigned int cfg; /* panel mode and pin usage etc. */
-+ unsigned int w;
-+ unsigned int h;
-+ unsigned int bpp; /* bit per pixel */
-+ unsigned int fclk; /* frame clk */
-+ unsigned int hsw; /* hsync width, in pclk */
-+ unsigned int vsw; /* vsync width, in line count */
-+ unsigned int elw; /* end of line, in pclk */
-+ unsigned int blw; /* begin of line, in pclk */
-+ unsigned int efw; /* end of frame, in line count */
-+ unsigned int bfw; /* begin of frame, in line count */
-+};
-+
-+static struct jzfb_info jzfb = {
-+ MODE_8BIT_SERIAL_TFT | PCLK_N | HSYNC_N | VSYNC_N,
-+ 320, 240, 32, 70, 1, 1, 273, 140, 1, 20
-+};
-+
-+vidinfo_t panel_info = {
-+ 320, 240, LCD_BPP,
-+};
-+
-+void *lcd_base;
-+void *lcd_console_address;
-+int lcd_line_length;
-+int lcd_color_fg;
-+int lcd_color_bg;
-+short console_col;
-+short console_row;
-+
-+static int jz_lcd_init_mem(void *lcdbase, vidinfo_t *vid)
-+{
-+ u_long palette_mem_size;
-+ struct jz_fb_info *fbi = &vid->jz_fb;
-+ int fb_size = vid->vl_row * (vid->vl_col * NBITS (vid->vl_bpix)) / 8;
-+
-+ fbi->screen = (u_long)lcdbase;
-+ fbi->palette_size = 256;
-+ palette_mem_size = fbi->palette_size * sizeof(u16);
-+
-+ debug("jz_lcd.c palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size);
-+ /* locate palette and descs at end of page following fb */
-+ fbi->palette = (u_long)lcdbase + fb_size + PAGE_SIZE - palette_mem_size;
-+
-+ return 0;
-+}
-+
-+static void jz_lcd_desc_init(vidinfo_t *vid)
-+{
-+ struct jz_fb_info * fbi;
-+ fbi = &vid->jz_fb;
-+ fbi->dmadesc_fblow = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 3*16);
-+ fbi->dmadesc_fbhigh = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 2*16);
-+ fbi->dmadesc_palette = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 1*16);
-+
-+ #define BYTES_PER_PANEL (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8)
-+
-+ /* populate descriptors */
-+ fbi->dmadesc_fblow->fdadr = virt_to_phys(fbi->dmadesc_fblow);
-+ fbi->dmadesc_fblow->fsadr = virt_to_phys((void *)(fbi->screen + BYTES_PER_PANEL));
-+ fbi->dmadesc_fblow->fidr = 0;
-+ fbi->dmadesc_fblow->ldcmd = BYTES_PER_PANEL / 4 ;
-+
-+ fbi->fdadr1 = virt_to_phys(fbi->dmadesc_fblow); /* only used in dual-panel mode */
-+
-+ fbi->dmadesc_fbhigh->fsadr = virt_to_phys((void *)fbi->screen);
-+ fbi->dmadesc_fbhigh->fidr = 0;
-+ fbi->dmadesc_fbhigh->ldcmd = BYTES_PER_PANEL / 4; /* length in word */
-+
-+ fbi->dmadesc_palette->fsadr = virt_to_phys((void *)fbi->palette);
-+ fbi->dmadesc_palette->fidr = 0;
-+ fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2)/4 | (1<<28);
-+
-+ if(NBITS(vid->vl_bpix) < 12) {
-+ /* assume any mode with <12 bpp is palette driven */
-+ fbi->dmadesc_palette->fdadr = virt_to_phys(fbi->dmadesc_fbhigh);
-+ fbi->dmadesc_fbhigh->fdadr = virt_to_phys(fbi->dmadesc_palette);
-+ /* flips back and forth between pal and fbhigh */
-+ fbi->fdadr0 = virt_to_phys(fbi->dmadesc_palette);
-+ } else {
-+ /* palette shouldn't be loaded in true-color mode */
-+ fbi->dmadesc_fbhigh->fdadr = virt_to_phys((void *)fbi->dmadesc_fbhigh);
-+ fbi->fdadr0 = virt_to_phys(fbi->dmadesc_fbhigh); /* no pal just fbhigh */
-+ }
-+}
-+
-+static int jz_lcd_hw_init(vidinfo_t *vid)
-+{
-+ struct jz_fb_info *fbi = &vid->jz_fb;
-+ unsigned int val = 0;
-+ unsigned int pclk;
-+ unsigned int stnH;
-+ int pll_div;
-+
-+ /* Setting Control register */
-+ switch (jzfb.bpp) {
-+ case 1:
-+ val |= LCD_CTRL_BPP_1;
-+ break;
-+ case 2:
-+ val |= LCD_CTRL_BPP_2;
-+ break;
-+ case 4:
-+ val |= LCD_CTRL_BPP_4;
-+ break;
-+ case 8:
-+ val |= LCD_CTRL_BPP_8;
-+ break;
-+ case 15:
-+ val |= LCD_CTRL_RGB555;
-+ case 16:
-+ val |= LCD_CTRL_BPP_16;
-+ break;
-+ case 17 ... 32:
-+ val |= LCD_CTRL_BPP_18_24; /* target is 4bytes/pixel */
-+ break;
-+
-+ default:
-+ printf("jz_lcd.c The BPP %d is not supported\n", jzfb.bpp);
-+ val |= LCD_CTRL_BPP_16;
-+ break;
-+ }
-+
-+ switch (jzfb.cfg & MODE_MASK) {
-+ case MODE_STN_MONO_DUAL:
-+ case MODE_STN_COLOR_DUAL:
-+ case MODE_STN_MONO_SINGLE:
-+ case MODE_STN_COLOR_SINGLE:
-+ switch (jzfb.bpp) {
-+ case 1:
-+ /* val |= LCD_CTRL_PEDN; */
-+ case 2:
-+ val |= LCD_CTRL_FRC_2;
-+ break;
-+ case 4:
-+ val |= LCD_CTRL_FRC_4;
-+ break;
-+ case 8:
-+ default:
-+ val |= LCD_CTRL_FRC_16;
-+ break;
-+ }
-+ break;
-+ }
-+
-+ val |= LCD_CTRL_BST_16; /* Burst Length is 16WORD=64Byte */
-+ val |= LCD_CTRL_OFUP; /* OutFIFO underrun protect */
-+
-+ switch (jzfb.cfg & MODE_MASK) {
-+ case MODE_STN_MONO_DUAL:
-+ case MODE_STN_COLOR_DUAL:
-+ case MODE_STN_MONO_SINGLE:
-+ case MODE_STN_COLOR_SINGLE:
-+ switch (jzfb.cfg & STN_DAT_PINMASK) {
-+ case STN_DAT_PIN1:
-+ /* Do not adjust the hori-param value. */
-+ break;
-+ case STN_DAT_PIN2:
-+ align2(jzfb.hsw);
-+ align2(jzfb.elw);
-+ align2(jzfb.blw);
-+ break;
-+ case STN_DAT_PIN4:
-+ align4(jzfb.hsw);
-+ align4(jzfb.elw);
-+ align4(jzfb.blw);
-+ break;
-+ case STN_DAT_PIN8:
-+ align8(jzfb.hsw);
-+ align8(jzfb.elw);
-+ align8(jzfb.blw);
-+ break;
-+ }
-+ break;
-+ }
-+
-+ REG_LCD_CTRL = val;
-+
-+ switch (jzfb.cfg & MODE_MASK) {
-+ case MODE_STN_MONO_DUAL:
-+ case MODE_STN_COLOR_DUAL:
-+ case MODE_STN_MONO_SINGLE:
-+ case MODE_STN_COLOR_SINGLE:
-+ if (((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL) ||
-+ ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL))
-+ stnH = jzfb.h >> 1;
-+ else
-+ stnH = jzfb.h;
-+
-+ REG_LCD_VSYNC = (0 << 16) | jzfb.vsw;
-+ REG_LCD_HSYNC = ((jzfb.blw+jzfb.w) << 16) | (jzfb.blw+jzfb.w+jzfb.hsw);
-+
-+ /* Screen setting */
-+ REG_LCD_VAT = ((jzfb.blw + jzfb.w + jzfb.hsw + jzfb.elw) << 16) | (stnH + jzfb.vsw + jzfb.bfw + jzfb.efw);
-+ REG_LCD_DAH = (jzfb.blw << 16) | (jzfb.blw + jzfb.w);
-+ REG_LCD_DAV = (0 << 16) | (stnH);
-+
-+ /* AC BIAs signal */
-+ REG_LCD_PS = (0 << 16) | (stnH+jzfb.vsw+jzfb.efw+jzfb.bfw);
-+
-+ break;
-+
-+ case MODE_TFT_GEN:
-+ case MODE_TFT_SHARP:
-+ case MODE_TFT_CASIO:
-+ case MODE_TFT_SAMSUNG:
-+ case MODE_8BIT_SERIAL_TFT:
-+ case MODE_TFT_18BIT:
-+ REG_LCD_VSYNC = (0 << 16) | jzfb.vsw;
-+ REG_LCD_HSYNC = (0 << 16) | jzfb.hsw;
-+ REG_LCD_DAV =((jzfb.vsw+jzfb.bfw) << 16) | (jzfb.vsw +jzfb.bfw+jzfb.h);
-+ REG_LCD_DAH = ((jzfb.hsw + jzfb.blw) << 16) | (jzfb.hsw + jzfb.blw + jzfb.w );
-+ REG_LCD_VAT = (((jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw)) << 16) \
-+ | (jzfb.vsw + jzfb.bfw + jzfb.h + jzfb.efw);
-+ break;
-+ }
-+
-+ switch (jzfb.cfg & MODE_MASK) {
-+ case MODE_TFT_SAMSUNG:
-+ {
-+ unsigned int total, tp_s, tp_e, ckv_s, ckv_e;
-+ unsigned int rev_s, rev_e, inv_s, inv_e;
-+
-+ pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) *
-+ (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */
-+
-+ total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw;
-+ tp_s = jzfb.blw + jzfb.w + 1;
-+ tp_e = tp_s + 1;
-+ ckv_s = tp_s - pclk/(1000000000/4100);
-+ ckv_e = tp_s + total;
-+ rev_s = tp_s - 11; /* -11.5 clk */
-+ rev_e = rev_s + total;
-+ inv_s = tp_s;
-+ inv_e = inv_s + total;
-+ REG_LCD_CLS = (tp_s << 16) | tp_e;
-+ REG_LCD_PS = (ckv_s << 16) | ckv_e;
-+ REG_LCD_SPL = (rev_s << 16) | rev_e;
-+ REG_LCD_REV = (inv_s << 16) | inv_e;
-+ jzfb.cfg |= STFT_REVHI | STFT_SPLHI;
-+ break;
-+ }
-+ case MODE_TFT_SHARP:
-+ {
-+ unsigned int total, cls_s, cls_e, ps_s, ps_e;
-+ unsigned int spl_s, spl_e, rev_s, rev_e;
-+ total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw;
-+ spl_s = 1;
-+ spl_e = spl_s + 1;
-+ cls_s = 0;
-+ cls_e = total - 60; /* > 4us (pclk = 80ns) */
-+ ps_s = cls_s;
-+ ps_e = cls_e;
-+ rev_s = total - 40; /* > 3us (pclk = 80ns) */
-+ rev_e = rev_s + total;
-+ jzfb.cfg |= STFT_PSHI;
-+ REG_LCD_SPL = (spl_s << 16) | spl_e;
-+ REG_LCD_CLS = (cls_s << 16) | cls_e;
-+ REG_LCD_PS = (ps_s << 16) | ps_e;
-+ REG_LCD_REV = (rev_s << 16) | rev_e;
-+ break;
-+ }
-+ case MODE_TFT_CASIO:
-+ break;
-+ }
-+
-+ /* Configure the LCD panel */
-+ REG_LCD_CFG = jzfb.cfg;
-+
-+ /* Timing setting */
-+ __cpm_stop_lcd();
-+
-+ val = jzfb.fclk; /* frame clk */
-+ if ( (jzfb.cfg & MODE_MASK) != MODE_8BIT_SERIAL_TFT) {
-+ pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) *
-+ (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */
-+ } else {
-+ /* serial mode: Hsync period = 3*Width_Pixel */
-+ pclk = val * (jzfb.w*3 + jzfb.hsw + jzfb.elw + jzfb.blw) *
-+ (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */
-+ }
-+
-+ if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) ||
-+ ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL))
-+ pclk = (pclk * 3);
-+
-+ if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) ||
-+ ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) ||
-+ ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_SINGLE) ||
-+ ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL))
-+ pclk = pclk >> ((jzfb.cfg & STN_DAT_PINMASK) >> 4);
-+
-+ if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) ||
-+ ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL))
-+ pclk >>= 1;
-+
-+ pll_div = (REG_CPM_CPCCR & CPM_CPCCR_PCS); /* clock source,0:pllout/2 1: pllout */
-+ pll_div = pll_div ? 1 : 2;
-+ val = (__cpm_get_pllout() / pll_div) / pclk;
-+ val--;
-+ if (val > 0x1ff) {
-+ printf("CPM_LPCDR too large, set it to 0x1ff\n");
-+ val = 0x1ff;
-+ }
-+ __cpm_set_pixdiv(val);
-+
-+ val = pclk * 3 ; /* LCDClock > 2.5*Pixclock */
-+ if (val > 150000000) {
-+ printf("Warning: LCDClock=%d\n, LCDClock must less or equal to 150MHz.\n", val);
-+ printf("Change LCDClock to 150MHz\n");
-+ val = 150000000;
-+ }
-+ val = (__cpm_get_pllout() / pll_div) / val;
-+ val--;
-+ if (val > 0x1f) {
-+ printf("CPM_CPCCR.LDIV too large, set it to 0x1f\n");
-+ val = 0x1f;
-+ }
-+ __cpm_set_ldiv( val );
-+ REG_CPM_CPCCR |= CPM_CPCCR_CE ; /* update divide */
-+
-+ __cpm_start_lcd();
-+ udelay(1000);
-+
-+ REG_LCD_DA0 = fbi->fdadr0; /* frame descripter*/
-+
-+ if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) ||
-+ ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL))
-+ REG_LCD_DA1 = fbi->fdadr1; /* frame descripter*/
-+
-+ return 0;
-+}
-+
-+void lcd_ctrl_init (void *lcdbase)
-+{
-+ __lcd_display_pin_init();
-+ __lcd_display_on() ;
-+
-+ jz_lcd_init_mem(lcdbase, &panel_info);
-+ jz_lcd_desc_init(&panel_info);
-+ jz_lcd_hw_init(&panel_info);
-+
-+}
-+
-+/*
-+ * Before enabled lcd controller, lcd registers should be configured correctly.
-+ */
-+void lcd_enable (void)
-+{
-+ REG_LCD_CTRL &= ~(1<<4); /* LCDCTRL.DIS */
-+ REG_LCD_CTRL |= 1<<3; /* LCDCTRL.ENA*/
-+}
-+
-+void lcd_disable (void)
-+{
-+ REG_LCD_CTRL |= (1<<4);
-+}
-+
-+void lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue)
-+{
-+}
-+
-+void lcd_initcolregs (void)
-+{
-+}
-diff --git a/drivers/video/nanonote_gpm940b0.h b/drivers/video/nanonote_gpm940b0.h
-new file mode 100644
-index 0000000..efe491e
---- /dev/null
-+++ b/drivers/video/nanonote_gpm940b0.h
-@@ -0,0 +1,135 @@
-+/*
-+ * JzRISC lcd controller
-+ *
-+ * Xiangfu Liu <xiangfu@sharism.cc>
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
-+ */
-+
-+#ifndef __QI_LB60_GPM940B0_H__
-+#define __QI_LB60_GPM940B0_H__
-+
-+struct lcd_desc{
-+ unsigned int next_desc; /* LCDDAx */
-+ unsigned int databuf; /* LCDSAx */
-+ unsigned int frame_id; /* LCDFIDx */
-+ unsigned int cmd; /* LCDCMDx */
-+};
-+
-+#define MODE_MASK 0x0f
-+#define MODE_TFT_GEN 0x00
-+#define MODE_TFT_SHARP 0x01
-+#define MODE_TFT_CASIO 0x02
-+#define MODE_TFT_SAMSUNG 0x03
-+#define MODE_CCIR656_NONINT 0x04
-+#define MODE_CCIR656_INT 0x05
-+#define MODE_STN_COLOR_SINGLE 0x08
-+#define MODE_STN_MONO_SINGLE 0x09
-+#define MODE_STN_COLOR_DUAL 0x0a
-+#define MODE_STN_MONO_DUAL 0x0b
-+#define MODE_8BIT_SERIAL_TFT 0x0c
-+
-+#define MODE_TFT_18BIT (1<<7)
-+
-+#define STN_DAT_PIN1 (0x00 << 4)
-+#define STN_DAT_PIN2 (0x01 << 4)
-+#define STN_DAT_PIN4 (0x02 << 4)
-+#define STN_DAT_PIN8 (0x03 << 4)
-+#define STN_DAT_PINMASK STN_DAT_PIN8
-+
-+#define STFT_PSHI (1 << 15)
-+#define STFT_CLSHI (1 << 14)
-+#define STFT_SPLHI (1 << 13)
-+#define STFT_REVHI (1 << 12)
-+
-+#define SYNC_MASTER (0 << 16)
-+#define SYNC_SLAVE (1 << 16)
-+
-+#define DE_P (0 << 9)
-+#define DE_N (1 << 9)
-+
-+#define PCLK_P (0 << 10)
-+#define PCLK_N (1 << 10)
-+
-+#define HSYNC_P (0 << 11)
-+#define HSYNC_N (1 << 11)
-+
-+#define VSYNC_P (0 << 8)
-+#define VSYNC_N (1 << 8)
-+
-+#define DATA_NORMAL (0 << 17)
-+#define DATA_INVERSE (1 << 17)
-+
-+
-+/* Jz LCDFB supported I/O controls. */
-+#define FBIOSETBACKLIGHT 0x4688
-+#define FBIODISPON 0x4689
-+#define FBIODISPOFF 0x468a
-+#define FBIORESET 0x468b
-+#define FBIOPRINT_REG 0x468c
-+
-+/*
-+ * LCD panel specific definition
-+ */
-+#define MODE (0xc9) /* 8bit serial RGB */
-+
-+#define __spi_write_reg1(reg, val) \
-+do { \
-+ unsigned char no; \
-+ unsigned short value; \
-+ unsigned char a=reg; \
-+ unsigned char b=val; \
-+ __gpio_set_pin(SPEN); \
-+ __gpio_set_pin(SPCK); \
-+ __gpio_clear_pin(SPDA); \
-+ __gpio_clear_pin(SPEN); \
-+ value=((a<<8)|(b&0xFF)); \
-+ for(no=0;no<16;no++) \
-+ { \
-+ __gpio_clear_pin(SPCK); \
-+ if((value&0x8000)==0x8000) \
-+ __gpio_set_pin(SPDA); \
-+ else \
-+ __gpio_clear_pin(SPDA); \
-+ __gpio_set_pin(SPCK); \
-+ value=(value<<1); \
-+ } \
-+ __gpio_set_pin(SPEN); \
-+} while (0)
-+
-+#define __lcd_display_pin_init() \
-+do { \
-+ __cpm_start_tcu(); \
-+ __gpio_as_output(SPEN); /* use SPDA */ \
-+ __gpio_as_output(SPCK); /* use SPCK */ \
-+ __gpio_as_output(SPDA); /* use SPDA */ \
-+} while (0)
-+
-+#define __lcd_display_on() \
-+do { \
-+ __spi_write_reg1(0x05, 0x1e); \
-+ __spi_write_reg1(0x05, 0x5e); \
-+ __spi_write_reg1(0x07, 0x8d); \
-+ __spi_write_reg1(0x13, 0x01); \
-+ __spi_write_reg1(0x05, 0x5f); \
-+} while (0)
-+
-+#define __lcd_display_off() \
-+do { \
-+ __spi_write_reg1(0x05, 0x5e); \
-+} while (0)
-+
-+#endif /* __QI_LB60_GPM940B0_H__ */
-diff --git a/include/configs/qi_lb60.h b/include/configs/qi_lb60.h
-index 52b370c..d3e78ad 100644
---- a/include/configs/qi_lb60.h
-+++ b/include/configs/qi_lb60.h
-@@ -32,6 +32,13 @@
- * Miscellaneous configurable options
- */
- #define CONFIG_NANONOTE
-+
-+#define CONFIG_LCD
-+#define CONFIG_SYS_WHITE_ON_BLACK
-+#define LCD_BPP LCD_COLOR32
-+#define CONFIG_VIDEO_GPM940B0
-+
-+
- #define CONFIG_JZ4740_MMC
- #define CONFIG_MMC 1
- #define CONFIG_FAT 1
-diff --git a/include/lcd.h b/include/lcd.h
-index 42070d7..6de5482 100644
---- a/include/lcd.h
-+++ b/include/lcd.h
-@@ -263,8 +263,44 @@ typedef struct vidinfo {
-
- void init_panel_info(vidinfo_t *vid);
-
--#else
-+#elif defined(CONFIG_JZSOC)
-+/*
-+ * LCD controller stucture for JZSOC: JZ4740
-+ */
-+struct jz_fb_dma_descriptor {
-+ u_long fdadr; /* Frame descriptor address register */
-+ u_long fsadr; /* Frame source address register */
-+ u_long fidr; /* Frame ID register */
-+ u_long ldcmd; /* Command register */
-+};
-+
-+/*
-+ * Jz LCD info
-+ */
-+struct jz_fb_info {
-+
-+ u_long fdadr0; /* physical address of frame/palette descriptor */
-+ u_long fdadr1; /* physical address of frame descriptor */
-+
-+ /* DMA descriptors */
-+ struct jz_fb_dma_descriptor * dmadesc_fblow;
-+ struct jz_fb_dma_descriptor * dmadesc_fbhigh;
-+ struct jz_fb_dma_descriptor * dmadesc_palette;
-+ u_long screen; /* address of frame buffer */
-+ u_long palette; /* address of palette memory */
-+ u_int palette_size;
-+};
-+typedef struct vidinfo {
-+ ushort vl_col; /* Number of columns (i.e. 640) */
-+ ushort vl_row; /* Number of rows (i.e. 480) */
-+ u_char vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8 */
-+
-+ struct jz_fb_info jz_fb;
-+} vidinfo_t;
-+
-+extern vidinfo_t panel_info;
-
-+#else
- typedef struct vidinfo {
- ushort vl_col; /* Number of columns (i.e. 160) */
- ushort vl_row; /* Number of rows (i.e. 100) */
-@@ -318,6 +354,7 @@ void lcd_show_board_info(void);
- #define LCD_COLOR4 2
- #define LCD_COLOR8 3
- #define LCD_COLOR16 4
-+#define LCD_COLOR32 5
-
- /*----------------------------------------------------------------------*/
- #if defined(CONFIG_LCD_INFO_BELOW_LOGO)
-@@ -369,7 +406,7 @@ void lcd_show_board_info(void);
- # define CONSOLE_COLOR_GREY 14
- # define CONSOLE_COLOR_WHITE 15 /* Must remain last / highest */
-
--#else
-+#elif LCD_BPP == LCD_COLOR16
-
- /*
- * 16bpp color definitions
-@@ -377,6 +414,15 @@ void lcd_show_board_info(void);
- # define CONSOLE_COLOR_BLACK 0x0000
- # define CONSOLE_COLOR_WHITE 0xffff /* Must remain last / highest */
-
-+#elif LCD_BPP == LCD_COLOR32
-+/*
-+ * 18,24,32 bpp color definitions
-+ */
-+# define CONSOLE_COLOR_BLACK 0x00000000
-+# define CONSOLE_COLOR_WHITE 0xffffffff /* Must remain last / highest */
-+
-+#else
-+
- #endif /* color definitions */
-
- /************************************************************************/
-@@ -406,7 +452,7 @@ void lcd_show_board_info(void);
- #if LCD_BPP == LCD_MONOCHROME
- # define COLOR_MASK(c) ((c) | (c) << 1 | (c) << 2 | (c) << 3 | \
- (c) << 4 | (c) << 5 | (c) << 6 | (c) << 7)
--#elif (LCD_BPP == LCD_COLOR8) || (LCD_BPP == LCD_COLOR16)
-+#elif (LCD_BPP == LCD_COLOR8) || (LCD_BPP == LCD_COLOR16) || (LCD_BPP == LCD_COLOR32)
- # define COLOR_MASK(c) (c)
- #else
- # error Unsupported LCD BPP.
---
-1.7.9.5
-
projects / openwrt / openwrt.git / blobdiff