--- a/drivers/net/wireless/ralink/rt2x00/rt2800.h
+++ b/drivers/net/wireless/ralink/rt2x00/rt2800.h
-@@ -1044,6 +1044,11 @@
+@@ -1056,6 +1056,11 @@
#define MIMO_PS_CFG_RX_STBY_POL FIELD32(0x00000010)
#define MIMO_PS_CFG_RX_RX_STBY0 FIELD32(0x00000020)
*/
--- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
+++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
-@@ -3778,14 +3778,16 @@ static void rt2800_config_channel_rf7620
+@@ -3836,14 +3836,16 @@ static void rt2800_config_channel_rf7620
rt2x00_set_field8(&rfcsr, RFCSR19_K, rf->rf4);
rt2800_rfcsr_write(rt2x00dev, 19, rfcsr);
rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
rt2x00_set_field8(&rfcsr, RFCSR1_TX2_EN_MT7620,
-@@ -3819,18 +3821,23 @@ static void rt2800_config_channel_rf7620
+@@ -3877,18 +3879,23 @@ static void rt2800_config_channel_rf7620
rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x20);
}
if (!test_bit(DEVICE_STATE_SCANNING, &rt2x00dev->flags)) {
if (conf_is_ht40(conf)) {
-@@ -3929,25 +3936,29 @@ static void rt2800_config_alc(struct rt2
+@@ -4002,25 +4009,29 @@ static void rt2800_config_alc_rt6352(str
if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY)))
rt2x00_warn(rt2x00dev, "RF busy while configuring ALC\n");
rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, mac_sys_ctrl);
rt2800_vco_calibration(rt2x00dev);
-@@ -6011,18 +6022,33 @@ static int rt2800_init_registers(struct
+@@ -4513,7 +4524,8 @@ static void rt2800_config_channel(struct
+ if (rt2x00_rt(rt2x00dev, RT6352)) {
+ /* BBP for GLRT BW */
+ bbp = conf_is_ht40(conf) ?
+- 0x10 : rt2x00_has_cap_external_lna_bg(rt2x00dev) ?
++ 0x10 : !rt2x00_has_cap_external_lna_bg(rt2x00dev) ?
++ 0x1a : rt2800_hw_get_chippkg(rt2x00dev) == 1 ?
+ 0x15 : 0x1a;
+ rt2800_bbp_glrt_write(rt2x00dev, 141, bbp);
+
+@@ -6017,18 +6029,33 @@ static int rt2800_init_registers(struct
} else if (rt2x00_rt(rt2x00dev, RT5350)) {
rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
} else if (rt2x00_rt(rt2x00dev, RT6352)) {
reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_1);
rt2x00_set_field32(®, TX_ALC_CFG_1_ROS_BUSY_EN, 0);
rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg);
-@@ -7127,14 +7153,16 @@ static void rt2800_init_bbp_6352(struct
+@@ -7141,14 +7168,16 @@ static void rt2800_init_bbp_6352(struct
rt2800_bbp_write(rt2x00dev, 188, 0x00);
rt2800_bbp_write(rt2x00dev, 189, 0x00);
/* BBP for G band GLRT function (BBP_128 ~ BBP_221) */
rt2800_bbp_glrt_write(rt2x00dev, 0, 0x00);
-@@ -10406,31 +10434,36 @@ static void rt2800_init_rfcsr_6352(struc
+@@ -10381,6 +10410,9 @@ static void rt2800_restore_rf_bbp_rt6352
+ rt2800_register_write(rt2x00dev, RF_BYPASS3, 0x0);
+ }
+
++ if (rt2800_hw_get_chippkg(rt2x00dev) != 1)
++ return;
++
+ if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16);
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x23);
+@@ -10458,6 +10490,9 @@ static void rt2800_calibration_rt6352(st
+ rt2800_register_write(rt2x00dev, RF_BYPASS3, reg);
+ }
+
++ if (rt2800_hw_get_chippkg(rt2x00dev) != 1)
++ return;
++
+ if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x66);
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x20);
+@@ -10548,31 +10583,36 @@ static void rt2800_init_rfcsr_6352(struc
rt2800_rfcsr_write(rt2x00dev, 42, 0x5B);
rt2800_rfcsr_write(rt2x00dev, 43, 0x00);
/* Initialize RF channel register to default value */
rt2800_rfcsr_write_chanreg(rt2x00dev, 0, 0x03);
-@@ -10496,63 +10529,71 @@ static void rt2800_init_rfcsr_6352(struc
+@@ -10638,63 +10678,71 @@ static void rt2800_init_rfcsr_6352(struc
rt2800_rfcsr_write_bank(rt2x00dev, 6, 45, 0xC5);
- rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
- rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xF7);
- rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x09);
--
-- rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x51);
-- rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06);
-- rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7);
-- rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x2C);
-- rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x64);
-- rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x51);
-- rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x36);
-- rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53);
-- rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16);
--
-- rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x6C);
-- rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFC);
-- rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1F);
-- rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27);
-- rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
-- rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
--
-- /* Initialize RF channel register for DRQFN */
-- rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
-- rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xE3);
-- rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xE5);
-- rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x28);
-- rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x68);
-- rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xF7);
-- rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x02);
-- rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xC7);
+ if (rt2800_hw_get_chipver(rt2x00dev) > 1) {
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x47);
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x71);
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xF7);
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x09);
+ }
-+
+
+- rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x51);
+- rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06);
+- rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7);
+- rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x2C);
+- rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x64);
+- rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x51);
+- rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x36);
+- rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53);
+- rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16);
+ if (rt2800_hw_get_chipver(rt2x00dev) > 1 &&
+ rt2800_hw_get_chipeco(rt2x00dev) >= 2) {
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x51);
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
+ }
-+
+
+- rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x6C);
+- rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFC);
+- rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1F);
+- rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27);
+- rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
+- rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
+-
+- /* Initialize RF channel register for DRQFN */
+- rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
+- rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xE3);
+- rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xE5);
+- rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x28);
+- rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x68);
+- rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xF7);
+- rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x02);
+- rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xC7);
+ if (rt2800_hw_get_chippkg(rt2x00dev) == 0 &&
+ rt2800_hw_get_chipver(rt2x00dev) == 1) {
+ /* Initialize RF channel register for DRQFN */
/* Initialize RF DC calibration register to default value */
rt2800_rfcsr_write_dccal(rt2x00dev, 0, 0x47);
-@@ -10615,12 +10656,17 @@ static void rt2800_init_rfcsr_6352(struc
+@@ -10757,12 +10805,17 @@ static void rt2800_init_rfcsr_6352(struc
rt2800_rfcsr_write_dccal(rt2x00dev, 62, 0x00);
rt2800_rfcsr_write_dccal(rt2x00dev, 63, 0x00);
+ rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x7C);
+ }
- rt6352_enable_pa_pin(rt2x00dev, 0);
- rt2800_r_calibration(rt2x00dev);
+ /* Do calibration and init PA/LNA */
+ rt2800_calibration_rt6352(rt2x00dev);