Add Broadcom's code for bcm63xx support

[project/bcm63xx/atf.git] / plat / bcm / include / pmc_addr_47622.h

diff --git a/plat/bcm/include/pmc_addr_47622.h b/plat/bcm/include/pmc_addr_47622.h
new file mode 100644 (file)
index 0000000..415eb8c
--- /dev/null
+++ b/plat/bcm/include/pmc_addr_47622.h
@@ -0,0 +1,134 @@
+/*
+<:copyright-BRCM:2019:DUAL/GPL:standard 
+
+   Copyright (c) 2019 Broadcom 
+   All Rights Reserved
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License, version 2, as published by
+the Free Software Foundation (the "GPL").
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+
+A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by
+writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.
+
+:> 
+*/
+
+#ifndef PMC_ADDR_47622_H__
+#define PMC_ADDR_47622_H__
+
+#define PMB_BUS_ID_SHIFT         12
+
+#define PMB_BUS_PERIPH           1
+#define PMB_ADDR_PERIPH          (16 | PMB_BUS_PERIPH << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PERIPH         4
+
+#define PMB_BUS_CRYPTO           0
+#define PMB_ADDR_CRYPTO          (1 | PMB_BUS_CRYPTO << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_CRYPTO         1
+
+#define PMB_BUS_PVTMON           0
+#define PMB_ADDR_PVTMON          (2 | PMB_BUS_PVTMON << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PVTMON         0
+
+#define PMB_BUS_CHIP_CLKRST      0
+#define PMB_ADDR_CHIP_CLKRST     (3 | PMB_BUS_CHIP_CLKRST << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_CHIP_CLKRST    0
+
+#define PMB_BUS_USB31_20         0
+#define PMB_ADDR_USB31_20        (4 | PMB_BUS_USB31_20 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_USB31_20       3
+
+#define PMB_BUS_WLAN0            0
+#define PMB_ADDR_WLAN0           (5 | PMB_BUS_WLAN0 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_WLAN0          1
+
+#define PMB_BUS_WLAN0_PHY1       0
+#define PMB_ADDR_WLAN0_PHY1      (6 | PMB_BUS_WLAN0_PHY1 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_WLAN0_PHY1     1
+
+#define PMB_BUS_WLAN0_PHY2       0
+#define PMB_ADDR_WLAN0_PHY2      (7 | PMB_BUS_WLAN0_PHY2 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_WLAN0_PHY2     1
+
+#define PMB_BUS_WLAN1            0
+#define PMB_ADDR_WLAN1           (8 | PMB_BUS_WLAN1 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_WLAN1          1
+
+#define PMB_BUS_WLAN1_PHY1       0
+#define PMB_ADDR_WLAN1_PHY1      (9 | PMB_BUS_WLAN1_PHY1 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_WLAN1_PHY1     1
+
+#define PMB_BUS_WLAN1_PHY2       0
+#define PMB_ADDR_WLAN1_PHY2      (10 | PMB_BUS_WLAN1_PHY2 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_WLAN1_PHY2     1
+
+#define PMB_BUS_MEMC             0
+#define PMB_ADDR_MEMC            (11 | PMB_BUS_MEMC << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_MEMC           1
+
+#define PMB_BUS_SYSP             0
+#define PMB_ADDR_SYSP            (0 | PMB_BUS_SYSP << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_SYSP           3
+
+#define PMB_BUS_PCIE0            1
+#define PMB_ADDR_PCIE0           (17 | PMB_BUS_PCIE0 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PCIE0          1
+
+#define PMB_BUS_ORION_CPU0       0
+#define PMB_ADDR_ORION_CPU0      (32 | PMB_BUS_ORION_CPU0 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_ORION_CPU0     1
+
+#define PMB_BUS_ORION_CPU1       0
+#define PMB_ADDR_ORION_CPU1      (33 | PMB_BUS_ORION_CPU1 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_ORION_CPU1     1
+
+#define PMB_BUS_ORION_CPU2       0
+#define PMB_ADDR_ORION_CPU2      (34 | PMB_BUS_ORION_CPU2 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_ORION_CPU2     1
+
+#define PMB_BUS_ORION_CPU3       0
+#define PMB_ADDR_ORION_CPU3      (35 | PMB_BUS_ORION_CPU3 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_ORION_CPU3     1
+
+#define PMB_BUS_ORION_NONCPU     0
+#define PMB_ADDR_ORION_NONCPU    (36 | PMB_BUS_ORION_NONCPU << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_ORION_NONCPU   1
+
+#define PMB_BUS_BIU_PLL          0
+#define PMB_ADDR_BIU_PLL         (38 | PMB_BUS_BIU_PLL << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_BIU_PLL        0
+
+#define PMB_BUS_BIU_BPCM         0
+#define PMB_ADDR_BIU_BPCM        (39 | PMB_BUS_BIU_BPCM << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_BIU_BPCM       1
+
+#define PMB_BUS_PCM              PMB_BUS_PERIPH
+#define PMB_ADDR_PCM             (16 | PMB_BUS_PCM << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PCM            4
+
+enum {
+       PCM_Zone_Main,
+       PCM_Zone_PCM = 3
+};
+
+//--------- SOFT Reset bits for PCM ------------------------
+#define   BPCM_PCM_SRESET_PCM_N       0x00000040
+
+#define RCAL_0P25UM_HORZ          0
+#define RCAL_0P25UM_VERT          1
+#define RCAL_0P5UM_HORZ           2
+#define RCAL_0P5UM_VERT           3
+#define RCAL_1UM_HORZ             4
+#define RCAL_1UM_VERT             5
+#define PMMISC_RMON_EXT_REG       ((RCAL_1UM_VERT + 1)/2)
+#define PMMISC_RMON_VALID_MASK    (0x1<<16)
+
+#endif