Add Broadcom's code for bcm63xx support

[project/bcm63xx/atf.git] / plat / bcm / include / pmc_addr_6855.h

diff --git a/plat/bcm/include/pmc_addr_6855.h b/plat/bcm/include/pmc_addr_6855.h
new file mode 100644 (file)
index 0000000..2f24616
--- /dev/null
+++ b/plat/bcm/include/pmc_addr_6855.h
@@ -0,0 +1,106 @@
+/*
+<:copyright-BRCM:2019:DUAL/GPL:standard 
+
+   Copyright (c) 2019 Broadcom 
+   All Rights Reserved
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License, version 2, as published by
+the Free Software Foundation (the "GPL").
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+
+A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by
+writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.
+
+:> 
+*/
+
+#ifndef PMC_ADDR_6855_H__
+#define PMC_ADDR_6855_H__
+
+#define PMB_BUS_MAX              2
+#define PMB_BUS_ID_SHIFT         12
+
+#define PMB_BUS_PERIPH           0
+#define PMB_ADDR_PERIPH          (0 | PMB_BUS_PERIPH << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PERIPH         4
+
+#define PMB_BUS_CHIP_CLKRST      0
+#define PMB_ADDR_CHIP_CLKRST     (1 | PMB_BUS_CHIP_CLKRST << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_CHIP_CLKRST    0
+
+#define PMB_BUS_SYSPLL           0
+#define PMB_ADDR_SYSPLL          (3 | PMB_BUS_SYSPLL << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_SYSPLL         0
+
+#define PMB_BUS_PVTMON           0
+#define PMB_ADDR_PVTMON          (6 | PMB_BUS_PVTMON << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PVTMON         0
+
+#define PMB_BUS_MEMC             0
+#define PMB_ADDR_MEMC            (8 | PMB_BUS_MEMC << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_MEMC           1
+
+#define PMB_BUS_USB20_2X         1
+#define PMB_ADDR_USB20_2X        (10 | PMB_BUS_USB20_2X << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_USB20_2X       4
+
+#define PMB_BUS_WAN              1
+#define PMB_ADDR_WAN             (11 | PMB_BUS_WAN << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_WAN            3
+
+#define PMB_BUS_XRDP              1
+#define PMB_ADDR_XRDP             (12 | PMB_BUS_XRDP << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_XRDP            3
+
+#define PMB_BUS_PCIE0             1
+#define PMB_ADDR_PCIE0            (17 | PMB_BUS_PCIE0 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PCIE0           1
+
+#define PMB_BUS_PCIE1             1
+#define PMB_ADDR_PCIE1            (18 | PMB_BUS_PCIE1 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PCIE1           1
+
+#define PMB_BUS_WLAN0            1
+#define PMB_ADDR_WLAN0           (19 | PMB_BUS_WLAN0 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_WLAN0          1
+
+#define PMB_BUS_WLAN0_PHY1       1
+#define PMB_ADDR_WLAN0_PHY1      (20 | PMB_BUS_WLAN0_PHY1 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_WLAN0_PHY1     1
+
+#define PMB_BUS_WLAN0_PHY2       1
+#define PMB_ADDR_WLAN0_PHY2      (21 | PMB_BUS_WLAN0_PHY2 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_WLAN0_PHY2     1
+
+#define PMB_BUS_ORION_CPU0       0
+#define PMB_ADDR_ORION_CPU0      (32 | PMB_BUS_ORION_CPU0 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_ORION_CPU0     1
+
+#define PMB_BUS_ORION_CPU1       0
+#define PMB_ADDR_ORION_CPU1      (33 | PMB_BUS_ORION_CPU1 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_ORION_CPU1     1
+
+#define PMB_BUS_ORION_CPU2       0
+#define PMB_ADDR_ORION_CPU2      (33 | PMB_BUS_ORION_CPU2 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_ORION_CPU2     1
+
+#define PMB_BUS_ORION_NONCPU     0
+#define PMB_ADDR_ORION_NONCPU    (36 | PMB_BUS_ORION_NONCPU << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_ORION_NONCPU   1
+
+#define PMB_BUS_BIU_PLL          0
+#define PMB_ADDR_BIU_PLL         (38 | PMB_BUS_BIU_PLL << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_BIU_PLL        0
+
+#define PMB_BUS_BIU_BPCM         0
+#define PMB_ADDR_BIU_BPCM        (39 | PMB_BUS_BIU_BPCM << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_BIU_BPCM       1
+
+#endif