[adm5120] change switch register access macros

[openwrt/svn-archive/archive.git] / target / linux / adm5120 / files / arch / mips / adm5120 / memory.c

diff --git a/target/linux/adm5120/files/arch/mips/adm5120/memory.c b/target/linux/adm5120/files/arch/mips/adm5120/memory.c
index 1bde6b02d59c14e770390be4877bf5bf94500cf7..1803f2bfc592aba284950d8f56f4c6ea4c6519fd 100644 (file)
--- a/target/linux/adm5120/files/arch/mips/adm5120/memory.c
+++ b/target/linux/adm5120/files/arch/mips/adm5120/memory.c
@@ -24,41 +24,37 @@
 #include <linux/init.h>
 #include <linux/types.h>
 #include <linux/kernel.h>
+#include <linux/io.h>
 
 #include <asm/bootinfo.h>
 #include <asm/addrspace.h>
 
-#include <asm/mach-adm5120/adm5120_info.h>
-#include <asm/mach-adm5120/adm5120_defs.h>
-#include <asm/mach-adm5120/adm5120_switch.h>
-#include <asm/mach-adm5120/adm5120_mpmc.h>
+#include <adm5120_info.h>
+#include <adm5120_defs.h>
+#include <adm5120_switch.h>
+#include <adm5120_mpmc.h>
 
-#define SWITCH_READ(r) *(u32 *)(KSEG1ADDR(ADM5120_SWITCH_BASE)+(r))
-#define SWITCH_WRITE(r,v) *(u32 *)(KSEG1ADDR(ADM5120_SWITCH_BASE)+(r))=(v)
-
-#define MPMC_READ(r) *(u32 *)(KSEG1ADDR(ADM5120_SWITCH_BASE)+(r))
-#define MPMC_WRITE(r,v) *(u32 *)(KSEG1ADDR(ADM5120_SWITCH_BASE)+(r))=(v)
-
-#if 1
-#  define mem_dbg(f, a...)     printk("mem_detect: " f, ## a)
+#ifdef DEBUG
+#  define mem_dbg(f, a...)     printk(KERN_INFO "mem_detect: " f, ## a)
 #else
 #  define mem_dbg(f, a...)
 #endif
 
-#define MEM_WR_DELAY   10000 /* 0.01 usec */
-
 unsigned long adm5120_memsize;
 
+#define MEM_READL(a)           __raw_readl((void __iomem *)(a))
+#define MEM_WRITEL(a, v)       __raw_writel((v), (void __iomem *)(a))
+
 static int __init mem_check_pattern(u8 *addr, unsigned long offs)
 {
-       volatile u32 *p1 = (volatile u32 *)addr;
-       volatile u32 *p2 = (volatile u32 *)(addr+offs);
-       u32 t,u,v;
+       u32 *p1 = (u32 *)addr;
+       u32 *p2 = (u32 *)(addr+offs);
+       u32 t, u, v;
 
        /* save original value */
-       t = *p1;
-       u = *p2;
+       t = MEM_READL(p1);
 
+       u = MEM_READL(p2);
        if (t != u)
                return 0;
 
@@ -68,15 +64,14 @@ static int __init mem_check_pattern(u8 *addr, unsigned long offs)
 
        mem_dbg("write 0x%08X to 0x%08lX\n", v, (unsigned long)p1);
 
-       *p1 = v;
-       mem_dbg("delay %d ns\n", MEM_WR_DELAY);
-       adm5120_ndelay(MEM_WR_DELAY);
-       u = *p2;
+       MEM_WRITEL(p1, v);
+       adm5120_ndelay(1000);
+       u = MEM_READL(p2);
 
        mem_dbg("pattern at 0x%08lX is 0x%08X\n", (unsigned long)p2, u);
 
        /* restore original value */
-       *p1 = t;
+       MEM_WRITEL(p1, t);
 
        return (v == u);
 }
@@ -87,7 +82,7 @@ static void __init adm5120_detect_memsize(void)
        u32     size, maxsize;
        u8      *p;
 
-       memctrl = SWITCH_READ(SWITCH_REG_MEMCTRL);
+       memctrl = SW_READ_REG(SWITCH_REG_MEMCTRL);
        switch (memctrl & MEMCTRL_SDRS_MASK) {
        case MEMCTRL_SDRS_4M:
                maxsize = 4 << 20;
@@ -103,11 +98,6 @@ static void __init adm5120_detect_memsize(void)
                break;
        }
 
-       /* disable buffers for both SDRAM banks */
-       mem_dbg("disable buffers for both banks\n");
-       MPMC_WRITE(MPMC_REG_DC0, MPMC_READ(MPMC_REG_DC0) & ~DC_BE);
-       MPMC_WRITE(MPMC_REG_DC1, MPMC_READ(MPMC_REG_DC1) & ~DC_BE);
-
        mem_dbg("checking for %uMB chip in 1st bank\n", maxsize >> 20);
 
        /* detect size of the 1st SDRAM bank */
@@ -138,9 +128,8 @@ static void __init adm5120_detect_memsize(void)
        mem_dbg("check presence of 2nd bank\n");
 
        p = (u8 *)KSEG1ADDR(maxsize+size-4);
-       if (mem_check_pattern(p, 0)) {
+       if (mem_check_pattern(p, 0))
                adm5120_memsize += size;
-       }
 
        if (maxsize != size) {
                /* adjusting MECTRL register */
@@ -159,17 +148,12 @@ static void __init adm5120_detect_memsize(void)
                        memctrl |= MEMCTRL_SDRS_64M;
                        break;
                }
-               SWITCH_WRITE(SWITCH_REG_MEMCTRL, memctrl);
+               SW_WRITE_REG(SWITCH_REG_MEMCTRL, memctrl);
        }
 
 out:
-       /* reenable buffer for both SDRAM banks */
-       mem_dbg("enable buffers for both banks\n");
-       MPMC_WRITE(MPMC_REG_DC0, MPMC_READ(MPMC_REG_DC0) | DC_BE);
-       MPMC_WRITE(MPMC_REG_DC1, MPMC_READ(MPMC_REG_DC1) | DC_BE);
-
        mem_dbg("%dx%uMB memory found\n", (adm5120_memsize == size) ? 1 : 2 ,
-               size >>20);
+               size>>20);
 }
 
 void __init adm5120_mem_init(void)