add support for titan variant (WRTP54G) (#6185)

[openwrt/staging/wigyori.git] / target / linux / ar7 / files / include / asm-mips / ar7 / ar7.h

diff --git a/target/linux/ar7/files/include/asm-mips/ar7/ar7.h b/target/linux/ar7/files/include/asm-mips/ar7/ar7.h
index d972e09ef6c9453cd597fb6fb36ad3969d7db823..19b5289fdd87244fa17907541b9330ac7005987d 100644 (file)
--- a/target/linux/ar7/files/include/asm-mips/ar7/ar7.h
+++ b/target/linux/ar7/files/include/asm-mips/ar7/ar7.h
@@ -44,6 +44,11 @@
 #define UR8_REGS_WDT   (AR7_REGS_BASE + 0x0b00)
 #define UR8_REGS_UART1 (AR7_REGS_BASE + 0x0f00)
 
+#define TITAN_REGS_MAC0                (0x08640000)
+#define TITAN_REGS_MAC1                (TITAN_REGS_MAC0 + 0x0800)
+#define TITAN_REGS_VLYNQ0      (AR7_REGS_BASE + 0x1c00)
+#define TITAN_REGS_VLYNQ1      (AR7_REGS_BASE + 0x1300)
+
 #define AR7_RESET_PEREPHERIAL  0x0
 #define AR7_RESET_SOFTWARE     0x4
 #define AR7_RESET_STATUS       0x8
@@ -53,15 +58,30 @@
 #define AR7_RESET_BIT_MDIO     22
 #define AR7_RESET_BIT_EPHY     26
 
+#define TITAN_RESET_BIT_EPHY1  28
+
 /* GPIO control registers */
 #define AR7_GPIO_INPUT 0x0
 #define AR7_GPIO_OUTPUT        0x4
 #define AR7_GPIO_DIR   0x8
 #define AR7_GPIO_ENABLE        0xc
+#define TITAN_GPIO_INPUT_0     0x0
+#define TITAN_GPIO_INPUT_1     0x4
+#define TITAN_GPIO_OUTPUT_0    0x8
+#define TITAN_GPIO_OUTPUT_1    0xc
+#define TITAN_GPIO_DIR_0       0x10
+#define TITAN_GPIO_DIR_1       0x14
+#define TITAN_GPIO_ENBL_0      0x18
+#define TITAN_GPIO_ENBL_1      0x1c
 
 #define AR7_CHIP_7100  0x18
 #define AR7_CHIP_7200  0x2b
 #define AR7_CHIP_7300  0x05
+#define AR7_CHIP_TITAN 0x07
+#define TITAN_CHIP_1050        0x0f
+#define TITAN_CHIP_1055        0x0e
+#define TITAN_CHIP_1056        0x0d
+#define TITAN_CHIP_1060        0x07
 
 /* Interrupts */
 #define AR7_IRQ_UART0  15
@@ -86,14 +106,22 @@ struct plat_dsl_data {
 
 extern int ar7_cpu_clock, ar7_bus_clock, ar7_dsp_clock;
 
+static inline int ar7_is_titan(void)
+{
+       return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x24)) & 0xffff) ==
+               AR7_CHIP_TITAN;
+}
+
 static inline u16 ar7_chip_id(void)
 {
-       return readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x14)) & 0xffff;
+       return ar7_is_titan() ? AR7_CHIP_TITAN : (readl((void *)
+               KSEG1ADDR(AR7_REGS_GPIO + 0x14)) & 0xffff);
 }
 
 static inline u8 ar7_chip_rev(void)
 {
-       return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x14)) >> 16) & 0xff;
+       return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + (ar7_is_titan() ? 0x24 :
+               0x14))) >> 16) & 0xff;
 }
 
 static inline int ar7_cpu_freq(void)