ar71xx: fix AR934X clock frequency calculation

[openwrt/staging/chunkeey.git] / target / linux / ar71xx / files / arch / mips / include / asm / mach-ar71xx / ar71xx.h

diff --git a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
index 97ac835dc0b0257224a76a33ec498a775b3649b3..87a352cc432a092a0e8d1983bfb3e579b859aeaa 100644 (file)
--- a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
+++ b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
@@ -212,6 +212,7 @@ extern enum ar71xx_soc_type ar71xx_soc;
 #define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK     0x7
 
 #define AR934X_PLL_REG_CPU_CONFIG      0x00
+#define AR934X_PLL_REG_DDR_CONFIG      0x04
 #define AR934X_PLL_REG_DDR_CTRL_CLOCK  0x8
 
 #define AR934X_CPU_PLL_CFG_OUTDIV_MSB  21
@@ -372,6 +373,13 @@ extern enum ar71xx_soc_type ar71xx_soc;
 
 #define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_RESET       1
 
+#define AR934X_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS         BIT(2)
+#define AR934X_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS         BIT(3)
+#define AR934X_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS         BIT(4)
+#define AR934X_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL     BIT(20)
+#define AR934X_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL     BIT(21)
+#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL     BIT(24)
+
 extern void __iomem *ar71xx_pll_base;
 
 static inline void ar71xx_pll_wr(unsigned reg, u32 val)