kernel: bump to 4.9.105

[openwrt/staging/stintel.git] / target / linux / ar71xx / patches-4.9 / 106-01-MIPS-ath79-fix-AR724X_PLL_REG_PCIE_CONFIG-offset.patch

diff --git a/target/linux/ar71xx/patches-4.9/106-01-MIPS-ath79-fix-AR724X_PLL_REG_PCIE_CONFIG-offset.patch b/target/linux/ar71xx/patches-4.9/106-01-MIPS-ath79-fix-AR724X_PLL_REG_PCIE_CONFIG-offset.patch
deleted file mode 100644 (file)
index e785b30..0000000
--- a/target/linux/ar71xx/patches-4.9/106-01-MIPS-ath79-fix-AR724X_PLL_REG_PCIE_CONFIG-offset.patch
+++ /dev/null
@@ -1,29 +0,0 @@
-From 0f15814bcdf59f10b708a3fba636acb089e9a4f1 Mon Sep 17 00:00:00 2001
-From: Mathias Kresin <dev@kresin.me>
-Date: Thu, 30 Mar 2017 15:34:39 +0200
-Subject: [PATCH] MIPS: ath79: fix AR724X_PLL_REG_PCIE_CONFIG offset
-
-According to the QCA u-boot source the "PCIE Phase Lock Loop
-Configuration (PCIE_PLL_CONFIG)" register is for all SoCs except the
-QCA955X and QCA956X at offset 0x10.
-
-Since the PCIE PLL config register is only defined for the AR724x fix
-only this value. The value is wrong since the day it was added and isn't
-yet used by any driver.
-
-Signed-off-by: Mathias Kresin <dev@kresin.me>
----
- arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-@@ -167,7 +167,7 @@
- #define AR71XX_AHB_DIV_MASK           0x7
- 
- #define AR724X_PLL_REG_CPU_CONFIG     0x00
--#define AR724X_PLL_REG_PCIE_CONFIG    0x18
-+#define AR724X_PLL_REG_PCIE_CONFIG    0x10
- 
- #define AR724X_PLL_FB_SHIFT           0
- #define AR724X_PLL_FB_MASK            0x3ff