ar71xx: Add kernel 4.9 support

[openwrt/staging/stintel.git] / target / linux / ar71xx / patches-4.9 / 622-MIPS-ath79-add-more-register-defines-for-QCA956x-SoC.patch

diff --git a/target/linux/ar71xx/patches-4.9/622-MIPS-ath79-add-more-register-defines-for-QCA956x-SoC.patch b/target/linux/ar71xx/patches-4.9/622-MIPS-ath79-add-more-register-defines-for-QCA956x-SoC.patch
new file mode 100644 (file)
index 0000000..cab2f6f
--- /dev/null
+++ b/target/linux/ar71xx/patches-4.9/622-MIPS-ath79-add-more-register-defines-for-QCA956x-SoC.patch
@@ -0,0 +1,38 @@
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -157,6 +157,10 @@
+ #define QCA956X_EHCI0_BASE    0x1b000000
+ #define QCA956X_EHCI1_BASE    0x1b400000
+ #define QCA956X_EHCI_SIZE     0x200
++#define QCA956X_GMAC_SGMII_BASE       (AR71XX_APB_BASE + 0x00070000)
++#define QCA956X_GMAC_SGMII_SIZE       0x64
++#define QCA956X_PLL_BASE      (AR71XX_APB_BASE + 0x00050000)
++#define QCA956X_PLL_SIZE      0x50
+ #define QCA956X_GMAC_BASE     (AR71XX_APB_BASE + 0x00070000)
+ #define QCA956X_GMAC_SIZE     0x64
+ 
+@@ -414,6 +418,7 @@
+ #define QCA956X_PLL_DDR_CONFIG_REG                    0x08
+ #define QCA956X_PLL_DDR_CONFIG1_REG                   0x0c
+ #define QCA956X_PLL_CLK_CTRL_REG                      0x10
++#define QCA956X_PLL_ETH_XMII_CONTROL_REG              0x30
+ 
+ #define QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT           12
+ #define QCA956X_PLL_CPU_CONFIG_REFDIV_MASK            0x1f
+@@ -1196,4 +1201,16 @@
+ #define QCA955X_ETH_CFG_TXE_DELAY_MASK        0x3
+ #define QCA955X_ETH_CFG_TXE_DELAY_SHIFT       20
+ 
++/*
++ * QCA956X GMAC Interface
++ */
++
++#define QCA956X_GMAC_REG_ETH_CFG              0x00
++
++#define QCA956X_ETH_CFG_SW_ONLY_MODE          BIT(7)
++#define QCA956X_ETH_CFG_SW_PHY_SWAP               BIT(8)
++#define QCA956X_ETH_CFG_SW_PHY_ADDR_SWAP      BIT(9)
++#define QCA956X_ETH_CFG_SW_APB_ACCESS         BIT(10)
++#define QCA956X_ETH_CFG_SW_ACC_MSB_FIRST      BIT(13)
++
+ #endif /* __ASM_MACH_AR71XX_REGS_H */