treewide: remove files for building 5.10 kernel

[openwrt/staging/stintel.git] / target / linux / at91 / patches-5.10 / 111-clk-at91-sama7g5-register-cpu-clock.patch

diff --git a/target/linux/at91/patches-5.10/111-clk-at91-sama7g5-register-cpu-clock.patch b/target/linux/at91/patches-5.10/111-clk-at91-sama7g5-register-cpu-clock.patch
deleted file mode 100644 (file)
index dc55e32..0000000
--- a/target/linux/at91/patches-5.10/111-clk-at91-sama7g5-register-cpu-clock.patch
+++ /dev/null
@@ -1,65 +0,0 @@
-From 36e97c421dd9f866e31fe14bcb7af01334791890 Mon Sep 17 00:00:00 2001
-From: Claudiu Beznea <claudiu.beznea@microchip.com>
-Date: Thu, 19 Nov 2020 17:43:17 +0200
-Subject: [PATCH 111/247] clk: at91: sama7g5: register cpu clock
-
-Register CPU clock as being the master clock prescaler. This would
-be used by DVFS. The block schema of SAMA7G5's PMC contains also a divider
-between master clock prescaler and CPU (PMC_CPU_RATIO.RATIO) but the
-frequencies supported by SAMA7G5 could be directly received from
-CPUPLL + master clock prescaler and the extra divider would do no work in
-case it would be enabled.
-
-Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
-Link: https://lore.kernel.org/r/1605800597-16720-12-git-send-email-claudiu.beznea@microchip.com
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- drivers/clk/at91/sama7g5.c       | 13 ++++++-------
- include/dt-bindings/clock/at91.h |  1 +
- 2 files changed, 7 insertions(+), 7 deletions(-)
-
---- a/drivers/clk/at91/sama7g5.c
-+++ b/drivers/clk/at91/sama7g5.c
-@@ -904,7 +904,7 @@ static void __init sama7g5_pmc_setup(str
-       if (IS_ERR(regmap))
-               return;
- 
--      sama7g5_pmc = pmc_data_allocate(PMC_ETHPLL + 1,
-+      sama7g5_pmc = pmc_data_allocate(PMC_CPU + 1,
-                                       nck(sama7g5_systemck),
-                                       nck(sama7g5_periphck),
-                                       nck(sama7g5_gck), 8);
-@@ -981,18 +981,17 @@ static void __init sama7g5_pmc_setup(str
-               }
-       }
- 
--      parent_names[0] = md_slck_name;
--      parent_names[1] = "mainck";
--      parent_names[2] = "cpupll_divpmcck";
--      parent_names[3] = "syspll_divpmcck";
--      hw = at91_clk_register_master_pres(regmap, "mck0_pres", 4, parent_names,
-+      parent_names[0] = "cpupll_divpmcck";
-+      hw = at91_clk_register_master_pres(regmap, "cpuck", 1, parent_names,
-                                          &mck0_layout, &mck0_characteristics,
-                                          &pmc_mck0_lock,
-                                          CLK_SET_RATE_PARENT, 0);
-       if (IS_ERR(hw))
-               goto err_free;
- 
--      hw = at91_clk_register_master_div(regmap, "mck0_div", "mck0_pres",
-+      sama7g5_pmc->chws[PMC_CPU] = hw;
-+
-+      hw = at91_clk_register_master_div(regmap, "mck0", "cpuck",
-                                         &mck0_layout, &mck0_characteristics,
-                                         &pmc_mck0_lock, 0);
-       if (IS_ERR(hw))
---- a/include/dt-bindings/clock/at91.h
-+++ b/include/dt-bindings/clock/at91.h
-@@ -34,6 +34,7 @@
- #define PMC_AUDIOPMCPLL               (PMC_MAIN + 6)
- #define PMC_AUDIOIOPLL                (PMC_MAIN + 7)
- #define PMC_ETHPLL            (PMC_MAIN + 8)
-+#define PMC_CPU                       (PMC_MAIN + 9)
- 
- #ifndef AT91_PMC_MOSCS
- #define AT91_PMC_MOSCS                0               /* MOSCS Flag */