at91: add kernel support for sama7g5 soc

[openwrt/staging/mkresin.git] / target / linux / at91 / patches-5.10 / 224-ARM-dts-at91-sama7g5-add-ram-controllers.patch

diff --git a/target/linux/at91/patches-5.10/224-ARM-dts-at91-sama7g5-add-ram-controllers.patch b/target/linux/at91/patches-5.10/224-ARM-dts-at91-sama7g5-add-ram-controllers.patch
new file mode 100644 (file)
index 0000000..3c36a41
--- /dev/null
+++ b/target/linux/at91/patches-5.10/224-ARM-dts-at91-sama7g5-add-ram-controllers.patch
@@ -0,0 +1,41 @@
+From cf96a88e44f1fde9f1a30ab335329ff9e895e6f8 Mon Sep 17 00:00:00 2001
+From: Claudiu Beznea <claudiu.beznea@microchip.com>
+Date: Mon, 23 Aug 2021 16:19:13 +0300
+Subject: [PATCH 224/247] ARM: dts: at91: sama7g5: add ram controllers
+
+Add RAM and RAMC PHY controllers. These are necessary for platform
+specific power management code.
+
+Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
+Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
+Link: https://lore.kernel.org/r/20210823131915.23857-3-claudiu.beznea@microchip.com
+---
+ arch/arm/boot/dts/sama7g5.dtsi | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi
+index cc6be6db7b80..ecabab4343b6 100644
+--- a/arch/arm/boot/dts/sama7g5.dtsi
++++ b/arch/arm/boot/dts/sama7g5.dtsi
+@@ -515,6 +515,18 @@ spi11: spi@400 {
+                       };
+               };
+ 
++              uddrc: uddrc@e3800000 {
++                      compatible = "microchip,sama7g5-uddrc";
++                      reg = <0xe3800000 0x4000>;
++                      status = "okay";
++              };
++
++              ddr3phy: ddr3phy@e3804000 {
++                      compatible = "microchip,sama7g5-ddr3phy";
++                      reg = <0xe3804000 0x1000>;
++                      status = "okay";
++              };
++
+               gic: interrupt-controller@e8c11000 {
+                       compatible = "arm,cortex-a7-gic";
+                       #interrupt-cells = <3>;
+-- 
+2.32.0
+