ath79: add Embedded Wireless Balin Platform

[openwrt/openwrt.git] / target / linux / ath79 / dts / ar9344_zbtlink_zbt-wd323.dts

diff --git a/target/linux/ath79/dts/ar9344_zbtlink_zbt-wd323.dts b/target/linux/ath79/dts/ar9344_zbtlink_zbt-wd323.dts
index 3fb37f2ae26ca3b6894defdef53913cdf73879d0..8fc21be1dcb4965f886d483b72d09f31d6cc7383 100644 (file)
--- a/target/linux/ath79/dts/ar9344_zbtlink_zbt-wd323.dts
+++ b/target/linux/ath79/dts/ar9344_zbtlink_zbt-wd323.dts
@@ -1,11 +1,10 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/dts-v1/;
+
+#include "ar9344.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
 
-#include "ar9344.dtsi"
-
 / {
        model = "ZBT WD323";
        compatible = "zbtlink,zbt-wd323", "qca,ar9344";
@@ -31,10 +30,6 @@
                sda-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
                scl-gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
 
-               /* can be removed on 4.19 */
-               gpios = <&gpio 19 GPIO_ACTIVE_LOW>,
-                       <&gpio 15 GPIO_ACTIVE_LOW>;
-
                pcf8563: pcf8563@51 {
                        compatible = "nxp,pcf8563";
                        reg = <0x51>;
@@ -49,18 +44,18 @@
                pinctrl-0 = <&enable_gpio20_gpio22>;
 
                wifi {
-                       label = "zbt-wd323:green:wifi";
+                       label = "green:wifi";
                        gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
                        linux,default-trigger = "phy0tpt";
                };
 
                lan1 {
-                       label = "zbt-wd323:orange:lan1";
+                       label = "orange:lan1";
                        gpios = <&gpio 20 GPIO_ACTIVE_LOW>;
                };
 
                lan2 {
-                       label = "zbt-wd323:orange:lan2";
+                       label = "orange:lan2";
                        gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
                };
        };
@@ -73,10 +68,6 @@
        pinctrl-0 = <&enable_gpio21>;
 };
 
-&uart {
-       status = "okay";
-};
-
 &gpio {
        pinctrl-names = "default";
        pinctrl-0 = <&jtag_disable_pins>;
@@ -93,16 +84,17 @@
 &eth0 {
        status = "okay";
        phy-handle = <&swphy4>;
-       mtd-mac-address = <&art 0x0>;
+       nvmem-cells = <&macaddr_art_0>;
+       nvmem-cell-names = "mac-address";
 };
 
 &eth1 {
        status = "okay";
-       mtd-mac-address = <&art 0x6>;
+       nvmem-cells = <&macaddr_art_6>;
+       nvmem-cell-names = "mac-address";
 };
 
 &spi {
-       num-chipselects = <1>;
        status = "okay";
 
        flash@0 {
@@ -160,3 +152,17 @@
                pinctrl-single,bits = <0x14 0x0 0xff00>;
        };
 };
+
+&art {
+       compatible = "nvmem-cells";
+       #address-cells = <1>;
+       #size-cells = <1>;
+
+       macaddr_art_0: macaddr@0 {
+               reg = <0x0 0x6>;
+       };
+
+       macaddr_art_6: macaddr@6 {
+               reg = <0x6 0x6>;
+       };
+};