ath79: add support for OCEDO Ursus

[openwrt/staging/hauke.git] / target / linux / ath79 / dts / qca9558_ocedo_ursus.dts

diff --git a/target/linux/ath79/dts/qca9558_ocedo_ursus.dts b/target/linux/ath79/dts/qca9558_ocedo_ursus.dts
new file mode 100644 (file)
index 0000000..1a92da3
--- /dev/null
+++ b/target/linux/ath79/dts/qca9558_ocedo_ursus.dts
@@ -0,0 +1,147 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+#include "qca9557.dtsi"
+
+/ {
+       compatible = "ocedo,ursus", "qca,qca9558";
+       model = "OCEDO Ursus";
+
+       chosen {
+               bootargs = "console=ttyS0,115200n8";
+       };
+
+       leds {
+               compatible = "gpio-leds";
+
+               wifi2 {
+                       label = "ursus:green:wlan2g";
+                       gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
+                       linux,default-trigger = "phy1tpt";
+               };
+
+               wifi5 {
+                       label = "ursus:green:wlan5g";
+                       gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
+                       linux,default-trigger = "phy0tpt";
+               };
+
+       };
+
+};
+
+&pcie1 {
+       status = "okay";
+};
+
+&uart {
+       status = "okay";
+};
+
+&pll {
+       clocks = <&extosc>;
+};
+
+&spi {
+       status = "okay";
+       num-cs = <1>;
+
+       flash@0 {
+               compatible = "jedec,spi-nor";
+               reg = <0>;
+               spi-max-frequency = <25000000>;
+
+               partitions {
+                       compatible = "fixed-partitions";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+
+                       uboot: partition@0 {
+                               label = "u-boot";
+                               reg = <0x000000 0x040000>;
+                               read-only;
+                       };
+
+                       partition@40000 {
+                               label = "u-boot-env";
+                               reg = <0x040000 0x010000>;
+                       };
+
+                       partition@50000 {
+                               compatible = "denx,uimage";
+                               label = "firmware";
+                               reg = <0x050000 0x740000>;
+                       };
+
+                       partition@790000 {
+                               label = "vendor";
+                               reg = <0x790000 0x740000>;
+                               read-only;
+                       };
+
+                       partition@ed0000 {
+                               label = "data";
+                               reg = <0xed0000 0x110000>;
+                               read-only;
+                       };
+
+                       partition@fe0000 {
+                               label = "id";
+                               reg = <0xfe0000 0x010000>;
+                               read-only;
+                       };
+
+                       art: partition@ff0000 {
+                               label = "art";
+                               reg = <0xff0000 0x010000>;
+                               read-only;
+                       };
+               };
+       };
+};
+
+&wmac {
+       status = "okay";
+
+       mtd-cal-data = <&art 0x1000>;
+       mtd-mac-address = <&art 0x06>;
+};
+
+&mdio0 {
+       status = "okay";
+
+       phy1: ethernet-phy@1 {
+               reg = <1>;
+       };
+
+       phy2: ethernet-phy@2 {
+               reg = <2>;
+       };
+};
+
+&eth0 {
+       status = "okay";
+       mtd-mac-address = <&art 0x00>;
+       phy-handle = <&phy1>;
+       pll-data = <0xa6000000 0x80000101 0x80001313>;
+
+       gmac_config: gmac-config {
+               device = <&gmac>;
+
+               rxdv-delay = <3>;
+               rxd-delay = <3>;
+               txen-delay = <0>;
+               txd-delay = <0>;
+               rgmii-enabled = <1>;
+       };
+};
+
+&eth1 {
+       status = "okay";
+       mtd-mac-address = <&art 0x12>;
+       phy-handle = <&phy2>;
+       pll-data = <0x3000101 0x101 0x1313>;
+};