brcm2708: organize kernel patches

[openwrt/openwrt.git] / target / linux / brcm2708 / patches-4.19 / 950-0693-drm-vc4-Fix-X-Y-positioning-of-planes-using-T_TILES-.patch

diff --git a/target/linux/brcm2708/patches-4.19/950-0693-drm-vc4-Fix-X-Y-positioning-of-planes-using-T_TILES-.patch b/target/linux/brcm2708/patches-4.19/950-0693-drm-vc4-Fix-X-Y-positioning-of-planes-using-T_TILES-.patch
new file mode 100644 (file)
index 0000000..6197d90
--- /dev/null
+++ b/target/linux/brcm2708/patches-4.19/950-0693-drm-vc4-Fix-X-Y-positioning-of-planes-using-T_TILES-.patch
@@ -0,0 +1,86 @@
+From 010e3665babdf589e26e2fb098ac1f39e519c0f6 Mon Sep 17 00:00:00 2001
+From: Boris Brezillon <boris.brezillon@bootlin.com>
+Date: Fri, 3 Aug 2018 11:22:31 +0200
+Subject: [PATCH] drm/vc4: Fix X/Y positioning of planes using T_TILES
+ modifier
+
+X/Y positioning of T-format buffers is quite tricky and the current
+implementation was failing to position a plane using this format
+correctly when the CRTC X, Y or both X and Y offsets were negative.
+It was also failing when the SRC X/Y offsets were != 0.
+
+Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
+Reviewed-by: Eric Anholt <eric@anholt.net>
+Link: https://patchwork.freedesktop.org/patch/msgid/20180803092231.26446-5-boris.brezillon@bootlin.com
+---
+ drivers/gpu/drm/vc4/vc4_plane.c | 50 ++++++++++++++++++++++++++++-----
+ 1 file changed, 43 insertions(+), 7 deletions(-)
+
+--- a/drivers/gpu/drm/vc4/vc4_plane.c
++++ b/drivers/gpu/drm/vc4/vc4_plane.c
+@@ -578,22 +578,58 @@ static int vc4_plane_mode_set(struct drm
+                                                (i ? h_subsample : 1) *
+                                                fb->format->cpp[i];
+               }
++
+               break;
+ 
+       case DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED: {
+-              /* For T-tiled, the FB pitch is "how many bytes from
+-               * one row to the next, such that pitch * tile_h ==
+-               * tile_size * tiles_per_row."
+-               */
+               u32 tile_size_shift = 12; /* T tiles are 4kb */
++              /* Whole-tile offsets, mostly for setting the pitch. */
++              u32 tile_w_shift = fb->format->cpp[0] == 2 ? 6 : 5;
+               u32 tile_h_shift = 5; /* 16 and 32bpp are 32 pixels high */
++              u32 tile_w_mask = (1 << tile_w_shift) - 1;
++              /* The height mask on 32-bit-per-pixel tiles is 63, i.e. twice
++               * the height (in pixels) of a 4k tile.
++               */
++              u32 tile_h_mask = (2 << tile_h_shift) - 1;
++              /* For T-tiled, the FB pitch is "how many bytes from one row to
++               * the next, such that
++               *
++               *      pitch * tile_h == tile_size * tiles_per_row
++               */
+               u32 tiles_w = fb->pitches[0] >> (tile_size_shift - tile_h_shift);
++              u32 tiles_l = vc4_state->src_x >> tile_w_shift;
++              u32 tiles_r = tiles_w - tiles_l;
++              u32 tiles_t = vc4_state->src_y >> tile_h_shift;
++              /* Intra-tile offsets, which modify the base address (the
++               * SCALER_PITCH0_TILE_Y_OFFSET tells HVS how to walk from that
++               * base address).
++               */
++              u32 tile_y = (vc4_state->src_y >> 4) & 1;
++              u32 subtile_y = (vc4_state->src_y >> 2) & 3;
++              u32 utile_y = vc4_state->src_y & 3;
++              u32 x_off = vc4_state->src_x & tile_w_mask;
++              u32 y_off = vc4_state->src_y & tile_h_mask;
+ 
+               tiling = SCALER_CTL0_TILING_256B_OR_T;
++              pitch0 = (VC4_SET_FIELD(x_off, SCALER_PITCH0_SINK_PIX) |
++                        VC4_SET_FIELD(y_off, SCALER_PITCH0_TILE_Y_OFFSET) |
++                        VC4_SET_FIELD(tiles_l, SCALER_PITCH0_TILE_WIDTH_L) |
++                        VC4_SET_FIELD(tiles_r, SCALER_PITCH0_TILE_WIDTH_R));
++              vc4_state->offsets[0] += tiles_t * (tiles_w << tile_size_shift);
++              vc4_state->offsets[0] += subtile_y << 8;
++              vc4_state->offsets[0] += utile_y << 4;
++
++              /* Rows of tiles alternate left-to-right and right-to-left. */
++              if (tiles_t & 1) {
++                      pitch0 |= SCALER_PITCH0_TILE_INITIAL_LINE_DIR;
++                      vc4_state->offsets[0] += (tiles_w - tiles_l) <<
++                                               tile_size_shift;
++                      vc4_state->offsets[0] -= (1 + !tile_y) << 10;
++              } else {
++                      vc4_state->offsets[0] += tiles_l << tile_size_shift;
++                      vc4_state->offsets[0] += tile_y << 10;
++              }
+ 
+-              pitch0 = (VC4_SET_FIELD(0, SCALER_PITCH0_TILE_Y_OFFSET) |
+-                        VC4_SET_FIELD(0, SCALER_PITCH0_TILE_WIDTH_L) |
+-                        VC4_SET_FIELD(tiles_w, SCALER_PITCH0_TILE_WIDTH_R));
+               break;
+       }
+