-From aaf3c3ab336f0ff54be5b7eb4de5adca3cd2c05a Mon Sep 17 00:00:00 2001
+From 85937f77d4cbafeba80594c3f760bed4ef114946 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Mon, 15 Feb 2016 17:31:41 -0800
-Subject: [PATCH 288/423] drm/vc4: Fix setting of vertical timings in the CRTC.
+Subject: [PATCH] drm/vc4: Fix setting of vertical timings in the CRTC.
It looks like when I went to add the interlaced bits, I just took the
existing PV_VERT* block and indented it, instead of copy and pasting