nuke old 2.6.23 code for brcm47xx

[openwrt/svn-archive/archive.git] / target / linux / brcm47xx / patches-2.6.23 / 622-ssb-cardbus-fixes.patch

diff --git a/target/linux/brcm47xx/patches-2.6.23/622-ssb-cardbus-fixes.patch b/target/linux/brcm47xx/patches-2.6.23/622-ssb-cardbus-fixes.patch
deleted file mode 100644 (file)
index 9f93572..0000000
--- a/target/linux/brcm47xx/patches-2.6.23/622-ssb-cardbus-fixes.patch
+++ /dev/null
@@ -1,108 +0,0 @@
---- a/drivers/ssb/driver_pcicore.c
-+++ b/drivers/ssb/driver_pcicore.c
-@@ -11,6 +11,7 @@
- #include <linux/ssb/ssb.h>
- #include <linux/pci.h>
- #include <linux/delay.h>
-+#include <linux/ssb/ssb_embedded.h>
- 
- #include "ssb_private.h"
- 
-@@ -27,6 +28,18 @@
-       ssb_write32(pc->dev, offset, value);
- }
- 
-+static inline
-+u16 pcicore_read16(struct ssb_pcicore *pc, u16 offset)
-+{
-+      return ssb_read16(pc->dev, offset);
-+}
-+
-+static inline
-+void pcicore_write16(struct ssb_pcicore *pc, u16 offset, u16 value)
-+{
-+      ssb_write16(pc->dev, offset, value);
-+}
-+
- /**************************************************
-  * Code for hostmode operation.
-  **************************************************/
-@@ -123,8 +136,10 @@
-       u32 addr = 0;
-       u32 tmp;
- 
--      if (unlikely(pc->cardbusmode && dev > 1))
-+      /* We do only have one cardbus device behind the bridge. */
-+      if (pc->cardbusmode && (dev >= 1))
-               goto out;
-+
-       if (bus == 0) {
-               /* Type 0 transaction */
-               if (unlikely(dev >= SSB_PCI_SLOT_MAX))
-@@ -324,7 +339,16 @@
-       pcicore_write32(pc, SSB_PCICORE_ARBCTL, val);
-       udelay(1); /* Assertion time demanded by the PCI standard */
- 
--      /*TODO cardbus mode */
-+      if (pc->dev->bus->has_cardbus_slot) {
-+              ssb_dprintk(KERN_INFO PFX "CardBus slot detected\n");
-+              pc->cardbusmode = 1;
-+              /* GPIO 1 resets the bridge */
-+              ssb_gpio_out(pc->dev->bus, 1, 1);
-+              ssb_gpio_outen(pc->dev->bus, 1, 1);
-+              pcicore_write16(pc, SSB_PCICORE_SPROM(0),
-+                              pcicore_read16(pc, SSB_PCICORE_SPROM(0))
-+                              | 0x0400);
-+      }
- 
-       /* 64MB I/O window */
-       pcicore_write32(pc, SSB_PCICORE_SBTOPCI0,
---- a/drivers/ssb/main.c
-+++ b/drivers/ssb/main.c
-@@ -559,6 +559,7 @@
-               goto out;
-       memcpy(&bus->boardinfo, &iv.boardinfo, sizeof(iv.boardinfo));
-       memcpy(&bus->sprom, &iv.sprom, sizeof(iv.sprom));
-+      bus->has_cardbus_slot = iv.has_cardbus_slot;
- out:
-       return err;
- }
---- a/include/linux/ssb/ssb.h
-+++ b/include/linux/ssb/ssb.h
-@@ -282,6 +282,8 @@
-       struct ssb_boardinfo boardinfo;
-       /* Contents of the SPROM. */
-       struct ssb_sprom sprom;
-+      /* If the board has a cardbus slot, this is set to true. */
-+      bool has_cardbus_slot;
- 
- #ifdef CONFIG_SSB_EMBEDDED
-       /* Lock for GPIO register access. */
-@@ -299,8 +301,13 @@
- 
- /* The initialization-invariants. */
- struct ssb_init_invariants {
-+      /* Versioning information about the PCB. */
-       struct ssb_boardinfo boardinfo;
-+      /* The SPROM information. That's either stored in an
-+       * EEPROM or NVRAM on the board. */
-       struct ssb_sprom sprom;
-+      /* If the board has a cardbus slot, this is set to true. */
-+      bool has_cardbus_slot;
- };
- /* Type of function to fetch the invariants. */
- typedef int (*ssb_invariants_func_t)(struct ssb_bus *bus,
---- a/include/linux/ssb/ssb_driver_pci.h
-+++ b/include/linux/ssb/ssb_driver_pci.h
-@@ -51,6 +51,11 @@
- #define  SSB_PCICORE_SBTOPCI1_MASK    0xFC000000
- #define SSB_PCICORE_SBTOPCI2          0x0108  /* Backplane to PCI translation 2 (sbtopci2) */
- #define  SSB_PCICORE_SBTOPCI2_MASK    0xC0000000
-+#define SSB_PCICORE_PCICFG0           0x0400  /* PCI config space 0 (rev >= 8) */
-+#define SSB_PCICORE_PCICFG1           0x0500  /* PCI config space 1 (rev >= 8) */
-+#define SSB_PCICORE_PCICFG2           0x0600  /* PCI config space 2 (rev >= 8) */
-+#define SSB_PCICORE_PCICFG3           0x0700  /* PCI config space 3 (rev >= 8) */
-+#define SSB_PCICORE_SPROM(wordoffset) (0x0800 + ((wordoffset) * 2)) /* SPROM shadow area (72 bytes) */
- 
- /* SBtoPCIx */
- #define SSB_PCICORE_SBTOPCI_MEM               0x00000000