cns3xxx: add linux 3.8 support and use it by default

[openwrt/svn-archive/archive.git] / target / linux / cns3xxx / patches-3.8 / 095-gpio_support.patch

diff --git a/target/linux/cns3xxx/patches-3.8/095-gpio_support.patch b/target/linux/cns3xxx/patches-3.8/095-gpio_support.patch
new file mode 100644 (file)
index 0000000..8f8f261
--- /dev/null
+++ b/target/linux/cns3xxx/patches-3.8/095-gpio_support.patch
@@ -0,0 +1,74 @@
+--- a/arch/arm/mach-cns3xxx/cns3420vb.c
++++ b/arch/arm/mach-cns3xxx/cns3420vb.c
+@@ -247,6 +247,10 @@ static void __init cns3420_init(void)
+ 
+       cns3xxx_ahci_init();
+       cns3xxx_sdhci_init();
++      cns3xxx_gpio_init( 0, 32, CNS3XXX_GPIOA_BASE_VIRT, IRQ_CNS3XXX_GPIOA,
++              NR_IRQS_CNS3XXX);
++      cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT, IRQ_CNS3XXX_GPIOB,
++              NR_IRQS_CNS3XXX + 32);
+ 
+       pm_power_off = cns3xxx_power_off;
+ }
+@@ -262,7 +266,7 @@ static struct map_desc cns3420_io_desc[]
+ 
+ static void __init cns3420_map_io(void)
+ {
+-      cns3xxx_map_io();
++      cns3xxx_common_init();
+       cns3xxx_pcie_iotable_init();
+       iotable_init(cns3420_io_desc, ARRAY_SIZE(cns3420_io_desc));
+ 
+--- a/arch/arm/mach-cns3xxx/core.c
++++ b/arch/arm/mach-cns3xxx/core.c
+@@ -82,7 +82,7 @@ static struct map_desc cns3xxx_io_desc[]
+       },
+ };
+ 
+-void __init cns3xxx_map_io(void)
++void __init cns3xxx_common_init(void)
+ {
+       iotable_init(cns3xxx_io_desc, ARRAY_SIZE(cns3xxx_io_desc));
+ }
+--- a/arch/arm/mach-cns3xxx/core.h
++++ b/arch/arm/mach-cns3xxx/core.h
+@@ -22,7 +22,7 @@ void __init cns3xxx_l2x0_init(void);
+ static inline void cns3xxx_l2x0_init(void) {}
+ #endif /* CONFIG_CACHE_L2X0 */
+ 
+-void __init cns3xxx_map_io(void);
++void __init cns3xxx_common_init(void);
+ void __init cns3xxx_init_irq(void);
+ int  __init cns3xxx_pcie_init(void);
+ void cns3xxx_power_off(void);
+--- a/arch/arm/Kconfig
++++ b/arch/arm/Kconfig
+@@ -361,6 +361,8 @@ config ARCH_CNS3XXX
+       bool "Cavium Networks CNS3XXX family"
+       select ARM_GIC
+       select CPU_V6K
++      select ARCH_REQUIRE_GPIOLIB
++      select GENERIC_IRQ_CHIP
+       select GENERIC_CLOCKEVENTS
+       select MIGHT_HAVE_CACHE_L2X0
+       select MIGHT_HAVE_PCI
+--- a/arch/arm/mach-cns3xxx/Makefile
++++ b/arch/arm/mach-cns3xxx/Makefile
+@@ -1,4 +1,4 @@
+-obj-$(CONFIG_ARCH_CNS3XXX)            += core.o pm.o devices.o
++obj-$(CONFIG_ARCH_CNS3XXX)            += core.o gpio.o pm.o devices.o
+ obj-$(CONFIG_PCI)                     += pcie.o
+ obj-$(CONFIG_MACH_CNS3420VB)          += cns3420vb.o
+ obj-$(CONFIG_SMP)                     += platsmp.o headsmp.o cns3xxx_fiq.o
+--- a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
++++ b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
+@@ -627,7 +627,7 @@ int cns3xxx_cpu_clock(void);
+ 
+ #if !defined(NR_IRQS) || (NR_IRQS < NR_IRQS_CNS3XXX)
+ #undef NR_IRQS
+-#define NR_IRQS                               NR_IRQS_CNS3XXX
++#define NR_IRQS                               (NR_IRQS_CNS3XXX + 64)
+ #endif
+ 
+ #endif        /* __MACH_BOARD_CNS3XXX_H */