kernel: v5.15: backport spi-nand supports from nand/next

[openwrt/staging/981213.git] / target / linux / generic / backport-5.15 / 420-mtd-next-02-mtd-spinand-gigadevice-add-support-for-GD5FxGQ4xExxG.patch

diff --git a/target/linux/generic/backport-5.15/420-mtd-next-02-mtd-spinand-gigadevice-add-support-for-GD5FxGQ4xExxG.patch b/target/linux/generic/backport-5.15/420-mtd-next-02-mtd-spinand-gigadevice-add-support-for-GD5FxGQ4xExxG.patch
new file mode 100644 (file)
index 0000000..09f0c44
--- /dev/null
+++ b/target/linux/generic/backport-5.15/420-mtd-next-02-mtd-spinand-gigadevice-add-support-for-GD5FxGQ4xExxG.patch
@@ -0,0 +1,63 @@
+From 573eec222bc82fb5e724586267fbbb1aed9ffd03 Mon Sep 17 00:00:00 2001
+From: Chuanhong Guo <gch981213@gmail.com>
+Date: Sun, 20 Mar 2022 17:59:58 +0800
+Subject: [PATCH 2/5] mtd: spinand: gigadevice: add support for GD5FxGQ4xExxG
+
+Add support for:
+ GD5F1GQ4RExxG
+ GD5F2GQ4{U,R}ExxG
+
+These chips differ from GD5F1GQ4UExxG only in chip ID, voltage
+and capacity.
+
+Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
+Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
+Link: https://lore.kernel.org/linux-mtd/20220320100001.247905-3-gch981213@gmail.com
+---
+ drivers/mtd/nand/spi/gigadevice.c | 30 ++++++++++++++++++++++++++++++
+ 1 file changed, 30 insertions(+)
+
+diff --git a/drivers/mtd/nand/spi/gigadevice.c b/drivers/mtd/nand/spi/gigadevice.c
+index da77ab20296e..85a61d3d8467 100644
+--- a/drivers/mtd/nand/spi/gigadevice.c
++++ b/drivers/mtd/nand/spi/gigadevice.c
+@@ -333,6 +333,36 @@ static const struct spinand_info gigadevice_spinand_table[] = {
+                    SPINAND_HAS_QE_BIT,
+                    SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+                                    gd5fxgq4uexxg_ecc_get_status)),
++      SPINAND_INFO("GD5F1GQ4RExxG",
++                   SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xc1),
++                   NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
++                   NAND_ECCREQ(8, 512),
++                   SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
++                                            &write_cache_variants,
++                                            &update_cache_variants),
++                   SPINAND_HAS_QE_BIT,
++                   SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
++                                   gd5fxgq4uexxg_ecc_get_status)),
++      SPINAND_INFO("GD5F2GQ4UExxG",
++                   SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xd2),
++                   NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
++                   NAND_ECCREQ(8, 512),
++                   SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
++                                            &write_cache_variants,
++                                            &update_cache_variants),
++                   SPINAND_HAS_QE_BIT,
++                   SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
++                                   gd5fxgq4uexxg_ecc_get_status)),
++      SPINAND_INFO("GD5F2GQ4RExxG",
++                   SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xc2),
++                   NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
++                   NAND_ECCREQ(8, 512),
++                   SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
++                                            &write_cache_variants,
++                                            &update_cache_variants),
++                   SPINAND_HAS_QE_BIT,
++                   SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
++                                   gd5fxgq4uexxg_ecc_get_status)),
+       SPINAND_INFO("GD5F1GQ4UFxxG",
+                    SPINAND_ID(SPINAND_READID_METHOD_OPCODE, 0xb1, 0x48),
+                    NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
+-- 
+2.35.1
+